CN103441100B - 显示基板及其制造方法、显示装置 - Google Patents

显示基板及其制造方法、显示装置 Download PDF

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CN103441100B
CN103441100B CN201310370380.3A CN201310370380A CN103441100B CN 103441100 B CN103441100 B CN 103441100B CN 201310370380 A CN201310370380 A CN 201310370380A CN 103441100 B CN103441100 B CN 103441100B
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electrode
layer
photoresist
pattern
area
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CN103441100A (zh
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段献学
白明基
徐德智
邹志翔
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Hefei BOE Optoelectronics Technology Co Ltd
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Priority to CN201510178332.3A priority Critical patent/CN104733384B/zh
Priority to CN201310370380.3A priority patent/CN103441100B/zh
Publication of CN103441100A publication Critical patent/CN103441100A/zh
Priority to PCT/CN2013/089981 priority patent/WO2015024350A1/zh
Priority to US14/381,823 priority patent/US10663820B2/en
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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
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    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
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    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362Active matrix addressed cells
    • G02F1/136227Through-hole connection of the pixel electrode to the active element through an insulation layer
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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    • G02F1/1362Active matrix addressed cells
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    • H01L27/1248Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
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    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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    • G02F1/134318Electrodes characterised by their geometrical arrangement having a patterned common electrode
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    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
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Abstract

本发明实施例提供一种显示基板及其制造方法、显示装置,涉及显示技术领域。方法包括在基板上形成刻蚀阻挡层图形和第一电极图形的步骤,形成所述刻蚀阻挡层图形和第一电极图形的步骤包括:依次形成刻蚀阻挡层薄膜和第一电极薄膜,通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形。本发明省去了刻蚀阻挡层图形单独形成的构图工艺,简化了工艺流程,节省了制作成本。本发明实施例用于制造显示装置。

Description

显示基板及其制造方法、显示装置
技术领域
本发明涉及显示技术领域,尤其涉及一种显示基板及其制造方法、显示装置。
背景技术
随着TFT-LCD(Thin Film Transistor Liquid Crystal Display,薄膜晶体管液晶显示器)显示技术的不断发展,越来越多的新技术不断地被提出和应用。基于ADS(Advanced Super Dimension Switch,AD-SDS,简称ADS,高级超维场转换技术)模式的TFT-LCD凭借其低功耗、宽视角等特点,得到了越来越多人们的关注。
ADS技术主要是通过同一平面内狭缝电极边缘所产生的电场以及狭缝电极层与板状电极层间产生的电场形成多维电场,使液晶盒内狭缝电极间、电极正上方所有取向液晶分子都能够产生旋转,从而提高了液晶工作效率并增大了透光效率。采用ADS技术的TFT-LCD产品不仅在画面品质上有所提高,且具有高分辨率、高透过率、宽视角、高开口率、低色差、无挤压水波纹等优点。
金属氧化物为有源层的薄膜晶体管较现有技术中的a-Si(非晶硅)为有源层薄膜晶体管相比,具有迁移率高、制备温度低、均一性好、对可见光透明和阈值电压低等特点,可实现高开口率和低功耗,未来应用前景广阔。
因此,集合ADS技术和金属氧化物薄膜晶体管优点的显示基板具有更广阔的应用前景。但是,金属氧化物易受H2,H2O等影响,为防止在后续湿法刻蚀工艺中刻蚀液对金属氧化物的影响,需要在金属氧化物表面另加刻蚀阻挡层进行保护。通常刻蚀阻挡层需要单独进行一次掩膜曝光工艺形成刻蚀阻挡层过孔,薄膜晶体管源漏极通过刻蚀阻挡层过孔与金属氧化物连接。这种结构,增加了掩膜板的成本和工艺的复杂性。
对于金属氧化物作为有源层的ADS型TFT-LCD而言,现有技术中通常需要通过7次构图工艺制造完成,而每一次构图工艺中又分别包括成膜、曝光、显影、刻蚀和剥离等工艺。构图工艺的次数过多将直接导致显示装置产品的成本上升,因此如何能够进一步减少构图工艺的次数也就成为了人们日益关注的问题。
发明内容
本发明的实施例提供一种显示基板及其制造方法、显示装置,可以减少在显示基板制造过程中构图工艺的次数,有效降低产品的生产成本。
为达到上述目的,本发明的实施例采用如下技术方案:
本发明实施例的一方面,提供一种显示基板制造方法,步骤包括:
提供一基板,在所述基板上栅绝缘层、有源层的图形;
依次形成刻蚀阻挡层薄膜和第一电极薄膜;
通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形。
本发明实施例的另一方面,提供一种显示基板,所述显示基板采用前述实施例提供的制造方法制造而成,所述显示基板至少包含栅绝缘层、有源层、刻蚀阻挡层和第一电极的图形,其中:
所述刻蚀阻挡层图形位于所述栅绝缘层与所述有源层之上且包括第一过孔区域、第一厚度区域和第二厚度区域;
所述刻蚀阻挡层图形的第一过孔区域具有贯穿整个刻蚀阻挡层以部分露出所述有源层的第一过孔图形;
所述刻蚀阻挡层图形的第一厚度区域位于所述栅绝缘层之上,对应于所述显示基板的第一电极;
所述刻蚀阻挡层图形的第二厚度区域位于除所述第一过孔区域与第一厚度区域之外的区域,第二厚度区域对应的刻蚀阻挡层厚度小于第一厚度区域的刻蚀阻挡层厚度;
所述第一电极图形位于所述刻蚀阻挡层的第一厚度区域之上且拥有与第一厚度区域相同的边界。
本发明实施例的又一方面,提供一种显示装置,所述显示装置包括如上所述的显示基板。
本发明实施例提供的显示基板以及制造方法、显示装置。本发明采用一次构图工艺同时形成刻蚀阻挡层与第一电极的图形。这样一来,与现有技术相比,省去了形成刻蚀阻挡层图形单独的构图工艺,可以将金属氧化物为有源层的ADS型显示基板制作过程中的构图工艺使用次数从7次减少到6次,从而简化了产品的生产步骤,显著降低了产品的生产成本。
附图说明
图1为本发明实施例提供的一种显示基板制造方法的流程示意图;
图2为本发明实施例提供的通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形的流程示意图;
图3为本发明实施例提供的另一种显示基板制造方法的流程示意图;
图4为基板上形成栅极和公共电极线的结构示意图
图5为图4所示的基板形成栅绝缘层的结构示意图;
图6为图5所示的基板形成有源层的结构示意图;
图7为图6所示的基板沉积刻蚀阻挡层薄膜、第一电极薄膜并涂覆正性光刻胶后的结构示意图;
图8为图7所示的基板进行曝光显影后的结构示意图;
图9为图8所示的基板进行第一次刻蚀工艺后的结构示意图;
图10为图9所示的基板进行第二次刻蚀工艺后的结构示意图;
图11为图10所示的基板中的光刻胶进行灰化后的结构示意图;
图12为图11所示的基板进行第三次刻蚀工艺后的结构示意图;
图13为图12所示的基板进行第四次刻蚀工艺后形成的第一过孔图形的一种结构示意图;
图14为图12所示的基板进行第四次刻蚀后形成的第一过孔图形的另一种结构示意图
图15为图13所示的基板进行光刻胶剥离、形成数据线、薄膜晶体管源极、薄膜晶体管漏极、导电沟道区域的结构示意图;
图16为图15所示的基板上形成带有第二过孔的钝化层图形的结构示意图
图17为本发明实施例提供的一种显示基板的结构示意图。
附图标记说明:
1—基板;                2—栅电极;             3—公共电极线;          4—栅绝缘层;
5—有源层;              6—刻蚀阻挡层;         7—第一电极薄膜;        8—正性光刻胶;
9—第一电极;            10—第一过孔;          11—薄膜晶体管源极;
12—薄膜晶体管沟道区域; 13—薄膜晶体管漏极;    14—钝化层;
15—第二过孔;           16—第二电极。
具体实施方式
需要说明的是:
1、本发明中所述的例如“X设置于Y上”或“X上设置有Y”中的“上”包含了X与Y接触,并且X位于Y的上方的意思,本发明中如附图所示,将基板定义为设置于最下方;
2、本发明所称的构图工艺包括光刻胶涂覆、掩模、曝光、显影、刻蚀、光刻胶剥离等工艺,光刻胶以正性光刻胶为例;
3、本发明中所述的“某某区域”是某某图形在基板上映射的区域,即该区域与某某图形具有相同的形状,例如栅线区域,即为栅线的图形在基板上的映射的区域,也可以理解为基板上将要设置栅线图形的区域。
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本发明实施例提供的一种显示基板的制造方法,如图1所示,所述显示基板的制造方法包括如下步骤:
S101、提供一基板,在所述基板上形成栅绝缘层、有源层的图形,形成所述栅绝缘层和有源层的图形的具体步骤包括:
S1011、在所述基板上形成栅绝缘层。
如图5所示,采用等离子体增强化学气相沉积(PECVD)或磁控溅射方法,在基板上沉积栅绝缘层薄膜,栅绝缘层4的材料可以采用氧化物、氮化物或氧氮化合物。
S1012、在栅绝缘层上形成有源层图形。
在完成步骤S1011的基板上沉积有源层薄膜,本发明实施例所述有源层具体为呈半导体特性的透明金属氧化物材料,可以为InGaZnO、InGaO、ITZO、AlZnO等材料中的至少一种。在金属氧化物薄膜上涂覆有一层光刻胶,通过具有特定图案的掩膜板进行曝光显影以使光刻胶产生图案,剥离掉未覆盖光刻胶处的金属氧化物后去除剩余的光刻胶,如图6所示,最终在栅绝缘层表面4上形成有源层5的图形。
S102、在有源层图形和栅绝缘层上沉积刻蚀阻挡层薄膜和第一电极薄膜。
具体的,如图7所示,采用等离子体增强化学气相沉积(PECVD)或磁控溅射方法在形成有金属氧化物图形5的基板上依次形成刻蚀阻挡层薄膜6和第一电极薄膜7。其中,刻蚀阻挡层薄膜可以是致密的氮化硅、氧化硅、氮氧化硅等材料,第一电极薄膜材料可以是ITO、ZnO、InGaZnO、InZnO、InGaO等透明导电材料。
S103、通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形。
具体的,在依次形成有刻蚀阻挡层薄膜和第一电极薄膜的基板上可以通过一次构图工艺形成该刻蚀阻挡层薄膜和第一电极的图形,该刻蚀阻挡层的图形位于有源层图形和栅绝缘层的表面,且覆盖薄膜晶体管的沟道区域,并且具有用于连接有源层与薄膜晶体管源漏极的第一过孔。
图2为本发明显示基板制造方法中形成刻蚀阻挡层和第一电极的图形构图工艺的具体流程图,在图1所示流程图中,所述步骤S103具体包括;
S1031、如图7所示,在所述第一电极薄膜上涂覆一层正性光刻胶8。
S1032、采用半色调或灰色调掩模板曝光,使光刻胶形成未曝光区域、部分曝光区域和完全曝光区域,其中,未曝光区域对应于第一电极所在区域;完全曝光区域对应于第一过孔图形所在区域;部分曝光区域对应于上述区域以外区域。
S1033、对光刻胶进行显影,未曝光区域的光刻胶厚度没有变化,形成光刻胶完全保留区域;部分曝光区域的光刻胶厚度变薄,形成光刻胶部分保留区域;完全曝光区域的光刻胶被完全去除,形成光刻胶完全去除区域。如图8所示,显影后的光刻胶的厚度包括三组不同厚度的区域,其中对应第一电极区域的光刻胶83厚度为t1,对应第一电极区域和第一过孔区域之外的区域的光刻胶82厚度为t2,对应第一过孔区域的光刻胶81厚度为t3,三个厚度值满足t1>t2,t3=0。
S1034、通过第一次刻蚀工艺完全刻蚀掉光刻胶完全去除区域对应的第一电极薄膜,露出此区域的刻蚀阻挡层薄膜,具体的,由于第一电极薄膜材料采用ITO、ZnO、InGaZnO、InZnO、InGaO等透明导电材料,工业上通常使用湿法刻蚀工艺刻蚀上述第一电极材料;刻蚀阻挡层薄膜采用致密的氮化硅、氧化硅、氮氧化硅等材料,而这些材料常常采用干法刻蚀工艺。因此为了保证完全刻蚀掉光刻胶完全去除区域对应的第一电极薄膜,可采用一定选择比的刻蚀液的湿法刻蚀工艺,刻蚀时间可以为所述光刻胶完全去除区域对应的第一电极膜层完全刻蚀时间的110%-300%,最终刻蚀完成后形成如图9所示图形。
S1035、通过第二次刻蚀工艺部分去除光刻胶完全去除区域对应的刻蚀阻挡层薄膜,如步骤S1034所述,第二次刻蚀工艺可以选用干法刻蚀工艺,为保证此次刻蚀只部分去除光刻胶完全去除区域对应的刻蚀阻挡层薄膜,具体干法刻蚀时间小于所述光刻胶完全去除区域对应的刻蚀阻挡层完全刻蚀时间,通过第二次刻蚀工艺最终形成如图10所示图形。
S1036、按照光刻胶部分保留区域的厚度灰化去除光刻胶,使光刻胶部分保留区域的光刻胶完全去除,光刻胶完全保留区域的光刻胶厚度减薄。灰化后的光刻胶图形如图11所示,与图10所示光刻胶图形相比,按照光刻胶部分保留区域的厚度灰化处理后,图10中光刻胶部分保留区域的光刻胶图形82被完全去除,露出第一电极薄膜。光刻胶完全保留区域83的光刻胶厚度减薄,最终形成光刻胶图形84。
S1037、通过第三次刻蚀工艺完全刻蚀掉光刻胶部分保留区域对应的第一电极薄膜。与第一次刻蚀工艺类似,第三次刻蚀工艺可选用湿法刻蚀工艺对光刻胶部分保留区域对应的第一电极薄膜进行刻蚀,以完全去除此区域的第一电极薄膜。经过第三次刻蚀工艺后最终形成如图12所示图形。应当注意的是,如背景介绍中所述,刻蚀阻挡层设置的目的在于防止应用湿法刻蚀工艺刻蚀金属时刻蚀液对有源层产生破坏。因此步骤S1035中第二次刻蚀工艺之所以部分去除光刻胶完全去除区域对应的刻蚀阻挡层薄膜是考虑到若完全刻蚀掉光刻胶完全去除区域对应的刻蚀阻挡层薄膜,步骤S1037中湿法刻蚀光刻胶部分保留区域对应的第一电极薄膜时,刻蚀液会对有源层产生影响。
S1038、通过第四次刻蚀工艺完全刻蚀掉光刻胶完全去除区域剩余的刻蚀阻挡层薄膜,露出有源层,光刻胶部分保留区域的刻蚀阻挡层薄膜按照S1037步骤后光刻胶完全去除区域对应的刻蚀阻挡层薄膜的厚度减薄,形成刻蚀阻挡层图形,刻蚀阻挡层图形具有连接有源层与薄膜晶体管源漏极的第一过孔。第四次刻蚀工艺可以为干法刻蚀,为了形成第一过孔图形,完全露出金属氧化物有源层,并且保证光刻胶部分去除区域剩余的刻蚀阻挡层薄膜经过刻蚀后仍有一定厚度以防止在后续刻蚀源漏金属时刻蚀液对沟道处的有源层产生影响,此次刻蚀工艺应控制刻蚀时间参数。具体刻蚀时间应大于光刻胶完全去除区域剩余的刻蚀阻挡层薄膜的完全刻蚀时间并且小于光刻胶部分保留区域对应的剩余刻蚀阻挡层薄膜的完全刻蚀时间。最终形成如图13所示图形,刻蚀阻挡层的图形包含第一过孔区域、第一厚度区域和第二厚度区域。第一过孔区域具有至少两个贯穿整个刻蚀阻挡层以部分露出所述有源层5的第一过孔10,所述第一过孔10边缘完全位于有源层5之上。由于第一过孔10的作用是用来电连接所述有源层5与薄膜晶体管的源漏电极,可以理解的是,只要能够实现上述功能,不同形状的第一过孔都是可以采用的,因此采用适当形状的掩膜板,按照S1031至S1038的步骤,也可以形成图14所述过孔图形。图14所示第一过孔10的边缘一端位于有源层5之上,另一端位于栅绝缘层之上。由于图14中所述的第一过孔可以使有源层5的侧面露出,所以较图13中的第一过孔可以获得更大的接触面积。所述刻蚀阻挡层图形6的第一厚度区域位于所述栅绝缘层4之上,对应于所述显示基板的第一电极9。所述刻蚀阻挡层图形6的第二厚度区域位于除所述第一过孔区域与第一厚度区域之外的区域,第二厚度区域对应的刻蚀阻挡层厚度小于第一厚度区域的刻蚀阻挡层厚度,需要指出的是,如图13或14所示,保护薄膜晶体管中有源层不受后续源漏金属刻蚀液影响的刻蚀阻挡层位于第二厚度区域。
S1039、去除剩余的光刻胶,露出第一电极图形。
本发明实施例提供的显示基板制造方法,采用一次构图工艺形成刻蚀阻挡层图形和第一电极图形,与现有技术相比,省去了刻蚀阻挡层单独形成的构图工艺。
进一步地,本发明实施例提供的显示基板制造方法,如图3所示,具体包括:
S201、在基板上形成栅线、栅电极以及公共电极线。
在显示基板的实际生产过程当中,基板具体可以是采用玻璃或透明树脂等具有一定坚固性的透明材料制成。在基板上需要采用一次构图工艺以形成栅线、栅电极以及公共电极线等结构的图形。
例如,可以采用等离子增强化学气相沉积(PECVD)、磁控溅射、热蒸发或其它成膜方法,在基板上形成金属层。其中,该金属层可以是钼、铝、铝铷合金、钨、铬、铜等金属形成的单层薄膜,也可以是以上金属多层形成的多层薄膜。在该金属层的表面形成有光刻胶,通过具有特定图案的掩膜板进行曝光显影以使光刻胶产生图案,剥离掉未覆盖光刻胶处的金属层,如图4所示,最终在基板1的表面形成栅线(图4中未示出)、栅电极2以及公共电极线3的图案。
S202、在基板、栅线、栅电极以及公共电极线上形成栅绝缘层。
S203、在栅绝缘层上形成有源层图形。
S204、在栅绝缘层上沉积刻蚀阻挡层薄膜和第一电极薄膜,通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形。
上述三个步骤S202、S203、S204与前述实施例中S101、S102、S103中的步骤相同,此处不再赘述。
S205、形成数据线、薄膜晶体管源极、薄膜晶体管漏极以及沟道区域。
在完成步骤S204的基板上沉积一层金属薄膜,金属薄膜可以采用Cr、W、Ti、Ta、Mo、Al、Cu等金属或合金,也可以采用由多层金属薄膜构成的复合薄膜。如图15所示,采用普通掩膜板通过构图工艺在形成有刻蚀阻挡层6和第一电极图形9的基板上形成数据线(图中未标出)、所述薄膜晶体管的源极11、所述薄膜晶体管的漏极13以及所述薄膜晶体管沟道区域12。所述薄膜晶体管的源极11、所述薄膜晶体管的漏极13通过第一过孔10与有源层5电连接,所述薄膜晶体管的漏极13搭接在第一电极9上。
S206、在形成有数据线、薄膜晶体管的源极以及薄膜晶体管的漏极的基板上形成含有第二过孔的钝化层,所述第二过孔贯穿钝化层、刻蚀阻挡层和栅绝缘层,露出公共电极线。
采用PECVD方法沉积钝化层14。钝化层14可以采用氧化物、氮化物或氧氮化合物,对应的反应气体可以为SiH4、NH3、N2的混合气体或SiH2Cl2、NH3、N2的混合气体。如图16所示,采用普通掩模板通过构图工艺形成第二过孔15,第二过孔15位于公共电极线3的上方,贯穿所述钝化层14、所述刻蚀阻挡层6与所述栅绝缘层4,并露出所述公共电极线3。本构图工艺中,还同时形成有栅线接口区域(栅线PAD)的栅线接口过孔(图中未标出)和数据线接口区域(数据线PAD)的数据线接口过孔(图中未标出)等图形。通过构图工艺形成栅线接口过孔和数据线接口过孔图形的工艺已广泛应用于目前的构图工艺中。
S207、通过构图工艺在形成有钝化层的基板上上形成第二电极图形,第二电极图形通过第二过孔与公共电极线3电连接。
如图17所示,在完成S206步骤的基板上,采用磁控溅射或热蒸发的方法,沉积一层第二电极薄膜,第二电极薄膜可以采用ITO、ZnO、InGaZnO、InZnO、InGaO等透明导电材料。采用普通掩模板通过构图工艺形成第二电极图形16,第二电极图形通过第二过孔15与公共电极线3电连接。
需要说明的是,在本发明实施例中,第一电极9为像素电极,其形状为板状;第二电极16为公共电极,其形状为狭缝状。第一电极9和第二电极16之间可以形成多维水平电场。
本发明实施例提供的显示基板制造方法,采用一次构图工艺形成刻蚀阻挡层图形和第一电极图形。这样一来,与现有技术相比,省去了刻蚀阻挡层的单独形成的构图工艺,可以将金属氧化物作为有源层的ADS型显示基板制作过程中的构图工艺使用次数从7次减少到6次,从而简化了产品的生产步骤,显著降低了产品的生产成本。
图17为本发明实施例提供的显示基板的截面图,参照图17,该显示基板包括:
形成在基板1上的栅线(图中未标出)、栅电极2、公共电极线3,栅线2和公共电极线3隔离设置。
形成在栅线、栅电极2以及公共电极线3之上并将栅线、栅电极以及公共电极线覆盖的栅绝缘层4,栅绝缘层4可采用等离子体增强化学气相沉积(PECVD)方法形成,栅绝缘层4材料可以采用氧化物、氮化物或氧氮化合物。
位于栅绝缘层4上的有源层5,其中,有源层5可以采用呈半导体特性的透明金属氧化物材料,例如,有源层可以为InGaZnO、InGaO、ITZO、AlZnO等材料中的至少一种。
位于所述栅绝缘层4与所述有源层5之上的刻蚀阻挡层图形6,刻蚀阻挡层6的作用是保护有源层5,以消除在刻蚀源漏金属层时刻蚀液对金属氧化物的影响,通常刻蚀阻挡层可以采用致密的氮化硅、氧化硅、氮氧化硅等材料。如图17所示,刻蚀阻挡层的图形包含第一过孔区域、第一厚度区域和第二厚度区域。第一过孔区域具有至少两个贯穿整个刻蚀阻挡层以部分露出所述有源层5的第一过孔10。由于第一过孔10的作用是用来电连接所述有源层5与薄膜晶体管的源漏电极,可以理解的是,只要能够实现上述功能,不同形状的第一过孔都是可以采用的,如图13所示,所述第一过孔10边缘可以完全位于有源层5之上;也可以如图14所示,所述第一过孔10的边缘一端位于有源层5之上,另一端位于栅绝缘层4之上。由于图14中所述的第一过孔可以使有源层5的侧面露出,所以较图13中的第一过孔,可以获得更大的接触面积。所述刻蚀阻挡层6的第一厚度区域位于所述栅绝缘层之上,对应于所述显示基板的第一电极。所述刻蚀阻挡层图形6的第二厚度区域位于除所述第一过孔区域与第一厚度区域之外的区域,第二厚度区域对应的刻蚀阻挡层厚度小于第一厚度区域的刻蚀阻挡层厚度,需要指出的是,如图17所示,保护薄膜晶体管中有源层不受源漏金属刻蚀液影响的刻蚀阻挡层位于第二厚度区域。
位于所述刻蚀阻挡层6的第一厚度区域之上的所述第一电极9,第一电极为像素电极,如前述显示基板制造方法的实施例所述,刻蚀阻挡层图形6和第一电极图形9在同一次构图工艺中形成,所以形成的第一电极图形9与刻蚀阻挡层的第一厚度区域的图形相对应,二者拥有相同的边界。
位于刻蚀阻挡层6和第一电极图形表面9的薄膜晶体管源极11、薄膜晶体管沟道区域12、和薄膜晶体管漏极13以及与薄膜晶体管源、漏极同时形成的数据线(图中未标出),所述薄膜晶体管的源极11、所述薄膜晶体管的漏极13通过第一过孔10与有源层5电连接,所述薄膜晶体管的漏极13搭接在第一电极9上。
位于所述数据线(图中未标出)、所述薄膜晶体管的源极11以及所述薄膜晶体管的漏极13的表面的含有第二过孔15的钝化层14,所述第二过孔15贯穿所述钝化层14、刻蚀阻挡层6和所述栅绝缘层4,露出公共电极线3。
位于所述钝化层表面的第二电极16,所述第二电极通过所述第二过孔15与所述公共电极线电连接3。
在本发明实施例中,第一电极9为像素电极,其形状为板状;第二电极16为公共电极,其形状为狭缝状。第一电极9和第二电极16之间可以形成多维水平电场。本发明实施例提供的显示基板,所述显示基板中蚀阻挡层图形和第一电极图形采用一次构图工艺形成。这样一来,与现有技术相比,省去了刻蚀阻挡层的MASK工艺,可以将以金属氧化物为有源层的ADS型显示基板制作过程中的构图工艺使用次数从7次减少到6次,从而简化了产品的生产步骤,显著降低了产品的生产成本。
需要说明的是,上述实施例中是以刻蚀阻挡层图形和第一电极图形通过一次构图工艺形成的显示基板为例进行的说明。可以理解的是,凡是通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形的显示基板都属于本发明所保护的范围,因此,本发明实施例提供的显示基板通过适当的变形也可以适用于其他类型的薄膜晶体管显示基板。
本发明实施例提供的显示装置,包括如上所述的显示基板。
该显示基板具体包括薄膜晶体管、第一电极和第二电极。其中,薄膜晶体管中的刻蚀阻挡层图形和第一电极图形是在一次构图工艺中形成的。
需要说明的是本发明所提供的显示装置可以为:液晶面板液晶电视、液晶显示器、数码相框、手机、平板电脑等具有任何显示功能的产品或部件。
本发明实施例提供的显示装置,包括显示基板,该显示基板采用一次构图工艺形成刻蚀阻挡层图形和第一电极图形。这样一来,刻蚀阻挡层图形和第一电极图形可以通过一次构图工艺加工得到,与现有技术相比,省去了刻蚀阻挡层单独形成的构图工艺,可以将ADS显示基板制作过程中的构图工艺使用次数从7次减少到6次,从而简化了产品的生产步骤,显著降低了产品的生产成本。
以上所述,仅为本发明的具体实施方式,但本发明的保护范围并不局限于此,任何熟悉本技术领域的技术人员在本发明揭露的技术范围内,可轻易想到变化或替换,都应涵盖在本发明的保护范围之内。因此,本发明的保护范围应以所述权利要求的保护范围为准。

Claims (9)

1.一种显示基板的制造方法,其特征在于,包括:
步骤1、提供一基板,在所述基板上形成栅绝缘层和有源层的图形;
步骤2、在完成步骤1的基板上依次形成刻蚀阻挡层薄膜和第一电极薄膜;
步骤3、通过一次构图工艺形成刻蚀阻挡层图形和第一电极图形;
其中步骤3具体包括:
步骤31、在所述第一电极薄膜上涂覆一层正性光刻胶;
步骤32、采用半色调或灰色调掩模板曝光显影,使光刻胶形成未曝光区域、部分曝光区域和完全曝光区域,其中,未曝光区域对应于第一电极图形所在区域;完全曝光区域对应于第一过孔图形所在区域;部分曝光区域对应于上述区域以外区域;
步骤33、显影处理后,未曝光区域的光刻胶厚度没有变化,形成光刻胶完全保留区域;部分曝光区域的光刻胶厚度变薄,形成光刻胶部分保留区域;完全曝光区域的光刻胶被完全去除,形成光刻胶完全去除区域;
步骤34、通过第一次刻蚀工艺完全刻蚀掉光刻胶完全去除区域对应的第一电极薄膜,露出此区域的刻蚀阻挡层薄膜;
步骤35、通过第二次刻蚀工艺部分去除光刻胶完全去除区域对应的刻蚀阻挡层薄膜;
步骤36、按照光刻胶部分保留区域的厚度灰化去除光刻胶,使光刻胶部分保留区域的光刻胶完全去除,光刻胶完全保留区域的光刻胶厚度减薄;
步骤37、通过第三次刻蚀工艺完全刻蚀掉光刻胶部分保留区域对应的第一电极薄膜;
步骤38、通过第四次刻蚀工艺完全刻蚀掉光刻胶完全去除区域剩余的刻蚀阻挡层薄膜,露出有源层,光刻胶部分保留区域的刻蚀阻挡层薄膜按照光刻胶完全去除区域剩余的刻蚀阻挡层薄膜的厚度减薄,形成刻蚀阻挡层图形,刻蚀阻挡层图形具有连接有源层与薄膜晶体管源漏极的第一过孔;
步骤39、去除剩余的光刻胶,露出第一电极图形。
2.根据权利要求1所述显示基板的制造方法,其特征在于,在形成所述栅绝缘层的步骤之前,所述方法还包括:
通过构图工艺在所述基板上形成栅线、栅电极以及公共电极线的图形。
3.根据权利要求2所述显示基板的制造方法,其特征在于,在形成所述刻蚀阻挡层图形和第一电极图形的步骤之后,所述方法还包括:
在形成有所述刻蚀阻挡层图形和第一电极图形的的显示基板上形成数据线、所述薄膜晶体管的源极、所述薄膜晶体管的漏极以及所述薄膜晶体管沟道区域,所述薄膜晶体管的源极、所述薄膜晶体管的漏极通过第一过孔与有源层电连接,所述薄膜晶体管的漏极搭接在第一电极上;
在形成有所述数据线、所述薄膜晶体管的源极、所述薄膜晶体管的漏极以及所述薄膜晶体管沟道区域的基板上形成具有第二过孔的钝化层,所述第二过孔贯穿所述钝化层、所述刻蚀阻挡层、所述栅绝缘层,露出所述公共电极线;
在所述钝化层上形成第二电极图形,所述第二电极图形通过所述第二过孔与所述公共电极线电连接。
4.一种采用权利要求1至3任一所述显示基板的制造方法制造的显示基板,所述显示基板至少包含栅绝缘层、有源层、刻蚀阻挡层和第一电极的图形,其特征在于,
所述刻蚀阻挡层图形位于所述栅绝缘层与所述有源层之上且包括第一过孔区域、第一厚度区域和第二厚度区域;
所述刻蚀阻挡层图形的第一过孔区域具有贯穿整个刻蚀阻挡层以部分露出所述有源层的第一过孔图形;
所述刻蚀阻挡层图形的第一厚度区域位于所述栅绝缘层之上,对应于所述显示基板的第一电极;
所述刻蚀阻挡层图形的第二厚度区域位于除所述第一过孔区域与第一厚度区域之外的区域,第二厚度区域对应的刻蚀阻挡层厚度小于第一厚度区域的刻蚀阻挡层厚度;
所述第一电极图形位于所述刻蚀阻挡层的第一厚度区域之上且拥有与第一厚度区域相同的边界。
5.根据权利要求4所述的显示基板,其特征在于,
所述刻蚀阻挡层中的第一过孔图形完全位于有源层之上。
6.根据权利要求4所述的显示基板,其特征在于,所述刻蚀阻挡层中的第一过孔图形位于有源层与栅绝缘层之上。
7.根据权利要求4所述的显示基板,其特征在于,所述显示基板还包括:
基板;
位于所述基板之上且位于所述栅绝缘层之下的栅线、栅电极以及公共电极线;
位于所述刻蚀阻挡层图形和第一电极图形表面的薄膜晶体管源极和薄膜晶体管漏极以及与薄膜晶体管源、漏极同时形成的数据线,所述薄膜晶体管的源极、所述薄膜晶体管的漏极通过第一过孔与有源层电连接,所述薄膜晶体管的漏极搭接在第一电极上;
位于所述数据线、所述薄膜晶体管的源极以及所述薄膜晶体管的漏极的表面的含有第二过孔的钝化层,所述第二过孔贯穿所述钝化层和所述栅绝缘层,露出所述公共电极线;
位于所述钝化层表面的第二电极,所述第二电极通过所述第二过孔与所述公共电极线电连接。
8.根据权利要求4至7任一所述的显示基板,其特征在于,所述有源层采用呈半导体特性的透明金属氧化物材料。
9.一种显示装置,其特征在于,所述显示装置包括如权利要求4至8任一所述的显示基板。
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