CN103403864A - 具有凝聚端子的半导体封装体 - Google Patents

具有凝聚端子的半导体封装体 Download PDF

Info

Publication number
CN103403864A
CN103403864A CN2012800100206A CN201280010020A CN103403864A CN 103403864 A CN103403864 A CN 103403864A CN 2012800100206 A CN2012800100206 A CN 2012800100206A CN 201280010020 A CN201280010020 A CN 201280010020A CN 103403864 A CN103403864 A CN 103403864A
Authority
CN
China
Prior art keywords
pad
metal
bonding
sintering
weld metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN2012800100206A
Other languages
English (en)
Other versions
CN103403864B (zh
Inventor
D·R·爱德华兹
S·P·格鲁姆
M·穆尔图扎
M·D·罗米格
K·哈亚塔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Publication of CN103403864A publication Critical patent/CN103403864A/zh
Application granted granted Critical
Publication of CN103403864B publication Critical patent/CN103403864B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4821Flat leads, e.g. lead frames with or without insulating supports
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49579Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582Metallic layers on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124Aluminium (Al) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147Copper (Cu) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48599Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48639Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48699Principal constituent of the connecting portion of the wire connector being Aluminium (Al)
    • H01L2224/487Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48738Principal constituent of the connecting portion of the wire connector being Aluminium (Al) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48739Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485Material
    • H01L2224/48505Material at the bonding interface
    • H01L2224/48799Principal constituent of the connecting portion of the wire connector being Copper (Cu)
    • H01L2224/488Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48838Principal constituent of the connecting portion of the wire connector being Copper (Cu) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48839Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/8385Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855Hardening the adhesive by curing, i.e. thermosetting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399Material
    • H01L2224/854Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85439Silver (Ag) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01013Aluminum [Al]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01028Nickel [Ni]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)
  • Powder Metallurgy (AREA)

Abstract

一种塑料封装体(100),在其中半导体芯片(101)通过粘合剂(102)附连到具有凝聚结构的金属条带(110a),并且电气连接到具有粒子结构的可键合且可焊接的金属条带(120);金属条带(120)接触凝聚结构的金属条带(110b),以形成垂直堆叠。焊料涂层(140)被焊接到凝聚金属条带(110a和110b)。

Description

具有凝聚端子的半导体封装体
技术领域
本发明总体涉及半导体器件和工艺,尤其是涉及用于接触半导体封装体的凝聚端子(agglomerate terminal)的结构和制造方法,所述结构和制造方法允许通过焊接和键合进行可靠的接触。
背景技术
半导体器件主要使用金属来在半导体芯片内的部件(例如晶体管)之间进行连通(communicate),以及在半导体芯片和外部器具(例如印刷电路板(PCB))之间进行连通。在半导体芯片内,可以通过如下步骤来形成金属线和互连:淀积溅射的、蒸发的和电镀的金属膜(例如铜、铝、钛和钨)并且将淀积的金属图形化成期望的电气元件,包括使用光刻、刻蚀和化学机械抛光(CMP)技术。
在半导体芯片与PCB之间,连通是通过通常被称为引脚框架的另一个金属结构进行的。引脚框架由金属片例如铜、铝和铁镍合金形成,这些金属片被冲压或刻蚀成芯片焊盘和期望的引脚配置,半导体芯片被附连到该芯片焊盘上。铜线或金线将芯片端子电气连接到引脚框架的引脚。
虽然上述的金属部件可以由各种金属元素制成,但是它们的共同特征是其多晶结构,所述多晶结构的特征在于各种尺寸和方向的金属颗粒(grain)由清晰的颗粒边界隔开。所述颗粒结构延伸整个金属迹线、金属线、金属插头、金属引脚和芯片焊盘。颗粒之间不存在空洞。
为了保护组装的半导体芯片和键合引线免受环境损害和处理损害,芯片和键合引线以及一部分引脚框架通常被包封在塑料封装中。某些部分的引脚框架被暴露在塑料外壳外面,以便通过焊点连接到PCB。焊接材料通常是金属合金,并且可以通过印刷或电镀被施加于PCB的封装体。
焊接印刷包括使用模板(stencil)和滚轴(squeegee)将悬浮在液体中的焊料粒子焊膏施加在工作表面上。之后是在高于焊料粒子的熔点的温度下回流焊膏,以便将焊料粒子熔化为液体状态。在冷却后,焊料呈现出固态形式,从而将所述半导体器件封装体物理连接且电气连接到PCB。即使在固态形式下,焊料也由多晶形式的金属间化合物和组分金属的同质混合物组成,尤其是在多次回流工艺后。当在适当温度和环境条件下被处理时,焊料主体通常不包含空洞或仅包含最小的空洞。
与使用电介质基板的封装相比,使用引脚框架的半导体器件封装通常具有更大的成本优势。即使这样,引脚框架的成本仍然是封装总体物料清单中的最大组成部分。近年来,已经提出了消除相对昂贵的引脚框架,用成本有效的替代品代替它的半导体封装的制造工艺。
该工艺包括将金属粒子焊膏和液体施加在载板上以形成短的、引脚般的条带的步骤。这个步骤之后是,在低于金属粒子熔化温度的温度下,将金属粒子烧结在每个条带中。即使粒子保持它们的固态,它们也联合从而生长为连续固体区域,从而形成适合取代传统引脚框架并且适合使用金或铜进行热超声引线键合工艺的金属结构。作为示例,在有机悬浮载色料(vehicle)中的银粉末已被用于在250℃与400℃之间的温度下在受控的气氛中烧制,从而生成适于高良率引线键合的表面。在烧制期间,悬浮载色料被烧掉,没有留下灰烬,并且银被烧结为高密度金属块。载板可以是不锈钢的,其在模塑后易于剥离,从而留下洁净的表面,准备好用于焊接。
发明内容
当具有作为常规引脚框架替代的烧结金属端子的模塑半导体封装将被用作无引脚器件,例如四方扁平封装无引线(QFN)或小外形无引线(SON)器件时,这些端子必须适于键合在封装内部上的引线并且适于附连在封装外面的焊料。申请人调查了用于将焊点接头附连到通过烧结金属粉末形成的金属结构的各种工艺,并最初遇到许多问题。当金属结构由银制成时,包含传统焊料或无铅合金的焊接凸点具有很强的溶解银以致凸点常常接触模制塑料的倾向。这些接触点失去机械性,并且通不过强度和可靠性试验。当金属结构由铜制成时,在剥离载板后,铜表面被迅速氧化,使得焊接凸点不能适当地润湿铜结构,得到的焊点接头是不牢固和不可靠的。
当申请人发现如下金属多层结构,该金属多层结构包括夹在可键合且可焊接金属的烧结后的纳米大小粒子的顶层与底层之间的微米大小和纳米大小金属粒子的烧结后的凝聚金属层时,申请人解决了在被用作替代常规引脚框架的半导体封装端子的烧结后的金属结构上形成可靠的键合和焊接触点的问题。凝聚金属的优选选择包括铜,并且可键合且可焊接金属的优选选择包括银。低成本且自图形化金属淀积技术的优选选择包括喷墨,丝网印刷和模版印刷。
在示例实施例中,大约30μm到40μm后的凝聚层由铜微米粒子和纳米粒子烧结而成,大约1μm到6μm厚的顶层和底层由银纳米粒子烧结而成。顶部银层有助于可靠地键合铜引线,以便连接到组装的半导体芯片,并且当被淀积在底层的焊料涂层被回流以便形成到凝聚铜层的可靠焊点接头时,底部银层被溶解。
另一个实施例是用于制造塑料半导体封装体的烧结端子从而替代常规引脚框架的高良率低成本方法。在选择可再用载板,例如由不锈钢或合金42制成的箔片后,将包括银纳米粒子的焊膏的第一组焊盘和第二组焊盘喷墨到箔片上。在淀积后,在大约250℃与400℃之间的温度下将纳米粒子烧结成厚度大约在1μm与6μm之间的固态银层。在下一个工艺步骤中,将掩膜与烧结后的银纳米粒子的焊盘对齐。在银焊盘的顶部,将包括铜微米粒子和铜纳米粒子的混合物的焊膏丝网印刷在第一组焊盘和第二组焊盘上。在淀积后,在大约250℃与400℃之间的温度下将微米和纳米粒子烧结成厚度大约在30μm与40μm之间的凝聚铜层。在第一组焊盘的凝聚铜层的顶部,喷墨并且烧结第二层银纳米粒子(层厚度大约为1μm到6μm),从而完成要封装的端子的多层堆叠。
利用粘合性聚合物,接着将半导体芯片附连在第二组焊盘的凝聚铜上。利用铜键合引线,将芯片电气连接到第一组焊盘的相应的第二银层。芯片、键合引线和金属层堆叠被包封在聚合物中,该聚合物被聚合以生成组装芯片的硬化板。载体箔从组装结构(通过剥离、推压或扭转)分离并且可以被再使用。
当焊料合金被涂覆在暴露的银端子上并被回流时,第一组和第二组焊盘的烧结层的银被全部溶解在焊料中,从而消除银迁移的任何危险。因此,焊料能够对凝聚铜层完美润湿,并且生成到封装端子的可靠焊点接头。
最后,硬化板可以被切割,以形成单片化的半导体器件封装体,从而准备好焊接到外部PCB。
附图说明
图1示出具有烧结的多层金属端子的塑料封装的半导体器件的示意性截面,所述烧结的多层金属端子具有凝聚和粒子结构,并且所述端子适于键合和焊料涂覆。
图2示出包括烧结的金属层堆叠的封装端子的放大显微照片,其中所述烧结的金属层具有凝聚和粒子结构。
图3-10示出用于制造半导体器件的工艺流程的某些步骤,其中垂直堆叠的金属结构包括微米粒子和纳米粒子的烧结的凝聚层。
具体实施方式
图1示出总体标为100的封装体的半导体器件,作为本发明的示例实施例。塑料封装体130容纳半导体芯片101,其采用粘合层102(通过高分子力)附连到金属条带110a。条带110a的结构是凝聚结构;替换地,条带110a可以具有粒子为主的结构。芯片101具有端子(键合焊盘)101a并电气连接到可键合且可焊接的金属条带120。条带120优选具有粒子结构;替换地,条带120可以具有凝聚结构。
正如这里所采用的,条带是材料与周围区域不同的细长材料带;其外形可以是线性的或不规则的;其厚度在其横向尺寸上可以是基本恒定的,或可以包括锥形部分;在特性上,条带等效于层。
由塑料化合物130形成的示例器件100的封装体优选具有表面平坦的长方体外形。由塑料化合物130形成的封装体的厚度131可以在大约0.5mm到1.0mm的范围内。在图1中长方体的平坦表面(包括器件端子)被标为132。在示例实施例中,多个第一端子150环绕第二端子151。第一端子150的长度优选在大约0.1mm到0.3mm的范围内,而第二端子151的长度优选在大约0.5mm到2.0mm的范围内,但是可以更长或更短。第一端子150和第二端子151被间隙152隔开。
正如这里所使用的,凝聚结构表示已经通过烧结步骤实现的各种大小的粒子的聚集合成物。条带110a是微米大小的金属粒子与纳米大小的粒子(优选具有相同金属)烧结的固体层。在图2的横截面中以625倍的放大率再现了凝聚结构的烧结条带的图示。作为示例,金属可以选自于包括铜、银、锌、镍、铟、镉、钴、铑、高温焊料以及金属填充的粘合剂的群组中;优选的选择是铜。条带110b包括与条带110a相同的金属和凝聚结构,因为条带110b以相同的工艺步骤制造(参见下面)。
正如这里所使用的,粒子结构表示已经通过烧结步骤实现的小的、分离粒子的合成物。可键合且可焊接金属条带120是烧结的纳米大小的粒子的固体层。作为示例,可键合且可焊接的金属可以选自于包括银、金、镍和钯的群组中;优选的选择是银。
在其他实施例中,层120可以更厚,并且可以具有通过烧结微米大小的金属粒子与纳米大小的金属粒子而得到的凝聚结构。
图1示出,粒子结构的可键合且可焊接金属条带120接触凝聚结构的第一金属条带(被标为110b),使得金属条带120在凝聚金属条带110b的顶部,并且条带120和110b形成金属层的垂直堆叠。因此,第一端子150包括垂直的多层金属堆叠。
图1示出焊料涂层140,其在与芯片101和金属条带120相对的条带表面处被分别焊接到条带110a和110b。焊料涂层的外部表面显示了在将焊料焊接到条带110a和110b的回流工艺期间,由液体焊料合金的表面张力确定的凸面轮廓。除了开始的焊料金属合金以外,涂层140在它们的基体中包括可焊接的金属。无论开始的焊料合金的成分是什么,在附连工艺流中进入液相之后,焊料合金部分地或完全地溶解最初被淀积且烧结作为凝聚结构的条带的基础的可焊接的金属条带。通过这个工艺,焊料合金可靠地形成对凝聚结构条带的紧密焊接接触。
作为溶解后的可焊接金属条带的残留物,平坦表面132示出了具有最初可焊接金属条带的尺寸和深度的凹痕。图1的每个端子具有凹痕。作为示例,图1示出了第一端子150的凹痕,其中用141表示凹痕长度,用142表示凹痕深度(细节参见下面的工艺描述)。
图1的器件100具有通过引线键合160电气连接到第一端子的芯片101。优选的键合引线由铜或铜合金制成;替换地,它们可以由金或铝或其合金制成。当使用球形键合技术时,球形键合点161优选附连到芯片,而至第二金属条带120(例如,银)的针脚键合点(stitch bond)162接触第一端子150(参见图2)。替换地,可以采用楔形键合。另一个替换的互连方法包括倒装芯片键合,其使用与条带120强力连接的金属凸点或由金属制成的接线柱;凸点金属的示例包括焊料和铜。如上所述,条带120优选是具有粒子结构或凝聚结构的烧结的银层;众所周知,银明显是可焊接的。
器件100的包封化合物130保护芯片101、键合线160、第一金属条带110a和110b以及第二金属条带120,并且其填充第一端子150与第二端子151之间的间隙152,从而在具有端子的封装侧面上形成平坦表面132。优选的材料是适于传递模塑的热塑成型化合物,例如具有无机填充物的基于环氧树脂的化合物。
图2是示例第一端子150在附连针脚键合点162之后但在附连焊料涂层之前的高度放大(625倍)的横截面。凝聚金属条带110b由烧结的铜制成,对于其横向延伸的绝大部分,具有大约40μm的厚度111,并且凝聚金属条带110b清晰地示出凝聚结构。在其他实施例中,厚度111可以在大约20μm与200μm之间。图2示出直径在大约2μm与7μm之间的多个铜粒子,其中大多数粒子是大约5μm的直径,这些铜粒子在烧结工艺中由纳米大小的铜粒子聚集在一起(在250℃到400℃下持续30分钟到60分钟,参见下面的工艺流程)。由于微米大小的粒子和纳米大小的粒子混合,得到的金属结构有时候被称为复合结构。除了这里示出的以外,其他粒子尺寸的分布也能够形成金属条带110b。有时可以观察到各种直径的小空洞,其散布在整个凝聚或混合结构中;然而,这些空洞不形成连续的开口链,从而例如伸展穿过厚度111。在铜条带110b的顶部表面和底部表面上是粒子结构的银条带120和401(包括随机的(occasional)空洞)。条带具有大约5μm的厚度142;在其他实施例中,厚度142可以在大约1μm与7μm之间。粒子结构的银条带由在大约250℃到400℃持续30分钟到60分钟(参见下面的工艺流程)的工艺下被烧结在一起的纳米大小的银粒子形成。
图3到10示出用于制造没有常规引脚框架的半导体器件的示例方法的工艺步骤。按顺序描述了该方法的示例实施的工艺步骤。在图3中所示的工艺的第一步骤包括固定具有厚度310的合适的载体301。载体301应当由如下可再用的基板材料制成,该基板材料为高温(在400℃与500℃之间)处理和制模提供稳定平台,但是同时对于所使用的金属和聚合物是无粘性的。载体材料对于产品的金属和聚合物应当仅具有低的分子间作用力;载体材料不应当是多孔的,并且仅提供可以被破坏的临时键合。载体材料甚至可以被涂覆有有助于移除最终产品的脱模剂。因此,剥离最终产品是可能的,并且载体可以被再使用。优选的材料包括但不限于聚四氟乙烯、聚酰亚胺、不锈钢、铜、镀铬铜、镀镍铜、铁镍合金,例如合金42TM。厚度310取决于所选择的材料;作为示例,对于合金42,厚度310可以是0.25mm;在这样的情况下,载体301类似于箔片。然而,在其他实施例中,载体301可以更厚,因而类似板。
在工艺流程的下一个步骤中,在载体上淀积导电图形,其用作封装的被暴露的引脚。在图4示出的工艺步骤中,具有厚度142的第一图形化的金属层被淀积在所选择的载体301上;所述图形包括导电条带401和402。优选的被淀积材料是混合在液体中的纳米大小金属粒子的焊膏;这些粒子在这里被称为纳米粒子。替换地,所述焊膏可以是微米大小和纳米大小粒子的混合物,有时候被称为复合混合物(hybrid mixture)(其得到凝聚为主的结构)。所述金属需要是可键合且可焊接的,并选自于包括银、金、镍和钯的群组中;优选的金属是银。淀积的方法选自于包括喷墨、模板印刷、丝网印刷和针式点胶组成的群组中;这个步骤的优选方法是喷墨,因为其可以产生粗糙度小于3μm的更加平坦的条带表面。所选择的技术允许所淀积的焊膏被图形化成第一焊盘401和第二焊盘402,使得一组第一焊盘401环绕每个第二焊盘402。由于焊膏应当产生表面是平坦为主的焊盘,所以焊膏的液体优选具有低的内部粘结性。第一焊盘401和第二焊盘402由间隙152间隔开。在图4示出的示例实施例中,第二焊盘402具有比第一焊盘401大的横向尺寸,但是在其他实施例中,它们的尺寸可以是相等的,或者焊盘402可以比焊盘401小。
替换地,焊膏可以包括微米大小的粒子以及纳米大小的粒子,使得得到的层将具有凝聚结构的特性。
在淀积后,金属纳米粒子(例如银纳米粒子)在低于金属元素的熔化温度的温度下,优选地在大约250℃与400℃之间进行烧结大约30分钟到60分钟。通过烧结,金属粒子彼此粘结在一起,并聚合为固态金属主体。得到的烧结后的焊盘(例如固态银)可以保留其粒子结构。焊盘401和402可以包括随机的空洞。焊盘厚度142的范围在1μm与7μm之间。
在如图5所示的下一个工艺步骤中,掩膜501与可键合且可焊接金属(如上所述,优选是银)的烧结后的纳米粒子的第一焊盘401和第二焊盘402对齐。当使用丝网印刷或模版印刷作为淀积技术时,掩膜通过这个技术形成。接着,在烧结后的纳米粒子的焊盘401和402上淀积焊膏,其中焊膏包括微米大小的金属粒子(所谓的微米粒子)和纳米大小的金属粒子(所谓的纳米粒子)的混合物。这些各种不同大小的金属粒子的混合物有时候被称为复合混合物。金属需要具有良好的导电性,并且选自于包括铜、银、锌、镍、铟、镉、钴、铑、高温焊料以及金属填充的粘合剂的群组中;优选的选择是铜。被淀积层的厚度111在20μm与200之间,优选地在大约40μm与60之间。利用之前的标识,在焊盘401上的混合层被标为110b,以及在焊盘402上的混合层被标为110a。在淀积后,除去掩膜。淀积方法选自于包括模板印刷、丝网印刷和喷墨的群组中;这个步骤的优选方法是丝网印刷。
在除去掩膜后,金属混合粒子,例如铜混合粒子,在低于所使用的金属的熔化温度的温度下,优选在大约250℃与400之间烧结30分钟到60分钟。得到的烧结后的焊盘是固态金属,例如具有凝聚结构的固态铜。焊盘401和402可以包括随机的空洞。一般来说,更高的烧结温度将得到更少的空洞。空洞不形成连续的路径,使得制模化合物(参见下面)不能达到与银层402的界面。
图6示出下一个工艺步骤。在凝聚层110b上淀积具有厚度142的第三图形化的金属条带120。层120的横向延伸几乎覆盖焊盘110b的顶部。优选的被淀积材料是混合在液体中的金属纳米粒子的焊膏。金属需要是可键合且可焊接的,并选自于包括银、金、镍和钯的群组中;优选的金属是银。淀积的方法选自于包括喷墨、模板印刷和丝网印刷的群组中;这个步骤的优选方法是喷墨。
在淀积后,金属纳米粒子,例如银纳米粒子,在大约250℃与400℃之间的温度下烧结大约30分钟到60分钟。得到的烧结后的焊盘是固态金属,例如固态银,并且可以保留其粒子结构。焊盘401和120可以包括随机的小空洞。焊盘厚度142的范围优选在1μm与7μm之间。如图6所示,得到的金属层的垂直堆叠650具有凝聚条带110a(例如铜),像可键合且可焊接金属(例如银)的两个较薄粒子条带120与401之间的三明治一样。
在如图7所示的下一个工艺步骤中,通过使用例如未固化的环氧树脂层102或自晶圆切割步骤后仍然邻接芯片的粘性膜,将具有端子(键合焊盘)101a的半导体芯片101粘性附连到凝聚金属层110a(例如铜)。替换地,芯片附连层可以被选择是导电和导热的,例如焊料。此后,芯片附连化合物102可以在大约150℃与250℃之间的温度下被固化(聚合)。
图8示出下一个工艺步骤:键合引线160从芯片端子101a跨到可键合且可焊接金属的第二层120,被定位在第一焊盘堆叠650的顶层。优选的键合引线由铜制成;替换的选择包括金和铝。引线160拱跨(arch)第一焊盘401与第二焊盘402之间的间隙152。当使用球形键合技术时,焊球161优选被附连到芯片端子101a,并且针脚162优选被附连到层120。替换的键合工艺在芯片端子101a与层120两者上形成焊球,其中在芯片端子101a或层120上形成针脚。当使用楔形键合技术时,层120再次具有针脚键合点。通常的键合温度在大约100℃与250℃之间。替换地,当使用倒装芯片键合时,金属凸点(例如焊点)被选择为有助于加强到具有粒子或凝聚结构的层的连接。
在如图9所示的下一个工艺步骤中,芯片101和键合引线160被包封在聚合物130中。同时,这个工艺步骤填充第一焊盘401与第二焊盘402之间的间隙152,并且在载体301上生成化合物的表面132。可以对可再用载体的各个条带执行包封步骤,或者如果组件被设定用于卷到卷(reel-to-reel)加工,则可以以卷到卷形式执行包封步骤。优选的包封技术是传递成型技术,其涉及大约170℃到180℃的温度。优选的热塑性化合物需要在150℃到200℃下聚合(硬化)几个小时。替换地,模制成型化合物可以是快速固化化合物,环氧树脂或热塑性塑料。在硬化化合物后,器件封装保持其长方形的外形。
在包封化合物130被硬化后,组件实现在图10中显示的工艺步骤,将载体301与第一层(焊盘)401和402的表面401a和402a分别分离,并且与在焊盘之间的间隙152中的硬化化合物分离。这个除去载体的步骤可以通过相对于被包封的组件进行剥离、推压或扭转载体301的技术执行。作为示例,图10示出剥离载体301的技术。在剥离后,载体301可以准备用于随后的再使用。除去载体的工艺步骤暴露了被烧结的固态金属条带401和402的金属表面401a和402a。在分离后,可再用载体在其被循环用于工艺流程的开始之前可能需要调节步骤,例如,清洗或施加脱模剂。
表面401a和402a可以通过压力触点电气连接到外部部件,如通常优选用于无引脚封装那样,或者它们可以经受下一个焊接工艺步骤,如适用于球栅阵列类型的封装那样。利用电解焊料电镀技术或无电镀工艺(如实用于镍、钯和金),施加焊料涂层。替换地,焊膏可以被筛选(screen)到焊盘上。接着,将焊料涂层加热到焊料回流温度,优选在大约200℃与260℃之间,这取决于所选择的焊料合金。当焊料是液体时,其溶解层401和402的可焊接金属;当这个金属是银时,其被焊料合金完全溶解,使得混合有银的合金可以可靠地润湿并且与焊盘110a和110b的凝聚金属交联。通过溶解银,消除了银迁移的任何风险。当焊盘110a和110b由凝聚铜制成时,少量的铜也可以被溶解在焊料中,从而增强了焊盘110a和110b到焊料的可靠接触。因此,建立了到具有凝聚金属结构的封装端子的可靠焊点接头。
由于经济效益的原因,在图3-10中概述的制造工艺流程优选地通过选择条带形式的载体来执行,使得可以并行处理多个芯片。在这种情况下,具有硬化的聚合物包封的条带类似于在除去载体后保留这个特性的刚性板。在这种情况下,工艺流程的最后步骤包括切割硬化板以便将每个芯片(每个芯片被组装在第二焊盘151上并由其相应的一组第一焊盘150环绕)单片化为包封的半导体器件100的步骤。优选的单片化方法是切割。应注意,在切割步骤中,由于与常规的半导体期间相比,器件100不包括金属引脚框架,因此刀片可以只走过硬化的塑料材料。
如上所述的相同原理可以被应用于具有多个芯片或堆叠芯片的产品,以及那些具有封装好的单个芯片的产品。这些原理也应用于如下封装,在其中第一和第二端子由具有粒子的焊膏烧结而成,使得它们均具有凝聚结构,以及应用于如下封装,在其中第一和第二端子由具有粒子的焊膏烧结而成,使得它们均具有粒子结构。它们也应用于如下封装,在其中半导体芯片通过倒装芯片技术被附连到可键合且可焊接金属的烧结后的条带。
本领域技术人员应当明白,在本发明的范围内,可以对上述实施例做出修改,并且许多其他的实施例也是可能的。

Claims (17)

1.一种半导体器件,其包括:
塑料封装体,在其中半导体芯片被粘性附连到具有凝聚结构的金属条带,并且被电气连接到具有粒子结构的可键合且可焊接金属条带。
2.根据权利要求1所述的器件,其中凝聚金属条带是用相同金属的纳米粒子烧结的金属微米粒子固态层。
3.根据权利要求2所述的器件,其中凝聚金属从由铜、银、锌、镍、铟、镉、钴、铑、高温焊料和金属填充的粘合剂组成的群组中选择。
4.根据权利要求2所述的器件,其中所述可键合且可焊接金属条带是烧结后的纳米粒子的固态层。
5.根据权利要求4所述的器件,其中所述可键合且可焊接金属从由银、金、镍和钯组成的群组中选择。
6.根据权利要求4所述的器件,其中所述粒子结构的可键合且可焊接金属条带接触凝聚结构的金属条带,使得它们形成具有凝聚金属结构条带的垂直堆叠。
7.根据权利要求6所述的器件,进一步包括被焊接到凝聚金属条带的焊料涂层。
8.一种半导体器件,其包括:
长方形的塑料封装体,所述封装体的一侧具有环绕第二端子的第一端子,所述第一端子和所述第二端子被间隙隔开;
所述第一端子,其包括具有凝聚结构的固态铜条带、被焊接到混合有银的焊料涂层的外部表面以及接触具有粒子结构的银层的内部表面;以及
所述第二端子,其包括具有凝聚结构的铜层、被焊接到混合有银的焊料涂层的外部表面以及半导体芯片粘性附连的内部表面。
9.根据权利要求8所述的器件,进一步包括:将所述半导体芯片键合到所述第一端子的烧结后的银纳米粒子的层的引线;以及包封芯片和引线并且填充第一和第二端子之间的间隙的聚合物。
10.一种用于制造半导体器件的方法,其包括:
在载体条带上形成第一层烧结后的可键合且可焊接金属,所述第一层被图形化成第一焊盘和第二焊盘,一组第一焊盘环绕每个第二焊盘,所述第一焊盘和所述第二焊盘被间隙隔开;以及
在所述第一焊盘和所述第二焊盘的第一层烧结后的可键合且可焊接金属上垂直形成图形化的凝聚金属层;以及
在所述第一焊盘的凝聚金属层上垂直形成第二层烧结后的可键合且可焊接金属。
11.根据权利要求10所述的方法,进一步包括:
将半导体芯片粘性附连到每个第二焊盘的凝聚金属层上,所述芯片具有端子;
使键合引线跨越所述间隙,从每个芯片的端子到相应的一组第一焊盘的第二层可键合且可焊接金属;
将芯片和引线包封在聚合物中,并且同时由化合物填充所述间隙,接着硬化所述化合物;以及
将所述载体条带与第一和第二焊盘的第一层以及在所述焊盘之间的间隙中的硬化的化合物分离,由此暴露组装芯片的硬化板的表面。
12.根据权利要求11所述的方法,进一步包括,在分离步骤后,进行以下步骤:用焊料合金涂覆所述第一和第二焊盘的暴露的第一层,接着回流所述焊料合金,由此将所述第一层的可焊接金属溶解在所述焊料合金中,并且使合金与凝聚金属层交联。
13.根据权利要求12所述的方法,进一步包括以下步骤:切割硬化板,从而单片化具有相应的一组环绕的第一焊盘的每个第二焊盘,作为包封好的半导体器件。
14.根据权利要求13所述的方法,其中所述可键合且可焊接金属从包括银、金、镍和钯的群组中选择;并且所述凝聚金属从包括铜、银、锌、镍、铟、镉、钴、铑、高温焊料以及金属填充的粘合剂的群组中选择。
15.根据权利要求10所述的方法,其中形成烧结后的可键合且可焊接金属的第一层包括以下步骤:
在载体条带上淀积包括可键合且可焊接金属的纳米粒子的焊膏,所淀积的焊膏被图形化成第一焊盘和第二焊盘,一组第一焊盘环绕每个第二焊盘,所述第一焊盘和所述第二焊盘被间隙隔开;以及
烧结纳米粒子,以生成可键合且可焊接金属的固态层的焊盘。
16.根据权利要求10所述的方法,其中形成所述凝聚金属层包括:
将掩膜与可键合且可焊接金属的烧结后的纳米粒子的焊盘对齐;
在所述第一和第二焊盘的烧结后的纳米粒子的焊盘上淀积包括金属微米粒子和金属纳米粒子的混合物的焊膏;
除去所述掩膜;以及
烧结金属微米粒子和纳米粒子,以生成堆叠在可键合且可焊接金属的烧结后的粒子的焊盘上的凝聚结构的固态层。
17.根据权利要求10所述的方法,其中形成第二层烧结后的可键合且可焊接金属的步骤包括以下步骤:
在所述第一焊盘的凝聚金属的焊盘上淀积包括可键合且可焊接金属的纳米粒子的焊膏;以及
烧结所述纳米粒子,以生成堆叠在凝聚金属层上的可键合且可焊接金属的固态层。
CN201280010020.6A 2011-02-23 2012-02-23 具有凝聚端子的半导体封装体 Active CN103403864B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201161445630P 2011-02-23 2011-02-23
US61/445,630 2011-02-23
US13/351,579 2012-01-17
US13/351,579 US8643165B2 (en) 2011-02-23 2012-01-17 Semiconductor device having agglomerate terminals
PCT/US2012/026378 WO2012116218A2 (en) 2011-02-23 2012-02-23 Semiconductor packages with agglomerate terminals

Publications (2)

Publication Number Publication Date
CN103403864A true CN103403864A (zh) 2013-11-20
CN103403864B CN103403864B (zh) 2016-07-06

Family

ID=46652081

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201280010020.6A Active CN103403864B (zh) 2011-02-23 2012-02-23 具有凝聚端子的半导体封装体

Country Status (4)

Country Link
US (2) US8643165B2 (zh)
JP (1) JP6116488B2 (zh)
CN (1) CN103403864B (zh)
WO (1) WO2012116218A2 (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742265A (zh) * 2014-12-24 2016-07-06 意法半导体股份有限公司 制造表面贴装半导体器件的封装的方法及半导体器件
CN107960132A (zh) * 2015-05-04 2018-04-24 由普莱克斯有限公司 带有印刷成形封装部件和导电路径再分布结构的引线载体
CN108475645A (zh) * 2016-01-13 2018-08-31 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN108807301A (zh) * 2017-05-01 2018-11-13 恩智浦美国有限公司 使用烧结附着的封装微电子组件安装
CN110391143A (zh) * 2019-07-02 2019-10-29 东莞链芯半导体科技有限公司 半导体封装结构及其封装方法
CN113814597A (zh) * 2021-10-28 2021-12-21 株洲中车时代半导体有限公司 电子器件的焊接方法

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103907185B (zh) * 2011-08-11 2016-10-19 联达科技控股有限公司 具有多材料印刷形成的包装部件的引线载体
US8586480B1 (en) * 2012-07-31 2013-11-19 Ixys Corporation Power MOSFET having selectively silvered pads for clip and bond wire attach
KR101988890B1 (ko) * 2012-10-30 2019-10-01 한국전자통신연구원 솔더 온 패드의 제조방법 및 그를 이용한 플립 칩 본딩 방법
JP6146642B2 (ja) * 2012-11-30 2017-06-14 大日本印刷株式会社 半導体装置用基板の製造方法および樹脂封止型半導体装置の製造方法
US8815648B1 (en) 2013-04-01 2014-08-26 Texas Instruments Incorporated Multi-step sintering of metal paste for semiconductor device wire bonding
US9978667B2 (en) * 2013-08-07 2018-05-22 Texas Instruments Incorporated Semiconductor package with lead frame and recessed solder terminals
US11217515B2 (en) * 2014-09-11 2022-01-04 Semiconductor Components Industries, Llc Semiconductor package structures and methods of manufacture
US10847691B2 (en) * 2014-12-11 2020-11-24 Luminus, Inc. LED flip chip structures with extended contact pads formed by sintering silver
KR20180002812A (ko) * 2015-05-04 2018-01-08 이오플렉스 리미티드 리드 캐리어 구조, 그리고 이로부터 다이 부착 패드들 없이 형성되는 패키지들
US10727085B2 (en) * 2015-12-30 2020-07-28 Texas Instruments Incorporated Printed adhesion deposition to mitigate integrated circuit package delamination
JP6963602B2 (ja) * 2017-04-21 2021-11-10 三井化学株式会社 半導体基板の製造方法
FR3083920A1 (fr) * 2018-07-13 2020-01-17 Linxens Holding Procede de fabrication de boitiers de composant electronique et boitier de composant electronique obtenu par ce procede
US11562947B2 (en) * 2020-07-06 2023-01-24 Panjit International Inc. Semiconductor package having a conductive pad with an anchor flange
CN114883284A (zh) * 2022-03-25 2022-08-09 清华大学 碳化硅芯片的耐高温封装结构及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040245648A1 (en) * 2002-09-18 2004-12-09 Hiroshi Nagasawa Bonding material and bonding method
US20060017069A1 (en) * 2002-02-18 2006-01-26 Robert Bergmann Electronic component with an adhesive layer and method for the production thereof
CN1744308A (zh) * 2004-09-04 2006-03-08 三星Techwin株式会社 倒装芯片半导体封装件及其制造方法
US20080145607A1 (en) * 2006-12-18 2008-06-19 Renesas Technology Corp. Semiconductor apparatus and manufacturing method of semiconductor apparatus

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5318651A (en) * 1991-11-27 1994-06-07 Nec Corporation Method of bonding circuit boards
JP2001250884A (ja) * 2000-03-08 2001-09-14 Sanyo Electric Co Ltd 回路装置の製造方法
AU2001290266A1 (en) 2000-10-25 2002-05-06 Harima Chemicals, Inc. Electroconductive metal paste and method for production thereof
DE10245451B4 (de) * 2002-09-27 2005-07-28 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip, der flexible Chipkontakte aufweist, und Verfahren zur Herstellung desselben, sowie Halbleiterwafer
US7524748B2 (en) * 2003-02-05 2009-04-28 Senju Metal Industry Co., Ltd. Method of interconnecting terminals and method of mounting semiconductor devices
WO2004103043A1 (ja) 2003-05-16 2004-11-25 Harima Chemicals, Inc. 銅微粒子焼結体型の微細形状導電体の形成方法、該方法を応用した銅微細配線ならびに銅薄膜の形成方法
EP1666175B1 (en) 2003-09-12 2019-05-15 SIJTechnology, Inc. Metal nano particle liquid dispersion capable of being sprayed in fine particle form and being applied in laminated state
US8053171B2 (en) * 2004-01-16 2011-11-08 Semiconductor Energy Laboratory Co., Ltd. Substrate having film pattern and manufacturing method of the same, manufacturing method of semiconductor device, liquid crystal television, and EL television
CN100587855C (zh) 2004-06-23 2010-02-03 播磨化成株式会社 导电金属膏
US7550319B2 (en) * 2005-09-01 2009-06-23 E. I. Du Pont De Nemours And Company Low temperature co-fired ceramic (LTCC) tape compositions, light emitting diode (LED) modules, lighting devices and method of forming thereof
US7982307B2 (en) * 2006-11-22 2011-07-19 Agere Systems Inc. Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate
US7955901B2 (en) * 2007-10-04 2011-06-07 Infineon Technologies Ag Method for producing a power semiconductor module comprising surface-mountable flat external contacts
US7836586B2 (en) 2008-08-21 2010-11-23 National Semiconductor Corporation Thin foil semiconductor package
US7754533B2 (en) 2008-08-28 2010-07-13 Infineon Technologies Ag Method of manufacturing a semiconductor device
US9041228B2 (en) * 2008-12-23 2015-05-26 Micron Technology, Inc. Molding compound including a carbon nano-tube dispersion
JP5617210B2 (ja) * 2009-09-14 2014-11-05 デクセリアルズ株式会社 光反射性異方性導電接着剤及び発光装置
JP5532419B2 (ja) * 2010-06-17 2014-06-25 富士電機株式会社 絶縁材、金属ベース基板および半導体モジュール並びにこれらの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060017069A1 (en) * 2002-02-18 2006-01-26 Robert Bergmann Electronic component with an adhesive layer and method for the production thereof
US7476981B2 (en) * 2002-02-18 2009-01-13 Infineon Technologies Ag Electronic module with layer of adhesive and process for producing it
US20040245648A1 (en) * 2002-09-18 2004-12-09 Hiroshi Nagasawa Bonding material and bonding method
CN1744308A (zh) * 2004-09-04 2006-03-08 三星Techwin株式会社 倒装芯片半导体封装件及其制造方法
US20080145607A1 (en) * 2006-12-18 2008-06-19 Renesas Technology Corp. Semiconductor apparatus and manufacturing method of semiconductor apparatus

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105742265A (zh) * 2014-12-24 2016-07-06 意法半导体股份有限公司 制造表面贴装半导体器件的封装的方法及半导体器件
CN105742265B (zh) * 2014-12-24 2018-11-09 意法半导体股份有限公司 制造表面贴装半导体器件的封装的方法及半导体器件
CN107960132A (zh) * 2015-05-04 2018-04-24 由普莱克斯有限公司 带有印刷成形封装部件和导电路径再分布结构的引线载体
CN108475645A (zh) * 2016-01-13 2018-08-31 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN108475645B (zh) * 2016-01-13 2023-07-18 德克萨斯仪器股份有限公司 用于封装应力敏感mems的结构和方法
CN108807301A (zh) * 2017-05-01 2018-11-13 恩智浦美国有限公司 使用烧结附着的封装微电子组件安装
CN108807301B (zh) * 2017-05-01 2024-01-26 恩智浦美国有限公司 使用烧结附着的封装微电子组件安装
CN110391143A (zh) * 2019-07-02 2019-10-29 东莞链芯半导体科技有限公司 半导体封装结构及其封装方法
CN113814597A (zh) * 2021-10-28 2021-12-21 株洲中车时代半导体有限公司 电子器件的焊接方法

Also Published As

Publication number Publication date
US20140038358A1 (en) 2014-02-06
WO2012116218A2 (en) 2012-08-30
CN103403864B (zh) 2016-07-06
US20120211889A1 (en) 2012-08-23
US8643165B2 (en) 2014-02-04
US8716068B2 (en) 2014-05-06
WO2012116218A3 (en) 2012-11-22
JP2014509455A (ja) 2014-04-17
JP6116488B2 (ja) 2017-04-19

Similar Documents

Publication Publication Date Title
CN103403864B (zh) 具有凝聚端子的半导体封装体
US20210005537A1 (en) Sintered Metal Flip Chip Joints
KR100787678B1 (ko) 플립칩 내장형 리드프레임 패키지 및 그 처리과정
TWI325626B (en) Method for packaging a semiconductor device
US8033016B2 (en) Method for manufacturing an electrode and electrode component mounted body
US10130995B2 (en) Method for manufacturing metal powder
JPH04234139A (ja) 半導体チップの基板への直接取付け法
US7427558B2 (en) Method of forming solder ball, and fabricating method and structure of semiconductor package using the same
US20100309641A1 (en) Interposer substrate, lsi chip and information terminal device using the interposer substrate, manufacturing method of interposer substrate, and manufacturing method of lsi chip
JP2002124533A (ja) 電極材料、半導体装置及び実装装置
CN100485895C (zh) 内埋式晶片封装结构及其工艺
US8368234B2 (en) Semiconductor device, production method for the same, and substrate
CN100492627C (zh) 芯片结构、芯片封装结构及其工艺
CN101770994A (zh) 具有金属突点的半导体封装基板
CN108183091A (zh) 一种封装结构及其工艺方法
CN104392941A (zh) 形成倒装芯片半导体封装的方法
CN104392940A (zh) 形成倒装芯片半导体封装的方法
US20090026633A1 (en) Flip chip package structure and method for manufacturing the same
KR102222146B1 (ko) 저비용 전도성 금속 구조체를 이용한 반도체 패키지
CN103493191B (zh) 电子元器件模块的制造方法及电子元器件模块
CN103325697B (zh) 半导体封装结构的制作方法
CN209843696U (zh) 利用导电性金属结构体的半导体封装
CN101740410B (zh) 芯片封装结构的制程
CN101510519A (zh) 覆晶式四方扁平无引脚型态封装结构及其制程
CN106298749A (zh) 发光二极管、电子器件及其制作方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant