CN105742265B - 制造表面贴装半导体器件的封装的方法及半导体器件 - Google Patents

制造表面贴装半导体器件的封装的方法及半导体器件 Download PDF

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CN105742265B
CN105742265B CN201510575044.1A CN201510575044A CN105742265B CN 105742265 B CN105742265 B CN 105742265B CN 201510575044 A CN201510575044 A CN 201510575044A CN 105742265 B CN105742265 B CN 105742265B
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preset
die pad
electronic device
contact
sintering
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CN105742265A (zh
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F·V·丰塔纳
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STMicroelectronics SRL
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STMicroelectronics SRL
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Abstract

一种用于制造表面贴装半导体器件的封装的方法及半导体器件，其包括半导体材料主体和包括多个接触端子的引线框架。所述多个接触端子电连接到所述半导体主体。所述接触端子由烧结材料制成。

Description

制造表面贴装半导体器件的封装的方法及半导体器件
优先权声明
本申请要求2014年12月24日提交的申请号为TO2014A001106的意大利专利申请的优先权，所述申请的全部内容在法律允许最大范围内通过引用合并于此。
技术领域
本发明涉及用于制造表面贴装半导体器件的封装的方法以及相应的半导体器件。
背景技术
半导体器件，如集成电路和微电子机械系统(MEMS)器件密封在相应封装内，所述封装执行保护功能及与外部世界的交互功能。例如，现有的已知封装能够在印刷电路板(PCB)上实现所谓的表面贴装。
更详细地，例如表面贴装封装包括所谓的“方形扁平无引线”(QFN)类型封装，也称为“微型引线框架”(MLF)或“小外形无引线”(SON)封装。
例如关于QFN类型封装通常包括树脂区，树脂区内部是引线框架，引线框架依次形成至少一排端子，所述端子从封装底表面暴露出来和/或延伸出来。发明人为费利克斯(Felix)等人的公开号为2005/0116321的美国专利申请描述了包含引线框架的封装的制造方法示例，所述专利申请的全部内容通过引用合并于此。
传统上，引线框架被制成带材，随后在制造过程中使用这些带材。因此，尽管现在从引线框架带材开始生产封装的技术比较稳定，但是这些技术仍然相对成本昂贵。此外，利用这些技术获得的封装相对较重。
半导体器件封装需要至少部分地克服现有技术的缺陷。
发明内容
表面贴装电子器件包括半导体材料主体和引线框架，所述引线框架包括电连接到所述半导体材料主体的多个接触端子。所述多个接触端子由烧结材料制成。
在一个实施例中，所述引线框架包括布置在绝缘区的多个焊盘和多个迹线。所述多个迹线中的每个迹线将对应的焊盘电连接到所述多个接触端子中的对应的接触端子。
在一个可选实施例中，所述表面贴装电子器件包括裸片焊盘，并且所述半导体材料主体布置在所述裸片焊盘上并通过焊线电连接到所述多个接触端子。
制造表面贴装电子器件的方法包括在支承结构上形成由可烧结材料制成的多个预置触点区。将包括半导体主体的芯片机械地耦合到所述支承结构。烧结所述可烧结材料，使得每个预置触点区形成对应的烧结预置触点。
附图说明
为了更好地理解本发明，现在参照附图并且仅以非限定的实例的方式描述本发明的优选实施例，其中：
图1至图3为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的截面图；
图4、图5和图7为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图；
图6为沿图5中示出的剖面线VI-VI绘制的图5所示中间结构的部分横截面的示意图；
图8A为所述制造方法的实施例的处理步骤中的中间结构的部分的侧视示意图；
图8B为图8A所示的同一步骤中的中间结构的部分的示意性的顶视图；
图9和图10为所述制造方法的实施例的连续处理步骤中的中间结构的各部分的侧视示意图；
图11至图14为所述制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的截面图；
图15和图16为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图；
图17和图18为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图；
图19至图25为所述制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的截面图；
图26和图34为半导体器件的示意性的截面图；
图27和图28为所述制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的截面图；
图29和图30为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图；
图31为三维电子结构的示意性的截面图；
图32和图33为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图；以及
图35和图36为本发明制造方法的实施例的连续处理步骤中的中间结构的各部分的示意性的顶视图。
具体实施方式
图1示出了水溶性支承结构2，其包括第一层4和第二层6，在下文中分别称为第一支承层4和第二支承层6。各示意图都不是按比例绘制的。
第一支承层4和第二支承层6布置为彼此接触并形成已知类型的粘合带。第一支承层4例如由聚乙酸乙烯酯(PVA)或聚乙烯吡咯烷酮(PVP)的薄膜形成，其厚度例如可以介于10μm和30μm之间。第二支承层6例如由可溶于水的压敏粘附膜(PSA膜)形成，其厚度可以介于20μm和30μm之间。更具体地，第二支承层6例如可以由包含聚乙酸乙烯酯和硅酸钠混合物的凝胶形成。
如图1所示，按照本发明制造方法，支承结构2机械地耦合到作为加强构件的板8，板8例如由钢制成并且厚度例如可以介于0.2mm和0.5mm之间。
更具体地，支承结构2是叠层结构；即支承结构2以使第二支承层6接触板8的方式地布置在板8上。为了消除在加热第二支承层6后可能产生的气泡，例如在压力5bar、温度200℃的增压炉中实现叠层结构。这样，由于第二支承层6的粘合作用，第一支承层4粘附到板8，如图2所示。因而形成组件10，即中间结构，其厚度例如可以介于0.23mm和0.56mm之间。
接下来，如图3所示，像例如通过紫外线照射固化的丙烯酸粘胶树脂的介电材料制成的第三层12形成在第一支承层4的顶部。可以采用已知方法形成第三层12，例如通过丝网印刷和后续固化的方法。此外，第三层12的厚度可以介于10μm和30μm之间。
另外，如图4所示，第三层12形成多个介电区。特别地，如图4所示，第一介电区14和第二介电区16在下文中分别称为第一基区14和第二基区16。通常，第一基区14和第二基区16彼此相同。
第一基区14和第二基区16彼此物理分离并横向交错布置。此外，在顶视图中，第一基区14和第二基区16中的每个基区形状都类似邮票；也就是具有矩形或方形的主体(分别标识为15和17)，从矩形或方形周边向外延伸有多个齿部，即突出部分，各齿部也是矩形或方形。在图4中，第一基区14的齿部标识为19，而第二基区16的齿部标识为21。
所述齿部依次限定多个凹槽，所述凹槽在顶部处打开并在底部处由第一支承层4界定。在图4中，第一基区14限定的凹槽标识为23，而第二基区16限定的凹槽标识为25。
为了简便起见，除非特别说明，通过描述包括第一基区14的中间结构10的各部分来描述本发明制造方法的操作步骤。
如图5所示，随后形成导电类型的多个预置触点区30、多个预置迹线区32和多个预置焊盘区34。
详细地，通过丝网印刷工艺，利用已知类型的相同烧结浆料形成预置触点区30、预置迹线区32和预置焊盘区34；例如，可以通过瞬时液相烧结(TPLS)来形成烧结浆料。
更详细地，所述烧结浆料可以包括具有例如直径介于10μm和30μm之间的等效直径的金属微粒。
进一步详细地，所述烧结浆料例如可以包括由环氧树脂粘合的铜和锡微粒。在本实例中，如果将所述微粒置于温度220℃的低氧含量环境中，所述微粒会形成铜-锡金属间化合物。再通过一个实例，通过将铜微粒镀银并在溶剂中分离也可以形成烧结浆料。在本实例中，如果烧结浆料加热到170℃，则所述溶剂会蒸发。
更详细地，为了接触下面的第一支承层4，每个预置触点区30都形成在第一基区14的对应的凹槽23内。
更详细地，如图6所示，每个预置触点区30包括底部和顶部，所述底部接触第一支撑层4并在对应的成对齿部19之间延伸，所述顶部覆盖在所述底部上并横向延伸直到其部分地覆盖在前述成对齿部19上。特别地，所述顶部包括第一横向子部和第二横向子部，所述子部分别在前述成对齿部19的两个齿部上面延伸。第一横向子部和第二横向子部中的每个子部的宽度例如可以为0.1mm。这样，当相应位置受到移除底层(在下文中描述)引起的应力时，或者当相应位置受到因预置触点区30与周围环境的热膨胀系数(CTE)存在差异而引起的热机械应力时，预置触点区30能够保持在中间结构10内的相应位置。
对于预置焊盘区34，通常它们的数量与预置触点区30的数量相等。此外，预置焊盘区34形成在第一基区14顶部，在这种情况下它们能够直接接触。特别地，通常预置触点区30沿虚拟方形的各边布置，并布置在第一基区14的主体15的中央部。
对于预置迹线区32，通常预置迹线区32的数量与预置触点区30的数量相等。此外，预置迹线区32形成在第一基区14顶部，在这种情况下实现直接接触。特别地，每个预置迹线区32布置在对应的预置焊盘区34和对应的预置触点区30之间，在这种情况下实现直接接触。因此，预置迹线区32形成大致沿放射状延伸的多个臂，所述臂在每个预置焊盘区34和对应的预置触点区30之间形成电气连接。
接下来，如图7所示，采用已知方法进行烧结过程。详细地，对中间结构10进行热处理。例如，在烧结浆料包含铜和锡微粒的情况下，可以在30分钟内使热处理温度从25℃逐渐升高至215℃，然后保持温度215℃持续75分钟。进一步地，可以在通过连续注入氮气获得的低氧含量(例如，低于百万分之二百(ppm))的受控环境中进行热处理。可选择地，如果烧结浆料包含镀银的铜微粒，可以在170℃温度下进行具有30分钟的持续时间的热处理。
完成烧结后，每个预置触点区30形成对应的预置触点36。此外，每个预置迹线区32形成对应的迹线38，同时每个预置焊盘区34形成对应的焊盘40。预置触点36、迹线38和焊盘40一起构成引线框架并一起形成单一烧结区，所述单一烧结区的厚度例如可以介于10μm和50μm之间，在下文中所述单一烧结区称为第一器件区A1。除了第一器件区A1外，图7还示出了形成在第二基区16上的第二器件区A2。
在已知方法中，烧结是不可逆的；即，即使再次增加温度至270℃，材料也不会再熔化。
接下来，提供了已知类型的芯片42，如图8A所示。
芯片42包括半导体主体44和多个触点46，所述触点被称为突出部46，其例如由通过助焊剂中的锡-银-铜(SAC)颗粒获得的焊膏形成。布置在突出部46和半导体主体44之间的是金属化焊盘(未示出)，突出部46本身安置在金属化焊盘上面。特别地，突出部46形成在金属化焊盘上，所述金属化焊盘布置在半导体主体44的顶面上。
如图8A和图8B所示，芯片42之后耦合到中间结构10。特别地，芯片42布置在所谓的倒装芯片结构中，这样使得每个突出部46置于对应的焊盘40上以在助焊剂的粘合作用下暂时固定到对应的焊盘40上。尽管未示出或未进一步描述，但是附加芯片被耦合到中间结构10的对应器件区上。
接下来，如图9所示，中间结构10和芯片42受到进一步热处理，例如在260℃温度下暴露于实施回流焊接的氮气流环境中进行。在实践中，完成焊接过程后，每个突出部46都焊接到对应的焊盘40。
接下来，如图10所示，采用已知方法以填充区48填充存在于突出部46之间的间隙(也称为下填料)。在实践中，如果将在其上布置有突出部46的金属化焊盘(未示出)限定的表面称为芯片表面，则填充区48在所述芯片表面及其下面部分之间延伸，也因此位于第一基区14的中央部。
例如，填充区48由热固性环氧树脂形成，其内部分散有硅胶微粒以降低树脂本身的热膨胀系数。这样，填充区48在芯片42和第一基区14之间建立固定的强机械连接，并能够减少发生热变化时作用在焊料上的机械应力，该应力是由于芯片42和第一基区14的热膨胀系数存在差异而产生的。
更详细地，通过已知类型的等离子清洗操作(未示出)可以提前形成填充区48，也可以紧跟着，再一次以已知的方式，即通过在150℃和170℃之间的温度下进行相应的热处理(未示出)形成填充区48，以使形成填充区48的树脂完成聚合反应。
接下来，如图11所示，通过注入相应的热固性环氧树脂形成介电区50，其内部分散有硅胶微粒。特别地，介电区50形成在芯片42的顶部及第一器件区A1的顶部，即预置触点36、迹线38和焊盘40的顶部。虽然未示出，但是介电区50也涂覆中间结构10和对应器件区上面的附加芯片。
接下来，如图12所示，将板8从机械机构10上机械地移除。然后，可以在其他处理过程中再次使用板8。
接下来，如图13所示，移除支承结构2。特别地，在具有介于2bar和5bar之间的压力、以及70℃的温度的环境下，通过喷水使第一支承层4和第二支承层6溶解。
接下来，虽然未示出，但是可以在175℃温度下实施进一步热处理。后者热处理也称为后成型固化(postmolding curing)。
如图14所示，然后以已知的方式执行划线与切割操作，以对中间结构10进行单一化(singulate)。换言之，使第一器件区A1与其他器件区分离，进而也使芯片42与其他芯片分离。从而形成半导体器件51。
完成切割操作后，介电区50形成封装区52，其覆盖芯片42。此外，在图14所示的实例中，以这种方式执行切割，使得每个预置触点36形成由烧结材料制成的对应触点53，不仅给出封装的底表面(在图14中标识为S1，并由第一基区14形成)，而且提供了因裸露而可焊接的侧表面。更详细地，每个触点53的侧表面(在图14中标识为S2)与封装区52的侧表面(在图14中标识为S3)共面。此外，封装区52的侧表面S3和封装区52的底表面S1的交汇处限定了边E，至少触点53的一部分沿边E延伸。在图14中，封装整体标识为P。
在实践中，图14示出的切割操作通常会形成带有方形扁平无引线(QFN)类型封装的器件。
根据图15示出的可选实施例，预置触点区、预置迹线区和预置焊盘区(分别标识为60、62和64)是通过相同可烧结墨水的喷墨印刷过程形成的。例如，该墨水可以包含分散在溶剂中的铜或银的纳米颗粒。此外，所述墨水可以在至少150℃温度下应用。通常，所述纳米颗粒的等效直径可以介于5nm和50nm之间。
接下来，如图16所示，例如可以在具有温度150℃的受控环境的炉子中进行烧结过程，或者在温度至少等于之前喷墨印刷过程的温度下进行烧结过程。
在烧结过程后，预置触点区60、预置迹线区62和预置焊盘区64分别形成预置触点(此处标识为66)、迹线(此处标识为68)和焊盘(此处标识为70)。预置触点66、迹线68和焊盘70为引线框架，并形成厚度介于10μm和30μm之间的单一烧结区。
接下来，执行前面参照图8A、图8B和图9至图14描述的操作。
根据图17示出的另一可选实施例，预置触点区30和第一器件区A1直接形成在第一支承层4上，并且彼此直接接触。所述预置迹线区和所述预置焊盘区未形成。
特别地，利用参照图5描述时提及的烧结浆料，再次通过丝网印刷工艺形成预置触点区30，其中所述浆料可以例如包括分散在环氧树脂中的铜和锡微粒，或者再例如包括镀银并分散在溶剂中的铜微粒。
第一器件区A1还包括预置裸片焊盘54，其在第一支承层4上面延伸并与第一支承层4直接接触。此外，预置裸片焊盘54被预置触点区30间隔环绕。特别地，在顶视图中，例如预置裸片焊盘54为方形；预置触点区30沿预置裸片焊盘54限定方形的各边进行布置。预置裸片焊盘54与预置触点区30是由相同烧结浆料制成的。
接下来，如图18所示，以已知的方式进行烧结过程。
详细地，按照参照图7描述的热处理类型中间结构10受到热处理，具体热处理类型取决于所采用的烧结浆料的类型。
完成烧结过程后，每个预置触点区30形成对应预置触点36。此外，预置裸片焊盘54形成裸片焊盘56。预置触点36和裸片焊盘56共同形成引线框架，并且可以具有例如介于15μm和50μm之间的厚度。
接下来，如图19所示，由已知类型导电胶制成的预置粘合区74形成在裸片焊盘56上
然后，如图20所示，芯片(此处标识为72)布置在预置粘合区74上。芯片72包括例如由二氧化硅制成的半导体主体(此处标识为75)和底部介电区77。此外，底部介电区77接触预置粘合区74。
接下来，如图21所示，在例如170℃温度下对中间结构10进行持续时间为两小时的热处理，以使预置粘合区74硬化。在对后者进行热处理后，预置粘合区74形成布置在芯片72和裸片焊盘56之间的粘合区76。
然后，使用氮气(96％)和氢气(4％)混合物作为反应气体，采用已知方法对预置触点36执行等离子清洗过程。该操作未示出。
接下来，如图22所示，通过例如由银制成的对应导线78，将芯片72电连接到预置触点36。每根导线78接触对应的预置触点36，以形成对应的焊线。所述焊线是在大约200℃温度下形成的。
接下来，如图23所示，前述介电区50形成在芯片72上和第一器件区A1上，即预置触点36上。此外，介电区50也涂覆中间结构10及对应器件区中的附加芯片。
然后，如图24所示，从中间结构10上移除板8。
接下来，如图25所示，移除支承结构2。特别地，在具有介于2bar和5bar之间的压力、以及70℃的温度的环境下，通过喷水使第一支承层4和第二支承层6溶解。
然后，虽然未示出，但是可以在175℃温度下实施进一步热处理；后者热处理的作用为“后成型固化”。
如图26所示，然后采用已知方法执行划线与切割操作，以对中间结构10进行单一化并形成半导体器件51。
特别地，图26示出的封装P通常与图14示出的封装类型相同，但是触点53通过焊线电连接到芯片72。在本实例中，裸片焊盘56和封装区52分别形成封装P的底表面S1的一部分。
根据可选实施例，芯片(在图27中标识为82)除了半导体主体75之外还包括金属化底部84。在本实例中，根据本公开的制造方法构想在执行图17示出的操作后布置芯片82，以使金属化底部84接触预置裸片焊盘54。接下来，如图28所示，执行前述烧结过程，之后在预置触点区30形成对应的预置触点36并且预置裸片焊盘54形成裸片焊盘56，其中预置触点36和裸片焊盘56共同形成引线框架。此外，为了进行烧结过程，芯片82保持固定于裸片焊盘56。
接下来，使用氮气(96％)和氢气(4％)混合物作为反应气体，采用已知方法对预置触点36执行等离子清洗过程。该操作未示出。然后，执行前面参照图22至图26描述的操作。
根据图29示出的另一个可选实施例，通过使用与参照图15描述的相同类型可烧结墨水的喷墨印刷过程，形成预置触点区和预置裸片焊盘(分别标识为90和94)。
接下来，如图30所示，例如可以在具有温度150℃的受控环境的炉子中进行烧结过程，或者在温度至少等于之前喷墨印刷过程的温度下进行烧结过程。
完成烧结操作后，预置触点区90和预置裸片焊盘94分别形成预置触点(此处标识为96)和裸片焊盘(此处标识为98)。例如，预置触点96和裸片焊盘98的具有例如介于10μm和30μm之间的厚度。
接下来，执行前面参照图19至图28描述的操作。
无论芯片布置在倒装芯片结构中还是通过焊线连接到触点，进一步地，预置触点区30和预置触点36都可以具有相应高度，以使触点53不仅延伸到封装P的底表面S1上，也延伸到封装区52的顶面(在图31中标识为S4)上，即封装本身的顶面上。然而，迹线38如前所述延伸。
如图31所示，可以形成三维结构100。三维结构100除了半导体器件51之外还包括至少一个附加器件102，其包括相应的半导体主体104，三维结构还包括相应的金属化区106和相应的多个触点108。例如，金属化区106布置在触点108和附加器件102的半导体主体104之间。此外，附加器件102的触点108接触半导体器件51的对应触点53的顶部。尽管在图31以示例的方式示出的实例中芯片42布置在倒装芯片结构中，但是，在芯片通过焊线连接到触点并且没有第一基区14的实例中，也可以实施该类型封装。
根据本公开教导的制造方法具有一定优势。特别地，本发明制造方法能够避免引线框架带材。此外，由于烧结材料质量轻且厚度小，因此通过本发明制造方法形成的封装重量更轻。在倒装芯片结构的实例中，封装厚度可以为0.2mm。而且，触点间距可以介于200μm和350μm之间。
总之，在不偏离本发明的范围的情况下，此处描述和示出方案的变型与改进都在附加的权利要求的限定范围内。
例如，如图32所示，在芯片通过焊线电连接到触点的实例中，也可以使用第三层12并进而使用前述第一基区14和第二基区16。在本实例中，完成参照图4描述的操作后，可以参照图5描述的操作即丝网印刷操作形成预置触点区30。进一步地，通过该丝网印刷操作，同样可以在第一基区14的主体15上形成预置裸片焊盘54。从而，预置触点区30与参照图6描述的触点区类型相同，并与使用第一基区14具有相同的优点，而无论通过何种方法应用烧结浆料。后续烧结处理与参照图18描述的处理类型相同，如图33所示，该后续烧结处理引起预置触点36和裸片焊盘56的形成。接下来，可以执行之前参照图19至图28描述的操作。由此，即可获得例如图34所示的半导体器件51。
如图35所示，在预置裸片焊盘形成在第一基区14上的实施例中，可以通过具有前述特性的喷墨印刷过程形成预置裸片焊盘。在本实施例中，喷墨印刷过程引起预置触点区和预置裸片焊盘(分别标识为90和94)的形成；预置裸片焊盘94布置在第一基区14上。后续烧结过程与参照图30描述的处理类型相同，如图36所示，所述后续烧结过程引起预置触点96和裸片焊盘98的形成。接下来，可以执行之前参照图19至图28描述的操作。
通常，本发明制造方法可以进一步用于形成与QFN封装不同类型的封装，例如焊区栅格阵列(LGA)类型封装。
可以没有填充区48。进一步地，例如可以实施超声波热焊，而不是回流焊接。
可以没有粘合区76。在本实施例中，例如可以在芯片72的底部介电区77上应用导电或绝缘的双面胶粘层(未示出)。接下来，芯片72在双面胶粘层的作用下固定到裸片焊盘56。
支承结构2可以仅由一层水溶性层(未示出)形成，而不是由第一支承层4和第二支承层6形成。在本实施例中，例如水溶性层是由可注射的聚乙酸乙烯酯或者其他生物材料形成。进一步地，水溶性层可以包括玻璃纤维或硅胶微粒。
更详细地，水溶性层可以具有以下特性：厚度介于0.2mm和1.0mm之间，室温环境中10Gpa的弹性系数，以及5GPa RT；体积膨胀系数低于200ppm；玻化转变温度高于150℃；熔点高于200℃；在80℃温度下完全溶解于水(但玻璃纤维/硅胶微粒除外)。

Claims (16)

1.一种表面贴装电子器件，包括：
半导体材料主体；
绝缘层，具有平面且连续的顶表面和由侧边缘限定的周边，至少一个侧边缘包括界定相邻凹槽的多个横向齿部；以及
引线框架，包括电连接到所述半导体材料主体的多个接触端子，所述接触端子填充由所述多个横向齿部界定的所述凹槽并且部分地覆盖在所述绝缘层的所述平面且连续的顶表面上。
2.根据权利要求1所述的表面贴装电子器件，其中所述绝缘层具有底表面；以及
其中所述多个接触端子延伸到所述底表面。
3.根据权利要求2所述的表面贴装电子器件，其中：
填充所述凹槽的所述多个接触端子延伸到所述绝缘层的所述至少一个侧边缘。
4.根据权利要求1所述的表面贴装电子器件，其中所述引线框架包括布置在所述绝缘层的所述平面且连续的顶表面上的多个焊盘和多个迹线，所述多个迹线中的每个迹线将对应的焊盘电连接到所述多个接触端子中的对应的接触端子。
5.根据权利要求1所述的表面贴装电子器件，还包括裸片焊盘，所述半导体材料主体布置在所述裸片焊盘上并通过焊线电连接到所述多个接触端子。
6.根据权利要求1所述的表面贴装电子器件，还包括封装介电区，所述封装介电区覆盖在所述半导体材料主体、所述绝缘层和至少部分所述引线框架上。
7.根据权利要求6所述的表面贴装电子器件，其中封装介电区形成所述封装的前表面，并且其中所述多个接触端子延伸到所述前表面。
8.根据权利要求1所述的表面贴装电子器件，其中所述多个接触端子中的每个接触端子都具有底表面，并且所述表面贴装电子器件还包括：
由底表面界定的封装，所述多个接触端子中的每个接触端子的底表面与所述封装的所述底表面共面。
9.根据权利要求1所述的表面贴装电子器件，其中所述表面贴装电子器件为方形扁平无引线类型或焊区栅格阵列类型。
10.一种用于制造表面贴装电子器件的方法，包括：
在支承结构上形成由可烧结材料制成的多个预置触点区，所述支承结构属于水溶性类型；
将包括半导体主体的芯片机械地耦合到所述支承结构；
烧结所述可烧结材料，以使每个预置触点区形成对应的烧结预置触点；
用介电涂层区涂覆所述芯片和所述多个预置触点区；以及
通过喷射水移除所述支承结构。
11.根据权利要求10所述的方法，还包括切割所述烧结预置触点的部分和所述介电涂层区，以使每个经切割的烧结预置触点具有裸露的侧表面。
12.根据权利要求10所述的方法，还包括：
在所述支承结构上形成至少一个绝缘区，使得所述至少一个绝缘区形成界定对应凹槽的多个横向齿部；以及
其中形成所述多个预置触点区包括形成所述多个预置触点区以使得每个预置触点区延伸到对应的凹槽中并部分地覆盖在所述绝缘区上。
13.根据权利要求12所述的方法，还包括：
在至少一个绝缘区上形成由所述可烧结材料制成的多个预置迹线和多个预置焊盘；以及
将所述半导体主体电连接到所述多个预置焊盘。
14.根据权利要求10所述的方法，还包括：
在所述支承结构上形成由所述可烧结材料制成的预置裸片焊盘；
烧结所述预置裸片焊盘以形成烧结裸片焊盘；
将所述芯片固定到所述烧结裸片焊盘；以及
将所述半导体主体电连接到所述烧结预置触点。
15.根据权利要求10所述的方法，还包括：
在所述支承结构上形成由所述可烧结材料制成的预置裸片焊盘；
将所述芯片布置在所述预置裸片焊盘上，使得所述芯片的金属化区接触所述预置裸片焊盘；
烧结所述预置裸片焊盘以形成烧结裸片焊盘；以及
将所述半导体主体电连接到所述烧结预置触点。
16.根据权利要求10所述的方法，其中形成所述多个预置触点区包括通过丝网印刷或喷墨印刷沉积所述可烧结材料。
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