CN214672573U - 一种多芯片烧结陶瓷封装结构 - Google Patents
一种多芯片烧结陶瓷封装结构 Download PDFInfo
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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Abstract
本实用新型涉及一种多芯片烧结陶瓷封装结构,它包括基岛和引脚,所述基岛上设置有陶瓷基片,所述陶瓷基片上开设有导电通孔,所述导电通孔内设置有导电金属柱,所述陶瓷基片上表面分为第一区域和第二区域,所述第一区域位于导电金属柱上方,所述第一区域上设置有金属层,所述金属层通过导电金属柱电性连接至基岛,所述第一区域上通过装片胶设置有第一芯片,所述第二区域上通过装片胶设置有第二芯片,所述第一芯片、第二芯片和引脚相互之间通过第一焊线相连接,所述第一芯片、第二芯片与金属层之间通过第二焊线相连接;本实用新型一种多芯片烧结陶瓷封装结构,它采用低温多次烧结陶瓷片替代现有裸硅片,可实现对现有高压隔离封装耐压能力大幅提升。
Description
技术领域
本实用新型涉及一种多芯片烧结陶瓷封装结构,属于半导体封装技术领域。
背景技术
现有的高压隔离封装工艺一般有两种,一种是利用不导胶+裸硅片进行高压隔离,另一种是利用高温烧结的陶瓷基片进行隔离。利用不导胶+裸硅片进行高压隔离的效果不佳,其隔离效果仅相当于陶瓷基片的1/10甚至更少。而利用高温烧结的陶瓷基片进行高压隔离的方法也存在不足,首先因其工艺为高温烧结,材质硬、脆,在封装过程中容易发生破裂,不利于产品可靠性。另外现有陶瓷基片表面与背面间是完全绝缘的,无法实现芯片接地需求。再次,无法满足多芯片封装的要求,在多芯片封装中,其与不同种类的芯片接合需使用不同胶水,要经过多次烘烤,从而导致可靠性不好。
发明内容
本实用新型所要解决的技术问题是针对上述现有技术提供一种多芯片烧结陶瓷封装结构,它采用低温多次烧结陶瓷片替代现有裸硅片,可实现对现有高压隔离封装耐压能力大幅提升。
本实用新型解决上述问题所采用的技术方案为:一种多芯片烧结陶瓷封装结构,它包括基岛和引脚,所述基岛上设置有陶瓷基片,所述陶瓷基片上开设有导电通孔,所述导电通孔内设置有导电金属柱,所述陶瓷基片上表面分为第一区域和第二区域,所述第一区域位于导电金属柱上方,所述第一区域上设置有金属层,所述金属层通过导电金属柱电性连接至基岛,所述第一区域上通过装片胶设置有第一芯片,所述第二区域上通过装片胶设置有第二芯片,所述第一芯片、第二芯片和引脚相互之间通过第一焊线相连接,所述第一芯片、第二芯片与金属层之间通过第二焊线相连接;
可选的,所述第二芯片为隔离芯片。
与现有技术相比,本实用新型的优点在于:
1、本实用新型针对常规高压隔离封装,使用低温多次烧结陶瓷片替代现有裸硅片,陶瓷基板的耐压能力是硅基板的10倍以上,可实现对现有高压隔离封装耐压能力大幅提升;
2、本实用新型陶瓷经过中低温预烧结+焊料与陶瓷共烧,不仅可以保证其模量/泊松比和芯片同步变化,同样可以保证陶瓷与L/F、芯片之间的粘结力,保证产品可靠性;
3、本实用新型陶瓷基片表面做通孔+印刷Cu电极实现芯片与基岛互联的需求,从而实现封装产品多功能需求;
4、本实用新型低温陶瓷基片覆铜可实现不同芯片全部装在陶瓷基片表面,并且焊料与陶瓷共同烧结一次,减少烘烤次数,提升可靠性。
附图说明
图1为本实用新型一种多芯片烧结陶瓷封装结构的示意图。
其中:
基岛1
引脚2
陶瓷基片3
导电通孔4
导电金属柱5
金属层6
第一芯片7
第二芯片8
装片胶9
第一焊线10
第二焊线11。
具体实施方式
以下结合附图实施例对本实用新型作进一步详细描述。
如图1所示,本实用新型涉及的一种多芯片烧结陶瓷封装结构,它包括基岛1和引脚2,所述基岛1上设置有陶瓷基片3,所述陶瓷基片3上开设有导电通孔4,所述导电通孔4内设置有导电金属柱5,所述陶瓷基片3上表面分为第一区域和第二区域,所述第一区域位于导电金属柱5上方,所述第一区域上设置有金属层6,所述金属层6通过导电金属柱5电性连接至基岛1,所述第一区域上通过装片胶9设置有第一芯片7,所述第二区域上通过装片胶9设置有第二芯片8,所述第一芯片7、第二芯片8和引脚2相互之间通过第一焊线10相连接,所述第一芯片7、第二芯片8与金属层6之间通过第二焊线11相连接;
所述第二芯片8为高压隔离芯片。
其制造方法包括以下步骤:
步骤一、先将无机的氧化铝粉与约30%~50%的玻璃材料加上有机黏结剂,使其混合均匀成为泥状的浆料,接着利用刮刀把浆料刮成片状,再经由一道干燥过程将片状浆料形成一片片薄薄的生胚;
步骤二、在生胚上钻导电通孔;
步骤三、在导电通孔中进行填料形成导电金属柱;
步骤四、在导电通孔上、下表面形成金属层,金属层作为内外电极使用,内外电极可使用银、铜、金等金属;
步骤五、将生胚放置于850~900℃的烧结炉中进行预烧结成型,形成柔性陶瓷基片;
步骤六、将陶瓷基片通过烧结银浆装在引线框架(基岛)上,烧结银浆具有高散热、高粘结力;
步骤七、在陶瓷基片上装各种芯片,再进行共同烧结,此时银浆及陶瓷全部固化成硬状,高压隔离芯片直接装在陶瓷基片上,场效应MOS芯片可以装在金属层上也可以在铜上焊线作为D极;
步骤八、在芯片与引脚之间以及芯片与金属层之间进行打线作业;
步骤九、利用塑封料进行塑封作业;
步骤十、将完成塑封的半成品进行切割或是冲切作业,使原本阵列式的塑封体切割或是冲切独立开来,制得一种多芯片烧结陶瓷封装结构。
上述实施例外,本实用新型还包括有其他实施方式,凡采用等同变换或者等效替换方式形成的技术方案,均应落入本实用新型权利要求的保护范围之内。
Claims (2)
1.一种多芯片烧结陶瓷封装结构,其特征在于:它包括基岛(1)和引脚(2),所述基岛(1)上设置有陶瓷基片(3),所述陶瓷基片(3)上开设有导电通孔(4),所述导电通孔(4)内设置有导电金属柱(5),所述陶瓷基片(3)上表面分为第一区域和第二区域,所述第一区域位于导电金属柱(5)上方,所述第一区域上设置有金属层(6),所述金属层(6)通过导电金属柱(5)电性连接至基岛(1),所述第一区域上通过装片胶(9)设置有第一芯片(7),所述第二区域上通过装片胶(9)设置有第二芯片(8),所述第一芯片(7)、第二芯片(8)和引脚(2)相互之间通过第一焊线(10)相连接,所述第一芯片(7)、第二芯片(8)与金属层(6)之间通过第二焊线(11)相连接。
2.根据权利要求1所述的一种多芯片烧结陶瓷封装结构,其特征在于:所述第二芯片(8)为隔离芯片。
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