CN103296086A - 用于半导体器件的栅极结构 - Google Patents

用于半导体器件的栅极结构 Download PDF

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CN103296086A
CN103296086A CN2012105915281A CN201210591528A CN103296086A CN 103296086 A CN103296086 A CN 103296086A CN 2012105915281 A CN2012105915281 A CN 2012105915281A CN 201210591528 A CN201210591528 A CN 201210591528A CN 103296086 A CN103296086 A CN 103296086A
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layer
semiconductor device
silicide
grid structure
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CN103296086B (zh
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李宗霖
袁锋
叶致锴
赖韦仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

描述了一种半导体器件及其制造方法，该半导体器件包括具有鳍片的衬底，该鳍片具有顶面以及第一横向侧壁和第二横向侧壁。硬掩模层可以形成在鳍片的顶面上(例如，提供双栅极器件)。栅极介电层和功函数金属层形成在鳍片的第一横向侧壁和第二横向侧壁上。硅化物层形成在位于鳍片的第一横向侧壁和第二横向侧壁上的功函数金属层上。硅化物层可以是完全硅化层并且可以对设置在鳍片中的器件的沟道区提供应力。本发明提供用于半导体器件的栅极结构。

Description

用于半导体器件的栅极结构
技术领域
本发明涉及半导体器件，具体而言，涉及finFET器件。
背景技术
半导体集成电路(IC)产业经历了快速增长。在这种增长过程中，通常通过减小器件部件尺寸或几何尺寸来增大器件的功能密度。这种按比例缩小工艺一般通过提高生产效率、降低成本和/或改善性能而带来益处。这种按比例缩小的工艺也增大了加工和制造IC的复杂性，并且为了实现这些进步，在IC制造方面也需要类似的发展。
同样地，对增强IC的性能以及缩小其几何尺寸的需求引入了多栅极器件。这些多栅极器件包括多栅极鳍式晶体管，也被称为finFET器件，因为沟道形成在从衬底延伸出来的“鳍片”上。finFET器件可以实现缩小器件的栅极宽度同时在包括沟道区的鳍片的侧面和/或顶部上设置栅极。
改善半导体器件性能的另一种方式是在器件的相关区域上提供应力或者对器件的相关区域提供应变。处理在区域中提供的应力是提高FET器件中的少数载流子迁移率的有效途径。当对半导体器件的沟道施加应力时，可以影响载流子的迁移率并且因而改变器件的跨导和导通电流(on-current)。例如，拉伸应力可能对NFET器件有益，容许增大通过沟道区的载流子(例如，空穴)的迁移率。相反，压缩应力可能对PFET器件有益。
发明内容
为了解决上述技术问题，一方面，本发明提供了一种半导体器件，包括：衬底，包括第一鳍片，其中，所述第一鳍片包括顶面以及第一横向侧壁和第二横向侧壁；硬掩模层，形成在所述第一鳍片的所述顶面上；栅极介电层，形成在所述硬掩模层以及所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上；功函数金属层，形成在位于所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上的所述栅极介电层上；以及硅化物层，形成在位于所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上的所述功函数金属层上。
所述的半导体器件还包括：设置在所述硅化物层上的金属填充层。
所述的半导体器件还包括设置在所述硅化物层上的金属填充层，该半导体器件还包括：邻近所述第一鳍片的第二鳍片，其中，所述金属填充层介于所述第一鳍片和所述第二鳍片之间。
所述的半导体器件还包括第二鳍片，其中，所述硅化物层在所述第一鳍片和所述第二鳍片之间的厚度大于所述第一鳍片的高度，并且其中，所述第一鳍片的所述高度由所述第一鳍片在所述衬底上设置的隔离结构上方延伸的距离限定。
所述的半导体器件还包括第二鳍片，其中，所述硅化物层在所述第一鳍片和所述第二鳍片之间的厚度小于所述第一鳍片的高度，其中，所述第一鳍片的所述高度由所述第一鳍片在所述衬底上设置的隔离结构的上方延伸的距离限定。
在所述的半导体器件中，所述硅化物层包含硅化镍(NiSi)。
在所述的半导体器件中，所述硅化物层不设置在所述硬掩模层的顶面上。
另一方面，本发明提供了一种制造半导体器件的方法，包括：提供具有第一鳍片和第二鳍片的半导体衬底；在所述第一鳍片和所述第二鳍片的顶面上形成硬掩模层；在所述第一鳍片和所述第二鳍片上形成功函数金属层；在所述功函数金属层上形成至少一个包含硅的层；以及对所述至少一个包含硅的层实施硅化工艺从而形成硅化物层。
在所述的方法中，在所述功函数金属层上直接形成所述硅化物层。
所述的方法还包括：在所述硅化物层上形成填充金属层。
在所述的方法中，形成所述至少一个包含硅的层包括形成非晶硅层。
在所述的方法中，形成所述至少一个包含硅的层包括在多晶硅层上形成非晶硅层，并且其中，实施所述硅化工艺包括将所述非晶硅层和所述多晶硅层转换成硅化物层。
在所述的方法中，形成所述至少一个包含硅的层包括蚀刻在所述第一鳍片和所述第二鳍片上形成的多晶硅层以形成经过蚀刻的多晶硅层，并且其中，所述硅化工艺包括将所述经过蚀刻的多晶硅层转换成硅化物材料。
在所述的方法中，形成所述至少一个包含硅的层包括蚀刻在所述第一鳍片和所述第二鳍片上形成的多晶硅层以形成经过蚀刻的多晶硅层，并且其中，所述硅化工艺包括将所述经过蚀刻的多晶硅层转换成硅化物材料，其中，所述经过蚀刻的多晶硅层的厚度大于约2/3的所述第一鳍片的高度。
在所述的方法中，形成所述至少一个包含硅的层包括蚀刻在所述第一鳍片和所述第二鳍片上形成的多晶硅层以形成经过蚀刻的多晶硅层，并且其中，所述硅化工艺包括将所述经过蚀刻的多晶硅层转换成硅化物材料，其中，所述经过蚀刻的多晶硅层的厚度大于所述第一鳍片的高度。
在所述的方法中，形成所述至少一个包含硅的层包括蚀刻在所述第一鳍片和所述第二鳍片上形成的多晶硅层以形成经过蚀刻的多晶硅层，并且其中，所述硅化工艺包括将所述经过蚀刻的多晶硅层转换成硅化物材料，所述的方法还包括：沉积所述多晶硅层；以及图案化所述多晶硅层以形成栅极结构，其中，在图案化所述多晶硅层之后实施蚀刻所述多晶硅层以形成所述经过蚀刻的多晶硅层。
又一方面，本发明提供了一种鳍式场效应晶体管(finFET)器件，包括：第一鳍片和第二鳍片，其中，隔离结构介于所述第一鳍片和所述第二鳍片之间；第一栅极结构，与所述第一鳍片的所述侧壁通过界面接合；第二栅极结构，与所述第二鳍片的所述侧壁通过界面接合，其中，所述第一栅极结构和所述第二栅极结构每一个都包括完全硅化层，并且其中，所述完全硅化层对所述第一鳍片和所述第二鳍片的沟道区提供应力。
所述的finFET器件还包括：硬掩模层，形成在所述第一栅极结构和所述第二栅极结构的顶面上。
在所述的finFET器件中，所述finFET是双栅极器件。
在所述的finFET器件中，所述完全硅化层介于所述第一栅极结构的功函数层和填充金属层之间。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各方面。应该强调的是，根据工业中的标准实践，对各种部件没有按比例绘制。实际上，为了清楚地讨论，各种部件的尺寸可以被任意地增大或减小
图1是根据本发明一个或多个方面的半导体器件的实施例的透视图。
图2是根据本发明一个或多个方面的制造半导体器件的方法的实施例的流程图。
图3至图5是根据图2的方法的工艺步骤的半导体器件的实施例的截面图。
图6至图11是根据图2的方法的在后续制造阶段的图3至图5的半导体器件的第一实施例的截面图。
图12至图15是根据图2的方法的在后续制造阶段的图3至图5的半导体器件的第二实施例的截面图。
图16至图19是根据图2的方法的在后续制造阶段的图3至图5的半导体器件的第三实施例的截面图。
具体实施方式
可以理解为了实施本发明的不同部件，以下公开内容提供了许多不同的实施例或实例。在下面描述元件和布置的特定实例以简化本发明。当然这些仅是实例并不打算用于限定。而且，在下面的描述中第一部件在第二部件上方或者在第二部件上的形成可以包括其中第一和第二部件以直接接触形成的实施例，并且也可以包括其中可以形成介于第一和第二部件之间的额外的部件，使得第一和第二部件可以不直接接触的实施例。为了简明和清楚，可以任意地以不同的比例绘制各种部件。另外，本发明可以在各个实例中重复附图标记和/或字母。这种重复是为了简明和清楚，并且其本身没有指明各个实施例之间的关系。可以理解，本领域技术人员能够设计出尽管在本文中没有明确描述但是体现了本发明原理的各种等效物。
图1中示出了半导体器件100。半导体器件100包括(一个或多个)finFET型器件。半导体器件100可以是n型finFET或者p型finFET。半导体器件100可以包括在IC(诸如，微处理器、存储器器件和/或其他IC)中。器件100包括衬底102、多个鳍片104、多个隔离结构106、以及设置在每个鳍片104上的栅极结构108。多个鳍片104中的每一个均包括标记为110的源极/漏极区，在该源极/漏极区中，在鳍片104中、在鳍片104上和/或在鳍片104周围形成源极或漏极部件。鳍片104的沟道区位于栅极结构108下面并且被标记为112。
衬底102可以是硅衬底。可选地，衬底102可以包括其他元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或它们的组合。在又一可选的实施例中，衬底102是绝缘体上半导体(SOI)衬底。
隔离结构106可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k介电材料和/或其他合适的绝缘材料形成。隔离结构106可以是浅沟槽隔离(STI)部件。在实施例中，隔离结构是STI部件并且通过在衬底102中蚀刻沟槽形成。然后可以用隔离材料填充沟槽，接着进行化学机械抛光(CMP)。用于隔离结构106和/或鳍片结构104的其他制造技术是可能的。隔离结构106可以包括多层结构，例如具有一个或多个衬垫层。
鳍片结构104可以提供其中形成一个或多个器件的有源区。在实施例中，在鳍片104中形成晶体管器件的沟道。鳍片104可以包含硅或者另一元素半导体，诸如锗；化合物半导体，包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟；合金半导体，包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP；或者它们的组合。可以采用合适的工艺(包括光刻和蚀刻工艺)来制造鳍片104。光刻工艺可以包括在衬底上面(例如，在硅层上)形成光刻胶层(光刻胶(resist))、使光刻胶暴露于图案、实施曝光后烘焙工艺以及使光刻胶显影以形成包括光刻胶的掩模元件。然后掩模元件可以用于保护衬底的区域，同时蚀刻工艺在硅层中形成凹槽，留下延伸的鳍片。可以采用反应离子蚀刻(RIE)和/或其他合适的工艺蚀刻凹槽。在衬底102上形成鳍片104的方法的众多其他实施例可能是适合的。
在实施例中，鳍片104宽约10纳米(nm)并且高约15nm和40nm之间(测自隔离区106之上的鳍片的高度)。然而，应当理解，鳍片104可以采用其他尺寸。可以采用n型和/或p型掺杂物来掺杂鳍片104。
栅极结构108可以包括栅极介电层、功函数层和/或一个或多个其他层。在实施例中，栅极结构108包括硅化物层，诸如在下文实施例中所述的硅化物层。硅化物层可以位于栅极介电层和/或功函数层的上面。
在实施例中，在制造期间提供半导体器件100，并且栅极结构108是牺牲栅极结构，诸如在用于形成金属栅极结构的替换栅极工艺中形成的牺牲栅极结构。在实施例中，栅极结构108包括多晶硅。在另一实施例中，栅极结构108包括金属栅极结构。
栅极结构108的栅极介电层可以包含二氧化硅。可以通过合适的氧化和/或沉积方法形成氧化硅。可选地，栅极结构108的栅极介电层可以包括高k介电层，诸如氧化铪(HfO2)。可选地，高k介电层可以任选地包含其他高k电介质，诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合、或者其他合适的材料。可以通过原子层沉积(ALD)和/或其他合适的方法形成高k介电层。
在实施例中，栅极结构108可以是金属栅极结构。金属栅极结构可以包括(一个或多个)界面层、(一个或多个)栅极介电层、(一个或多个)功函数层、如下面所述的硅化物层、(一个或多个)填充金属层和/或用于金属栅极结构的其他合适的材料。在其他实施例中，金属栅极结构108还可以包括保护层、蚀刻终止层和/或其他合适的材料。界面层可以包括介电材料，诸如氧化硅层(SiO2)或者氮氧化硅(SiON)。可以通过化学氧化、热氧化、原子层沉积(ALD)、CVD和/或其他合适的电介质形成界面介电层。
可以包含在栅极结构108中的示例性p型功函数金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p型功函数金属或它们的组合。可以包含在栅极结构108中的示例性n型功函数金属包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函数金属或它们的组合。功函数值与功函数层的材料组分相关，并因此，选择第一功函数层的材料以调谐其功函数值从而使在将要在相应区域中形成的器件中达到期望的阈值电压Vt。可以通过CVD、PVD和/或其他合适的工艺沉积(一个或多个)功函数层。填充金属层可以包含Al、W或Cu和/或其他合适的材料。可以通过CVD、PVD、电镀和/或其他合适的工艺形成填充金属。可以在(一个或多个)功函数金属层的上方沉积填充金属，从而填充通过去除伪栅极结构形成的沟槽或者开口的剩余部分。硅化物层可以介于功函数层和填充金属之间。硅化物层可以基本上类似于下面所述的这些层，例如，下面分别参照图8、图9、图14和图17所述的硅化物层802、硅化物层902、硅化物层1402和/或硅化物层1702。
半导体器件100可以包括没有具体示出的其他层和/或部件，包括其他源极/漏极区、层间介电(ILD)层、接触件、互连件和/或其他合适的部件。
半导体器件100的性能可以受益于在沟道区112中的鳍片104上以及在鳍片104中提供的应力。在实施例中，可以产生拉伸应变。在另一实施例中，可以产生压缩应变。可以采用下面参照图2所述的方法200获得应变。在实施例中，通过在沟道区域上设置的栅极结构中设置完全硅化的层，对沟道提供应力。关于在鳍片上提供的应力的描述也记载在2011年9月23日提交的申请第13/243,723号(代理人案号2011-0614/24061.1884)中，特此将该申请的全部内容并入作为参考。
现在参照图2，示出根据本发明的一个或多个方面的半导体制造方法200的流程图。可以实施方法200以增加在半导体器件(诸如场效应晶体管(FET))的一个或多个区域中提供的应力或者应变。在实施例中，可以实施方法200以形成多栅极鳍式晶体管或者finFET器件。在实施例中，可以实施方法200以形成双栅极finFET器件。但是，可以认识到可以从本方法受益的其他器件类型。图3至图19是根据图2的方法200的步骤制造的半导体器件的实施例的截面图。应当理解，图3至图19以及示出的器件仅是代表性的而不是限制性的。
还应当理解，方法200包括具有互补金属氧化物半导体(CMOS)技术工艺流程的特征的步骤，并因此在本文中仅进行简述。可以在方法200之前、之后和/或期间实施其他步骤。类似地，可以认识到可以从本文所述方法受益的器件的其他部分。也可以理解，可以通过CMOS技术制造部分半导体器件300，并因此在本文中对一些工艺仅进行简述。此外，示出的半导体器件可以包括各种其他器件和部件，诸如其他晶体管、双极结型晶体管、电阻器、电容器、二极管、熔丝等，但将其简化以便更好地理解本发明的发明构思。本文所述的半导体器件可以包括互连的多个器件。
方法200开始于框202，其中，提供半导体衬底。半导体衬底可以基本上类似于上面关于参照图1所述的半导体器件100的半导体衬底102所论述的半导体衬底。在实施例中，半导体衬底包括从衬底延伸出来的多个鳍片。
参照图3的实例，半导体器件300包括具有多个鳍片104的衬底102。隔离结构(例如，STI部件)106介于鳍片104之间。半导体器件300可以基本上类似于上面参照图1所述的半导体器件100。
硬掩模层302位于鳍片104的顶面的上面。硬掩模层302可以提供用于待在鳍片104上形成的双栅极器件(例如，栅极结构108在鳍片104的横向侧面而不是在提供双栅极(相对于三栅极)晶体管的顶面与鳍片104的沟道区通过界面接合)。硬掩模层302可以包含氮化硅或者其他合适的硬掩模材料。
然后方法200继续到框204，其中，在衬底上形成栅极层。在实施例中，在从衬底延伸出来的鳍片上和/或其包围形成栅极层。栅极层可以包括多个层，诸如界面层、栅极介电层、功函数层、保护层、和/或其他合适的层。
参照图4的实例，在衬底102上设置栅极介电层402和功函数金属层404。具体而言，在鳍片104上设置栅极介电层402和功函数金属层404。随后可以对栅极介电层402和功函数金属层404进行图案化(如下面论述的)以使其包含在栅极结构诸如上面参照图1所描述的栅极结构108中。
栅极介电层402可以包含二氧化硅。可以通过合适的氧化和/或沉积方法形成氧化硅。可选地，栅极介电层402可以包括高k介电层，诸如氧化铪(HfO2)。可选地，高k介电层可以任选地包含其他高k电介质，诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合、或者其他合适的材料。可以通过原子层沉积(ALD)和/或其他合适的方法形成高k介电层。界面层(例如，氧化硅)可以位于栅极介电层402的下面。
功函数金属层404可以是n型或者p型功函数层。可以包含在栅极结构108的功函数金属层404中的示例性p型功函数金属包括TiN、TaN、Ru、Mo、Al、WN、ZrSi2、MoSi2、TaSi2、NiSi2、WN、其他合适的p型功函数材料或它们的组合。可以包含在功函数金属层404中的示例性n型功函数金属包括Ti、Ag、TaAl、TaAlC、TiAlN、TaC、TaCN、TaSiN、Mn、Zr、其他合适的n型功函数金属或它们的组合。功函数层404可以包括多个层。可以通过CVD、PVD和/或其他合适的工艺沉积(一个或多个)功函数层404。
然后，方法200继续到框206，其中，在衬底上形成多晶硅层。可以作为位于鳍片上面的栅极结构的一部分形成多晶硅层。在实施例中，在参照上面框204所述的栅极层上形成多晶硅层。可以对栅极层和多晶硅层进行图案化以提供栅极结构，诸如上面参照图1所述的栅极结构108。例如，多晶硅层可以是作为金属栅极形成工艺(例如，先栅极或者后栅极替换栅极工艺)的一部分形成的牺牲层。可以通过合适的沉积工艺，诸如，例如低压化学汽相沉积(LPCVD)和等离子体增强CVD(PECVD)形成多晶硅层。参照图5的实例，在栅极层402/404上形成多晶硅层502。
然后方法200继续到框208，其中，实施另一制造工艺，包括图案化栅极结构以及形成器件的源极/漏极区。
这些制造工艺可以包括用于形成本领域中已知的各种部件的MOS技术加工。例如，方法200可以包括图案化栅极层和/或多晶硅层以形成栅极结构。图案化可以包括光刻、蚀刻和/或其他合适的工艺。也可以邻近栅极结构形成(一个或多个)源极/漏极区。在实施例中，(一个或多个)源极/漏极区包括位于鳍片上和/或其周围的外延生长区。邻接栅极结构的侧壁可以形成间隔元件。间隔元件可以包括一个或多个层。在实施例中，间隔元件限定出源极/漏极延伸区。在外延生长工艺期间，可以采用结注入和/或原位掺杂来掺杂源极/漏极区。可以在源极/漏极区上形成硅化物区。硅化物材料可以包括硅化镍(NiSi)、硅化镍铂(NiPtSi)、硅化镍铂锗(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi))、硅化钴(CoSi)、其他合适的导电材料和/或它们的组合。可以通过包括沉积金属层、对金属层进行退火以使金属层能够与硅反应形成硅化物以及然后去除未反应的金属层的工艺形成硅化物接触部件。
然后可以在栅极结构和/或源极/漏极区上形成接触蚀刻终止层(CESL)和层间介电层(ILD)。可以用于形成CESL的材料的实例包括氮化硅、氧化硅、氮氧化硅和/或本领域中已知的其他材料。可以通过PECVD工艺和/或其他合适的沉积或者氧化工艺形成CESL。ILD层可以包含介电材料，诸如原硅酸四乙酯(TEOS)氧化物、未掺杂的硅玻璃或掺杂的氧化硅(诸如硼磷硅酸盐玻璃(BPSG)、熔融石英玻璃(FSG)、磷硅酸盐玻璃(PSG)、硼掺杂的硅玻璃(BSG))、和/或其他合适的介电材料。可以通过PECVD工艺或者其他合适的沉积技术沉积ILD层。在其形成之后，可以实施化学机械抛光(CMP)工艺来平坦化ILD层。在实施例中，CMP工艺暴露出上面框206中所述的多晶硅层的顶面。
然后方法200继续到框210，其中，在衬底上制备(一个或多个)目标层。目标层包含硅。目标层是待硅化的层，如参照下面框212所述的。在器件的沟道区上形成目标层，使得目标层的硅化提供可以在器件中诱导沟道应变的硅化物层(例如，完全硅化层)。目标层可以包含在栅极结构诸如例如上面参照图1所述的栅极结构108中。
在实施例中，目标层包括上面参照框206所述的多晶硅层或其部分。在实施例中，在衬底上沉积包含硅的层。下面分别参照图6至图7、图12至图13和图16论述形成目标层的多个实施例。但是，本领域的普通技术人员将认识到在本发明范围内的其他实施例。
在实施例中，通过去除上面参照框206所述的多晶硅层以及在衬底上形成包含硅的层以提供目标层来制备目标层。采用图6至图7作为示例性的，如图6中所示出的，从衬底102去除多晶硅层502。可以通过合适的湿法或者干法蚀刻工艺去除多晶硅层502。例如，可以使用蚀刻溶液，诸如，例如NH4OH、稀HF和/或其他合适的蚀刻剂。其后，在衬底102上形成含硅层702。层702可以是非晶硅(a-Si)。可以通过PECVD和/或其他合适的工艺形成层702。层702的厚度T1可以小于约一半的鳍片之间的间隔S1。
在另一实施例中，通过去除上面参照框206所述的多晶硅层的一部分以使一部分多晶硅层保留在衬底上来制备目标层。然后可以在经过蚀刻的多晶硅层上形成另一包含硅的层。采用图12至图13作为示例性的，蚀刻多晶硅层502以形成如图12中示出的经过蚀刻的多晶硅层1202。可以通过合适的湿法或者干法蚀刻工艺蚀刻多晶硅层。例如，可以使用蚀刻溶液，诸如，例如NH4OH、稀释HF和/或其他合适的蚀刻剂。经过蚀刻的多晶硅层1202具有厚度T2。厚度T2可以大于约2/3的高度H2，高度H2是位于隔离区106之上的鳍片104的高度。其后，参见图13，在衬底102上形成含硅层1302。层1302可以是非晶硅(a-Si)。层1302的厚度T3可以小于约一半的鳍片之间的间隔S1。在实施例中，间距S1介于约2nm和10nm之间。可以直接在多晶硅层1202上形成含硅层1302。
在另一实施例中，通过去除上面参照框206所述的多晶硅层的一部分以使一部分多晶硅层保留在衬底上来制备目标层。将剩余的多晶硅层用作目标层。在实施例中，在转换成硅化物的目标层中不包括其他含硅层。采用图16作为示例性的，蚀刻多晶硅层502以形成经过蚀刻的多晶硅层1602。可以通过合适的湿法或者干法蚀刻工艺蚀刻多晶硅层。例如，可以使用蚀刻溶液，诸如，例如NH4OH、稀HF和/或其他合适的蚀刻剂。经过蚀刻的多晶硅层1602具有厚度T3。厚度T3可以大于高度H3，高度H3是在隔离区106之上的鳍片104的高度。换句话说，经过蚀刻的多晶硅层1602的顶面位于鳍片104的顶面之上。
然后方法200继续到框212，其中，提供在框210中所述的(一个或多个)目标层的硅化。上面参照框210所述的(一个或多个)目标层可以是完全硅化的(例如，消耗所有的硅来提供硅化物)。在实施例中，将非晶硅目标层转换成硅化物。在另一个实施例中，将非晶硅层和下面的多晶硅层转换成硅化物。在实施例中，将剩余的多晶硅层转换成硅化物。下面参照图8、图9、图14和图17来论述这些实施例中的每一个。
在实施例中，通过包括沉积金属层(诸如镍)、以及对金属层进行退火以使金属层能够与包含硅的目标层反应形成硅化物层的工艺来形成硅化物层。可以采用诸如物理汽相沉积(PVD)(溅射)、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)、常压化学汽相沉积(APCVD)、低压CVD(LPCVD)、高密度等离子体CVD(HDPCVD)或原子层CVD(ALCVD)的常规工艺沉积金属层。退火可以在诸如Ar、He、N2或者其他惰性气体的气氛中采用快速热退火(RTA)。可以采用二次退火来提供稳定的硅化物层。硅化物材料可以包括硅化镍(NiSi)、硅化镍铂(NiPtSi)、硅化镍铂锗(NiPtGeSi)、硅化镍锗(NiGeSi)、硅化镱(YbSi)、硅化铂(PtSi)、硅化铱(IrSi)、硅化铒(ErSi)、硅化钴(CoSi)、其他合适的导电材料、和/或它们的组合。硅化物层可以是完全硅化的。
参照图8的实例，(图7的)层702已经被完全硅化成硅化物层802。图8示出鳍片104之间具有间隙G的实施例。在另一实施例中，图9示出层702是完全硅化的，从而形成了硅化物层902。硅化物层902填充鳍片104之间的区域，不留下间隙。图8和图9的实施例可以由层702的厚度和/或硅化条件来决定。
参照图14的实例，层1302(例如，a-Si)和(图12的)经过蚀刻的多晶硅层1202(都)被完全硅化成硅化物层1402。图14示出鳍片104之间具有间隙G2的实施例。但是，在其他实施例中，硅化物层1402可以填充鳍片104之间的区域，因此不留下间隙。硅化物层1402具有厚度T1。厚度T1可以大于鳍片高度H2。硅化物层1402的顶面可以位于鳍片104的顶面之上。
参照图17的实例，(图16的)经过蚀刻的多晶硅层1602已经完全硅化成硅化物层1702。硅化物层1702具有厚度T4。厚度T4可以大于鳍片高度H3。硅化物层1702的顶面可以位于鳍片104的顶面之上。因此，在后续工艺期间，硅化物层1702可以保护设置在鳍片104的侧壁上的功函数层404。
在如在上面各个实施例中所述形成硅化物层之后，可以从衬底去除任何剩余的未反应的金属层。在实施例中，从衬底去除未反应的镍。在实施例中，也可以去除在鳍片上形成的硬掩模上面的材料。参照图18的实例，已经从硬掩模层302的顶面去除功函数金属404(参见图17)。
然后方法200继续到框214，其中，在衬底上形成填充金属层。可以在如上面参照框212所述形成的硅化物层上形成填充金属层。填充金属层可以用于“填充”栅极结构的剩余部分，以使可以形成接触件。在实施例中，填充金属填充通过在替换栅极工艺中去除伪栅极结构形成的沟槽或者开口的剩余部分。填充金属可以包含Al、W或Cu和/或其他合适的材料。可以通过CVD、PVD、电镀和/或其他合适的工艺形成填充金属。
参照图10的实例，在硅化物层802上设置填充金属层1002。图10示出在沉积填充金属层1002之后的图8的实施例。参照图11的实例，在硅化物层902上设置填充金属层1102。图11示出在沉积填充金属层1102之后的图9的实施例。
参照图15的实例，在硅化物层1402上设置填充金属层1502。图15示出在沉积填充金属层1502之后的图14的实施例。
参照图19的实例，在硅化物层1702上设置填充金属层1902。图19示出在沉积填充金属层1902之后的图18的实施例。
方法200可以继续包括用于形成本领域中已知的各种部件的另一CMOS或者MOS技术加工。可以实施的示例性工艺包括形成连接至栅极结构(包括填充金属层)的接触部件，以及形成具有可以将在衬底上形成的一个或多个半导体器件互连起来的通孔和互连线的多层互连件(MLI)。
因此，可以理解，提供了实现在鳍片的侧壁上形成硅化物层的器件和器件的制造方法。鳍片可以包括诸如finFET的半导体器件的沟道。硅化物层可以通过在鳍片上提供应力从而在器件的沟道区中诱导应变而对器件带来益处。finFET可以是具有设置在鳍片的顶面上的硬掩模层的双栅极finFET器件。可以理解，本文所公开的不同实施例提供了不同的公开内容，以及可以在不背离本发明主旨和范围的情况下，对这些实施例做各种不同的改变、替换和更改。
在一个实施例中，描述了一种半导体器件，该半导体器件包括具有鳍片的衬底，该鳍片具有顶面和第一横向侧壁和第二横向侧壁。硬掩模层形成在鳍片的顶面上。栅极介电层形成在鳍片的第一横向侧壁和第二横向侧壁上。功函数金属层形成在位于鳍片的第一横向侧壁和第二横向侧壁上的栅极介电层上。硅化物层形成在位于鳍片的第一横向侧壁和第二横向侧壁上的功函数金属层上。
还描述了一种制造半导体的方法，该方法包括提供具有第一鳍片和第二鳍片的半导体衬底以及在第一鳍片和第二鳍片的顶面上形成硬掩模层。在第一鳍片和第二鳍片上还形成功函数金属层。其后，在功函数金属层上形成至少一个包含硅的层。对至少一个包含硅的层实施硅化工艺从而形成硅化物层。
在又一实施例中，提供了一种鳍式场效应晶体管(finFET)器件。该器件包括第一鳍片和第二鳍片以及介于第一鳍片和第二鳍片之间的隔离结构。第一栅极结构与第二鳍片的侧壁通过界面接合。第二栅极结构与第二鳍片的侧壁通过界面接合。第一栅极结构和第二栅极结构每一个都包括完全硅化层。完全硅化层对第一鳍片和第二鳍片的沟道区提供应力。
在另一实施例中，finFET器件可以包括在第一栅极结构和第二栅极结构的顶面上形成的硬掩模层。finFET可以是双栅极器件(例如，通过接触鳍片的两侧(例如，横向侧壁)限定出沟道)。完全硅化层可以介于栅极结构中的功函数层和填充金属层之间。

Claims (10)

1.一种半导体器件，包括：
衬底，包括第一鳍片，其中，所述第一鳍片包括顶面以及第一横向侧壁和第二横向侧壁；
硬掩模层，形成在所述第一鳍片的所述顶面上；
栅极介电层，形成在所述硬掩模层以及所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上；
功函数金属层，形成在位于所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上的所述栅极介电层上；以及
硅化物层，形成在位于所述第一鳍片的所述第一横向侧壁和所述第二横向侧壁上的所述功函数金属层上。
2.根据权利要求1所述的半导体器件，还包括：设置在所述硅化物层上的金属填充层。
3.根据权利要求2所述的半导体器件，还包括：邻近所述第一鳍片的第二鳍片，其中，所述金属填充层介于所述第一鳍片和所述第二鳍片之间。
4.根据权利要求1所述的半导体器件，还包括第二鳍片，其中，所述硅化物层在所述第一鳍片和所述第二鳍片之间的厚度大于所述第一鳍片的高度，并且其中，所述第一鳍片的所述高度由所述第一鳍片在所述衬底上设置的隔离结构上方延伸的距离限定。
5.根据权利要求1所述的半导体器件，还包括第二鳍片，其中，所述硅化物层在所述第一鳍片和所述第二鳍片之间的厚度小于所述第一鳍片的高度，其中，所述第一鳍片的所述高度由所述第一鳍片在所述衬底上设置的隔离结构的上方延伸的距离限定。
6.一种制造半导体器件的方法，包括：
提供具有第一鳍片和第二鳍片的半导体衬底；
在所述第一鳍片和所述第二鳍片的顶面上形成硬掩模层；
在所述第一鳍片和所述第二鳍片上形成功函数金属层；
在所述功函数金属层上形成至少一个包含硅的层；以及
对所述至少一个包含硅的层实施硅化工艺从而形成硅化物层。
7.根据权利要求6所述的方法，还包括：
在所述硅化物层上形成填充金属层。
8.根据权利要求6所述的方法，其中，形成所述至少一个包含硅的层包括蚀刻在所述第一鳍片和所述第二鳍片上形成的多晶硅层以形成经过蚀刻的多晶硅层，并且其中，所述硅化工艺包括将所述经过蚀刻的多晶硅层转换成硅化物材料。
9.一种鳍式场效应晶体管(finFET)器件，包括：
第一鳍片和第二鳍片，其中，隔离结构介于所述第一鳍片和所述第二鳍片之间；
第一栅极结构，与所述第一鳍片的所述侧壁通过界面接合；
第二栅极结构，与所述第二鳍片的所述侧壁通过界面接合，其中，所述第一栅极结构和所述第二栅极结构每一个都包括完全硅化层，并且其中，所述完全硅化层对所述第一鳍片和所述第二鳍片的沟道区提供应力。
10.根据权利要求9所述的finFET器件，还包括：
硬掩模层，形成在所述第一栅极结构和所述第二栅极结构的顶面上。
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