CN108231687B - 半导体器件以及半导体器件制造的方法 - Google Patents
半导体器件以及半导体器件制造的方法 Download PDFInfo
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- CN108231687B CN108231687B CN201710985652.9A CN201710985652A CN108231687B CN 108231687 B CN108231687 B CN 108231687B CN 201710985652 A CN201710985652 A CN 201710985652A CN 108231687 B CN108231687 B CN 108231687B
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Abstract
本发明的实施例提供了金属栅极结构和相关方法,该方法包括在衬底上形成第一鳍和第二鳍。在各个实施例中,第一鳍具有第一栅极区域并且第二鳍具有第二栅极区域。例如,在第一栅极区域和第二栅极区域上方形成金属栅极线。在一些实施例中,金属栅极线从第一鳍延伸至第二鳍,并且金属栅极线包括牺牲金属部分。在各个实例中,实施线切割工艺以将金属栅极线分隔成第一金属栅极线和第二金属栅极线。在一些实施例中,牺牲金属部分防止线切割工艺期间的介电层的横向蚀刻。本发明的实施例还涉及半导体器件以及半导体器件制造的方法。
Description
技术领域
本发明的实施例总体涉及半导体领域,更具体地,涉及金属栅极结构及其方法。
背景技术
电子工业已经历对更小和更快的电子器件需求的不断增长,更小和更快的电子器件能够同时支持更多数量的越来越复杂和尖端的功能。因此,半导体工业的持续趋势是制造低成本、高性能和低功率的集成电路(IC)。到目前为止,已经通过按比例缩小半导体IC尺寸(例如,最小特征尺寸)并且从而提高生产效率以及降低相关成本,在很大程度上实现了这些目标。然而,这种按比例缩小也使半导体制造工艺的复杂度增加。因此,半导体IC和器件的持续进步的实现需要半导体制造工艺和技术中的类似进步。
已经引入多栅极器件以通过增加栅极沟道耦合而改进栅极控制、减小截止电流和降低短沟道效应(SCE)。已经引入的这样一种多栅极器件是鳍式场效应晶体管(FinFET)。FinFET得名于鳍状结构,该鳍状结构从所在衬底处延伸,并且该鳍状结构用于形成FET沟道。FinFET与传统的互补金属氧化物半导体(CMOS)工艺兼容并且它们的三维结构允许它们在保持栅极控制和缓解SCE的同时大大按比例缩小。此外,已经引入替换多晶硅栅电极的金属栅电极。金属栅电极提供了许多超越多晶硅栅电极的优势,诸如避免多晶硅耗尽效应、通过选择适当的栅极金属来调整功函以及其它益处。例如,金属栅电极制造工艺可以包括金属层沉积以及随后的金属层切割工艺。在一些情况下,金属层切割工艺可能导致层间电介质(ILD)的部分的损失,从而使器件的可靠性降低。
因此,现有的技术不是在所有方面都完全令人满意。
发明内容
根据本发明的一个方面,提供了一种半导体器件制造的方法,包括:在衬底上形成第一鳍和第二鳍,所述第一鳍具有第一栅极区域并且所述第二鳍具有第二栅极区域;在所述第一栅极区域和所述第二栅极区域上方形成金属栅极线,其中,所述金属栅极线从所述第一鳍延伸至所述第二鳍,并且其中,所述金属栅极线包括牺牲金属部分;以及实施线切割工艺以将所述金属栅极线分隔成第一金属栅极线和第二金属栅极线,其中,所述牺牲金属部分防止所述线切割工艺期间的介电层的横向蚀刻。
根据本发明的另一个方面,提供了一种方法,包括:形成从衬底延伸的多个鳍元件,所述多个鳍元件的每个均包括栅极区域,其中,介电层设置在每个邻近的所述栅极区域之间;在所述多个鳍元件的每个的所述栅极区域上方沉积第一功函金属层;在所述第一功函金属层上方形成牺牲金属层;在形成所述牺牲金属层之后,使用图案化的硬掩模层限定切割区域,其中,所述图案化的硬掩模层包括对应于限定的切割区域的开口;以及通过所述图案化的硬掩模层中的所述开口实施蚀刻工艺,以去除所述牺牲金属层和所述第一功函金属层,其中,所述牺牲金属层防止实施所述蚀刻工艺期间的所述介电层的去除。
根据本发明的又一个方面,提供了一种半导体器件,包括:第一鳍和第二鳍,从衬底延伸,所述第一鳍具有第一栅极区域并且所述第二鳍具有第二栅极区域;第一金属层,设置在所述第一栅极区域上方并且沿着介电层的第一侧的第一侧壁,其中,在线切割区域内形成所述介电层;以及第二金属层,设置在所述第二栅极区域上方并且沿着所述介电层的第二侧的与所述第一侧壁相对的第二侧壁;其中,所述第一金属层在所述第一栅极区域上方具有第一厚度,并且其中,所述第一金属层沿着所述介电层的所述第一侧的所述第一侧壁具有第二厚度。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据本发明的一个或多个方面的FinFET器件的实施例的立体图;
图2是根据一些实施例的相邻的鳍、金属栅极结构以及金属栅极切割图案的俯视图;
图3示出了根据至少一些现有工艺实施的金属栅极线切割工艺的FinFET结构的截面图;
图4示出了根据本发明的实施例的实施金属栅极线切割工艺的FinFET结构的截面图;
图5是根据本发明的一个或多个方面的半导体制造方法的流程图;
图6A、图7A、图8A、图9A、图10A、图11A和图12A示出了沿着基本平行于由图1的截面CC’限定的平面的平面并且根据图5的方法制造的FinFET结构的截面图;以及
图6B、图7B、图8B、图9B、图10B、图11B和图12B示出了沿着基本平行于由图1的截面AA’限定的平面的平面并且根据图5的方法制造的FinFET结构的截面图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上),而本文使用的空间相对描述符可以同样地做出相应的解释。
应该注意,本发明以多栅极晶体管或鳍式多栅极晶体管(在本文中称为FinFET器件)的形式来呈现实施例。这种器件可以包括P型金属氧化物半导体FinFET器件或N型金属氧化物半导体FinFET器件。FinFET器件可以是双栅极器件、三栅极器件、块状器件、绝缘体上硅(SOI)器件和/或其它结构。本领域普通技术人员可以想到其它得益于本发明的各方面的半导体器件的实施例。例如,本文中描述的一些实施例也可以应用于全环栅(GAA)器件、欧米茄栅极(Ω栅极)器件或Pi栅极(Π栅极)器件。
本发明通常涉及金属栅极结构以及相关的方法。具体地,本发明针对金属栅极切割工艺和相关结构。已经引入作为多晶硅栅电极的替换的金属栅电极。金属栅电极提供了许多超越多晶硅栅电极的优势,诸如避免多晶硅耗尽效应、通过选择适当的栅极金属调整功函以及其它益处。例如,金属栅电极制造工艺可以包括金属层沉积以及随后的金属层切割工艺。在一些情况下,金属层切割工艺可能导致层间电介质(ILD)的部分的损失,导致器件可靠性降低。
本发明的实施例提供了超越现有技术的优势,但是应该理解,其它实施例可以提供不同的优势,不是所有优势都有必要在此处讨论,并且没有特定的优势对所有实施例都是需要的。通常,并且根据此处公开的实施例,提供了金属栅极切割工艺和相关结构。本发明的至少一些实施例可以用于减少金属栅极切割工艺期间的层间电介质(ILD)损失。例如,在至少一些现有工艺中,金属栅极层的过蚀刻(例如,在金属栅极切割工艺期间)可能导致这种不期望的ILD损失。为了缓解这个问题,本发明的实施例提供了在鳍(例如,FinFET)上和相邻的线切割区域上具有不同厚度的金属栅极层或多层。此外,在至少一些实施例中,牺牲金属部分可以用于防止金属线切割工艺期间的横向蚀刻,从而有效地防止ILD损失。
图1中示出的是FinFET器件100。本文公开的各个实施例可以用于制造FinFET器件100和/或可以存在于FinFET器件100的最终结构中。FinFET器件100包括一个或多个基于鳍的、多栅极场效应晶体管(FET)。FinFET器件100包括衬底102、从衬底102处延伸的至少一个鳍元件104、隔离区域106以及设置在鳍元件104上和周围的栅极结构108。衬底102可以是诸如硅衬底的半导体衬底。衬底可以包括各个层,包括形成在半导体衬底上的导电或绝缘层。根据本领域中已知的设计需求,该衬底可以包括各种掺杂配置。该衬底也可以包括其它半导体,诸如锗、碳化硅(SiC)、硅锗(SiGe)或金刚石。可选地,该衬底可以包括化合物半导体和/或合金半导体。此外,在一些实施例中,该衬底可以包括外延层(epi层),该衬底可以受到应变以用于增强性能,该衬底可以包括绝缘体上硅(SOI)结构和/或该衬底可以具有其它合适的增强部件。
鳍元件104,类似于衬底102,可以包括:硅或另一元素半导体,诸如锗;化合物半导体,包括碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。可以使用包括光刻和蚀刻工艺的合适的工艺制造鳍104。光刻工艺可以包括:在衬底上面(例如,在硅层上)形成光刻胶层(抗蚀剂),使光刻胶曝光至图案,实施曝光后烘烤工艺,以及使光刻胶显影以形成包括光刻胶的掩蔽元件。在一些实施例中,可以使用极紫外(EUV)光刻工艺或电子束(e束)光刻工艺来实施图案化光刻胶以形成掩蔽元件。之后,该掩蔽元件可以用于在蚀刻工艺在硅层内形成凹槽的同时保护衬底的区域,从而留下延伸的鳍104。可以使用干蚀刻(例如,化学氧化去除)、湿蚀刻和/或其它合适的工艺来蚀刻凹槽。也可以使用方法的许多其它实施例来在衬底102上形成鳍104。
多个鳍104的每个也包括源极区域105和漏极区域107,其中,源极/漏极区域105、107形成在鳍104中、上和/或周围。可以在鳍104上方外延生长源极/漏极区域105、107。晶体管的沟道区域沿着平行于由图1的截面BB’限定的平面的平面设置在栅极结构108下面的鳍104内。在一些实例中,鳍的沟道区域包括高迁移率材料,诸如锗以及以上讨论的任何化合物半导体或合金半导体和/或它们的组合。高迁移率材料包括电子迁移率大于硅的那些材料。例如,高于在室温(300K)下具有约1350cm2/V-s的本征电子迁移率和约480cm2/V-s的空穴迁移率的Si。
隔离区域106可以是浅沟槽隔离(STI)部件。可选地,可以在衬底102上和/或内部实现场氧化物、LOCOS部件和/或其他合适的隔离部件。隔离区域106可以由氧化硅、氮化硅、氮氧化硅、氟掺杂的硅酸盐玻璃(FSG)、低k电介质、它们的组合和/或本领域中已知的其它合适的材料组成。在实施例中,隔离结构是STI部件并且通过在衬底102中蚀刻沟槽形成。之后,可以用隔离材料填充沟槽,随后是化学机械抛光(CMP)工艺。然而,其它实施例是可能的。在一些实施例中,隔离区域106可以包括多层结构,例如,具有一个或多个衬垫层。
栅极结构108包括具有形成在鳍104的沟道区域上方的界面层110、形成在界面层110上方的栅极介电层112以及形成在栅极介电层112上方的金属层114。界面层110可以包括诸如氧化硅层(SiO2)或氮氧化硅的介电材料。可以通过化学氧化、热氧化、原子层沉积(ALD)、化学汽相沉积(CVD)和/或其它合适的方法来形成界面层110。栅极介电层112可以包括诸如氧化铪(HfO2)的高k介电层。可选地,高k介电层可以包括其它高k电介质,诸如TiO2、HfZrO、Ta2O3、HfSiO4、ZrO2、ZrSiO2、它们的组合或其它合适的材料。仍在其它实施例中,栅极介电层可以包括二氧化硅或其它合适的电介质。可以通过ALD、物理汽相沉积(PVD)、氧化和/或其它合适的方法来形成介电层。金属层114可以包括诸如W、TiN、TaN、WN、Re、Ir、Ru、Mo、Al、Co、Ni、它们的组合和/或其它合适的组成的导电层。在一些实施例中,金属层114可以包括用于N型FinFET的第一金属材料和用于P型FinFET的第二金属材料。因此,FinFET器件100可以包括双功函金属栅极配置。例如,第一金属材料(例如,用于N型器件)可以包括功函与衬底导带的功函基本匹配的金属,或者功函至少基本与鳍104的沟道区域的导带的功函匹配的金属。类似地,例如,第二金属材料(例如,用于P型器件)可以包括功函基本与衬底价带的功函匹配的金属,或者功函至少基本与鳍104的沟道区域的价带的功函匹配的金属。因此,金属层114可以提供用于FinFET器件100(包括N型和P型FinFET器件100)的栅电极。在一些实施例中,金属层114可选择包括多晶硅层。可以使用PVD、CVD、电子束(e束)蒸发和/或其它合适的工艺形成金属层114。在一些实施例中,在栅极结构108的侧壁上形成侧壁间隔件。侧壁间隔件可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合的介电材料。
现在参照图2,图2中示出的是相邻的鳍204和设置在鳍204上方并且基本垂直于鳍204的金属栅极结构208的俯视图。在一些实施例中,图2的截面AA’可以基本平行于由图1的截面AA’限定的平面,并且图2的截面CC’可以基本平行于由图1的截面CC’限定的平面。在一些情况下,鳍204可以与以上描述的鳍104基本相同,并且金属栅极208可以与以上描述的栅极结构108的至少一些方面类似。例如,图2也示出了金属栅极切割图案210,其在一些实例中可以由图案化的硬掩模层限定。在一些实施例中,金属栅极切割图案210提供了开口(例如,在图案化的硬掩模层中),通过该开口实施金属栅极线切割(line-cut)工艺,并且可以切割金属栅极结构208的金属栅极层在该开口中的部分212。如此处描述的,金属栅极线切割工艺可以包括干蚀刻工艺、湿蚀刻工艺或它们的组合,该金属栅极线切割工艺用于去除金属栅极结构208的金属栅极层在由金属栅极切割图案210限定的区域内的部分。例如,金属栅极线切割工艺可以用于将金属栅极线切割成单独的、电断开的线。在一些实施例中,作为金属栅极线切割工艺的一部分,可以在线切割区域(例如,已经去除部分金属栅极层的地方)内形成介电层。
参照图3,图3中示出的是根据至少一些现有工艺的FinFET结构300的沿着基本平行于由图1的截面AA’限定的平面的平面截取的截面图,其中,实施金属栅极线切割工艺。FinFET结构300可以包括以上参照图1描述的一个或多个部件,诸如从衬底延伸的鳍元件304、隔离区域306以及设置在鳍元件304上和周围的栅极结构308。栅极结构308可以包括具有介电层310(包括界面层和栅极介电层)以及形成在介电层310上方的金属层的栅极堆叠件。在一些实例中,金属层可以包括第一金属材料312(例如,诸如P型功函金属(PWFM))、位于第一金属材料312上方的第二金属材料314(例如,诸如N型功函金属(NWFM))以及位于第二金属材料314上方的第三金属材料316(例如,诸如钨)。在各个实例中,可以在第三金属材料316上方形成介电层318。同样如图3示出的,第一金属材料312和第二金属材料314的总厚度定义为“T1”。在至少一些现有金属栅极线切割工艺中,第一金属材料312和第二金属材料314的厚度可能引起工艺挑战。例如,图3进一步示出了金属栅极切割区域320,其中,栅极结构308的金属层断开,并且如上所述,可以作为金属栅极线切割工艺的一部分,形成金属栅极切割区域320。在各种情况下,在随后的处理步骤中,可以在金属栅极切割区域320内形成介电层。特别值得注意的是,第一金属材料312和第二金属材料314可以具有从鳍元件304延伸至切割区域320的基本均匀的厚度T1。在一些情况下,在形成切割区域320之前,第一金属材料312和第二金属材料314也可以具有穿过切割区域320延伸的基本均匀的厚度T1,并且T1可以在线切割工艺期间被去除。在一些情况下,至少部分由于第一金属材料312和第二金属材料314在切割区域320处的厚度T1,至少一些现有工艺在金属栅极线切割工艺期间,可能需要显著地过蚀刻切割区域320内的金属层,以完全地去除设置在其中的金属层。由于这种过蚀刻,附近的介电层(例如,介电层318或其它层间电介质)可能存在显著的损失(例如,蚀刻)。因此,期望在金属栅极线切割工艺期间减少这种介电损失。
现在参照图4,图4中示出的是根据本发明的各个实施例的FinFET结构400沿着基本平行于由图1的截面AA’限定的平面的平面截取的截面图,其中,实施金属栅极线切割工艺。通常,本发明的实施例可以提供在FinFET的鳍元件上具有不同厚度的金属栅极层或多层,与相邻的线切割区域相比。此外,一些实施例提供了牺牲金属部分可以用于防止金属线切割工艺期间的横向蚀刻。FinFET结构400可以包括以上参照图1和图3描述的一个或多个部件,诸如从衬底延伸的鳍元件404、隔离区域406以及设置在鳍元件404上和周围的栅极结构408。栅极结构408可以包括具有介电层410(包括界面层和栅极介电层)以及形成在介电层410上方的金属层的栅极堆叠件。如上所述,金属层可以包括第一金属材料412(例如,PWFM)、第二金属材料414(例如,NWFM)以及第三金属材料416(例如,诸如钨)。在各个实例中,可以在第三金属材料416上方形成介电层418。图4也示出了金属栅极切割区域420,可以作为如上所述的金属栅极线切割工艺的一部分,形成金属栅极切割区域420,并且可以在随后的处理阶段期间在该区域内形成介电层。
与至少一些现有工艺(例如,图3)相反,并且在一些实施例中,第一金属材料412和第二金属材料414可以不具有从鳍元件404延伸至切割区域420的基本均匀的厚度T1。相反,在一些实施例中,如图4所示,第一金属材料412和第二金属材料414在鳍元件404上方可以具有总厚度‘T1’,而在相邻的切割区域420处具有小于T1的第二厚度‘T2’。在一些实施例中,可以在第二金属材料414的沉积之前实施用于形成切割区域420的金属栅极切割工艺。在一些实施例中,厚度T2对应于单个第一金属材料412(例如,PWFM)的厚度。因此,在一些情况下,在形成切割区域420之前,第二金属材料414可能不会沉积在切割区域420处。因此,在一些实施例中,可以在线切割工艺期间去除具有厚度T2的第一金属材料而不是具有厚度T1的第一金属材料和第二金属材料。在一些实施例中,由于单个第一金属材料412在切割区域420处的T2较薄(例如,与T1相比),因此本发明的实施例可以不需要如至少一些现有工艺的情况一样显著地过蚀刻切割区域420内的金属层。因此,可以避免附近的介电层(例如,介电层418或其它层间电介质)的损失(例如,通孔蚀刻)。此外,在一些实施例中,第三金属材料416可以包括诸如钨(W)的材料,其可以用作横向蚀刻停止材料。因此,可以通过第三金属材料416的横向蚀刻停止功能进一步缓解附近的介电层的横向蚀刻。在一些情况下,第三金属材料416是在随后的工艺步骤中去除的牺牲层。
现在参照图5,图5中所示的是根据至少一些实施例的半导体制造方法500的流程图。还可以在方法500之前、期间和之后提供额外的步骤,并且对于方法的额外的实施例,可以在其它步骤之前或之后替换、消除或移动所描述的一些步骤。还应注意,方法500是示例性的,并且不旨在限制本发明超出所附权利要求中明确列举的那些。以下将结合图6A、图6B、图7A、图7B、图8A、图8B、图9A、图9B、图10A、图10B、图11A、图11B以及图12A、图12B进一步描述方法500。图6A、图7A、图8A、图9A、图10A、图11A和图12A示出了FinFET结构600的沿着基本平行于由图1的截面CC’限定的平面的平面截取的截面图,以及图6B、图7B、图8B、图9B、图10B、图11B和图12B示出了FinFET结构600的沿着基本平行于由图1的截面AA’限定的平面的平面截取的截面图。
在各个实施例中,方法500开始于框502,其中,提供包括鳍和隔离区域的衬底。参照图6A和图6B的实例并且在框502的实施例中,示出了结构600。FinFET结构600可以包括以上参照图1描述的一个或多个部件,诸如从衬底延伸的鳍元件604、隔离区域606以及设置在鳍元件604上和周围的栅极结构608。在一些实施例中,可以如上所述形成鳍元件604。栅极结构608可以包括具有介电层(例如,包括界面层和栅极介电层)和形成在介电层上方的金属层的栅极堆叠件。
方法500进入框504,其中,沉积第一功函金属层。在一些实施例中,第一功函金属层包括PWFM。仍参照图6A和图6B的实例并且在框504的实施例中,在鳍元件604上方和周围形成包括PWFM层610的金属层。仅通过实例,PWFM层610可以包括Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。在各个实施例中,可以使用PVD、CVD、电子束(e束)蒸发和/或其它合适的工艺形成PWFM层610。
之后,方法500继续至框506,其中,沉积牺牲金属层并且实施化学机械抛光(CMP)工艺。在一些实施例中,牺牲金属层包括钨(W)层。根据各个实施例,如上所述,牺牲金属层用于缓解随后的金属栅极切割工艺期间的横向蚀刻。如图6A和图6B的实例所示,并且在框506的实施例中,形成牺牲金属层612并且实施CMP工艺以平坦化牺牲金属层612的顶面。图6A和图6B也示出了多个栅极堆叠件615,其可以具有形成在栅极堆叠件615的侧壁上的一个或多个侧壁间隔件层617。该侧壁间隔件层可以包括诸如氧化硅、氮化硅、碳化硅、氮氧化硅或它们的组合的介电材料。此外,在各个实施例中,介电层619可以介于多个栅极堆叠件615的每个之间。在至少一些实施例中,牺牲金属层612可以用于在随后的金属栅极切割工艺期间保护介电层619。
方法500继续至框508,其中,沉积且图案化硬掩模层。在一些实施例中,硬掩模层可以包括图案化的光刻胶层。可选地,在一些实施例中,硬掩模层可以包括诸如氮化硅、氮氧化硅、碳化硅或其它合适的材料的图案化的介电层。参照图6A和图6B的实例,沉积硬掩模层614。参照图7A和图7B的实例,图案化硬掩模层614。在一些实施例中,图案化的硬掩模层614包括限定之后将实施的金属栅极线切割的开口704。例如,在一些情况下,开口704可以对应于金属栅极切割图案(与图2的金属栅极切割图案210类似)。在各个实施例中,在开口704内暴露结构600的位于一个栅极堆叠件615上方的部分。在一些实施例中,开口704具有比暴露的栅极堆叠件615的邻近的侧壁间隔件之间的距离更大的宽度。在一些情况下,这放宽了用于金属栅极线切割工艺的光刻工艺的分辨率限制。
方法500进入框510,其中,实施金属栅极线切割工艺。参照图8A和图8B的实例并且在框510的实施例中,实施金属栅极线切割工艺。如图8A和图8B所示,线切割工艺可以用于通过开口704去除牺牲金属层612的暴露部分(包括其下方的PWFM层610)以形成线切口804。在一些实施例中,线切口804延伸至隔离区域606内并且有效地将邻近的栅极堆叠件中的导电栅极金属层彼此分隔开。例如,用于实施框510的金属栅极线切割工艺的蚀刻工艺可以包括湿蚀刻、干蚀刻和/或它们的组合。在一些实施例中,选择蚀刻工艺以选择性地蚀刻牺牲金属层612和PWFM层610而基本没有蚀刻侧壁间隔件617和介电层619。如上所述,由于切割区域内单个PWFM层610的T2较薄(例如,与T1相比),因此本发明的实施例可以至少不需要像一些现有工艺的情况一样显著地过蚀刻切割区域内的金属层。因此,可以避免附近的介电层(例如,介电层619)的损失(例如,通孔蚀刻)。在一些实施例中,在形成线切口804之后,可以通过蚀刻工艺去除图案化的硬掩模层614。在一些情况下,其中,图案化的硬掩模层614是图案化的光刻胶层,可以通过湿剥离和/或等离子体灰化去除图案化的硬掩模层614。
方法500继续至框512,其中,沉积介电层并且实施CMP工艺。参照图9A和图9B的实例,并且在框512实施例中,可以沉积介电层902并且实施CMP以平坦化介电层902的顶面。在一些实施例中,介电层902可以包括氧化硅、氮化硅、氮氧化物和/或其它合适的介电材料层。因此,在各个实施例中,介电层902可以进一步用于电隔离相邻的栅极堆叠件的栅极金属线。
在各种情况下,之后,方法500继续至框514,其中,如图10A和图10B的实例所示,去除牺牲金属层612。在各个实施例中,可以通过湿蚀刻、干蚀刻或它们的组合去除牺牲金属层612。在牺牲金属层612的去除之后,方法500继续至框516,其中,沉积第二功函金属层。在一些实施例中,第二功函金属层包括NWFM。参照图11A和图11B的实例,并且在框516的实施例中,在结构600上方形成包括NWFM层1110的金属层。仅作为实例,NWFM层1110可以包括Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。在各个实施例中,可以使用PVD、CVD、电子束(e束)蒸发和/或其它合适的工艺形成NWFM层1110。在一些实施例中,可以在NWFM层1110的形成之后实施回蚀刻工艺。
在一些实施例中,在形成NWFM层1110之后,胶层可以沉积在NWFM层1110上方。在一些实施例中,可以在胶层的形成之后实施回蚀刻工艺。之后,方法500继续至框518,其中,沉积金属层并且实施CMP工艺。参照图12A和图12B的实例,并且在框518的实施例中,形成金属层1202并且实施CMP工艺以平坦化金属层1202的顶面。在一些实施例中,金属层1202包括钨(W)层。可选地,在一些实施例中,金属层1202可以包括其它金属,诸如Ni、Pd、Pt、Be、Ir、Te、Re、Ru、Rh、W、Mo、WN、RuN、MoN、TiN、TaN、WC、TaC、TiC、TiAlN、TaAlN或它们的组合。在包括沉积在NWFM层1110上方的胶层的实施例中,金属层1202可以沉积在胶层上。
FinFET结构600可以经受进一步处理以形成本领域已知的各个部件和区域。例如,随后的处理可以在衬底上形成各个接触件/通孔/线和多层互连部件(例如,金属层和层间电介质),各个接触件/通孔/线和多层互连部件被配置为连接各个部件以形成可以包括一个或多个FinFET器件的功能电路。在进一步的实例中,多层互连可以包括垂直互连件(诸如通孔或接触件)以及水平互连件(诸如金属线)。各个互连部件可以采用包括铜、钨和/或硅化物的各种导电材料。在一个实例中,镶嵌和/或双镶嵌工艺用于形成含铜(copper-related)的多层互连结构。
本文描述的各个实施例提供了超越现有技术的若干优势。应该理解,不是所有优势都已经在此处讨论,没有特定的优势对所有实施例都是需要的,并且其它是实施例可以提供不同的优势。例如,本文讨论的实施例包括金属栅极切割工艺和相关结构。本发明的至少一些实施例可以应于减少金属栅极切割工艺期间的层间电介质(ILD)损失。例如,在至少一些现有工艺中,金属栅极层的过蚀刻(例如,在金属栅极切割工艺期间)可能导致这种不期望的ILD损失。为了缓解这个问题,本发明的实施例提供了在鳍(例如,FinFET)上和相邻的线切割区域上具有不同厚度的金属栅极层或多层。此外,在至少一些实施例中,牺牲金属部分可以用于防止金属线切割工艺期间的横向蚀刻,从而有效地防止ILD损失。因此,本发明的实施例用于克服至少一些目前光刻胶组成和方法的各个缺点。
因此,本发明的一个实施例描述了方法,该方法包括在衬底上形成第一鳍和第二鳍。在各个实施例中,第一鳍具有第一栅极区域并且第二鳍具有第二栅极区域。例如,在第一栅极区域和第二栅极区域上方形成金属栅极线。在一些实施例中,金属栅极线从第一鳍延伸至第二鳍,并且金属栅极线包括牺牲金属部分。在各个实例中,实施线切割工艺以将金属栅极线分隔成第一金属栅极线和第二金属栅极线。在一些实施例中,牺牲金属部分防止线切割工艺期间的介电层的横向蚀刻。
在一些实施例中,实施所述线切割工艺包括:在所述金属栅极线上方形成图案化的硬掩模,其中,所述图案化的硬掩模限定开口;以及通过所述开口蚀刻所述金属栅极线。
在一些实施例中,所述牺牲金属部分包括牺牲钨(W)层。
在一些实施例中,所述金属栅极线包括N型功函金属(NWFM),并且其中,在所述N型功函金属(NWFM)的沉积之前实施所述线切割工艺。
在一些实施例中,所述金属栅极线包括P型功函金属(PWFM),并且其中,在所述P型功函金属(PWFM)的沉积之后实施所述线切割工艺。
在一些实施例中,所述线切割工艺包括湿蚀刻工艺。
在一些实施例中,所述线切割工艺形成具有线切割区域侧壁的线切割区域,其中,所述金属栅极线在所述第一栅极区域和所述第二栅极区域的每个上方均具有第一厚度,并且其中,所述金属栅极线在所述线切割区域侧壁的每个处均具有第二厚度。
在一些实施例中,所述第二厚度小于所述第一厚度。
在一些实施例中,所述金属栅极线包括沉积在所述第一栅极区域和所述第二栅极区域的每个上方的P型功函金属(PWFM)和N型功函金属(NWFM),并且其中,所述金属栅极线包括沉积在所述线切割区域侧壁的每个处的N型功函金属(NWFM)。在另一个实施例中,讨论了方法,该方法包括形成从衬底延伸的多个鳍元件。在各个实施例中,多个鳍元件的每个均包括栅极区域、以及设置在每个相邻的栅极区域之间的介电层。在一些情况下,在多个鳍元件的每个的栅极区域上方沉积第一功函金属层。之后,在一些实施例中,在第一功函金属层上方形成牺牲金属层。在一些实施例中,在形成牺牲金属层之后,使用图案化的硬掩模层限定切割区域,其中,图案化的硬掩模层包括对应于限定的切割区域的开口。在各个实例中,之后,通过图案化的硬掩模层中的开口实施蚀刻工艺,以去除牺牲金属层和第一功函金属层。在一些实施例中,牺牲金属层防止实施蚀刻工艺期间的介电层的去除。
在一些实施例中,该方法还包括:在实施所述蚀刻工艺之后,在通过所述蚀刻工艺形成的线切割内沉积介电层;以及去除所述牺牲金属层。
在一些实施例中,该方法还包括:在所述第一功函金属层上方并且至少部分地在所述线切割内沉积的所述介电层的侧壁上方沉积第二功函金属层。
在一些实施例中,该方法还包括:在所述多个鳍元件的每个的所述栅极区域上方沉积胶层;以及在所述胶层上方形成金属层。
在一些实施例中,所述第一功函金属层包括P型功函金属(PWFM)。
在一些实施例中,所述第二功函金属层包括N型功函金属(NWFM)。
在一些实施例中,所述图案化的硬掩模层具有比暴露的栅极堆叠件的邻近的侧壁间隔件之间的距离更大的宽度。
在又一实施例中,讨论了半导体器件,该半导体器件包括从衬底延伸的第一鳍和第二鳍,第一鳍具有第一栅极区域并且第二鳍具有第二栅极区域。在一些实施例中,该器件也包括设置在第一栅极区域上方并且沿着介电层的第一侧的第一侧壁的第一金属层,其中,在线切割区域内形成介电层。此外,该器件可以包括设置在第二栅极区域上方并且沿着介电层的第二侧的与第一侧壁相对的第二侧壁的第二金属层。在各个实施例中,第一金属层在第一栅极区域上方具有第一厚度,并且第一金属层沿着介电层的第一侧的第一侧壁具有第二厚度。
在一些实施例中,所述第二厚度小于所述第一厚度。
在一些实施例中,所述第二金属层在所述第二栅极区域上方具有所述第一厚度,并且其中,所述第二金属层沿着所述介电层的所述第二侧的所述第二侧壁具有所述第二厚度。
在一些实施例中,所述第一金属层和所述第二金属层包括位于所述第一栅极区域和所述第二栅极区域的每个上方的P型功函金属(PWFM)和N型功函金属(NWFM),并且其中,所述第一金属层和所述第二金属层包括沉积在所述介电层的所述第一侧壁和所述第二侧壁的每个处的N型功函金属(NWFM)。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,他们可以容易地使用本发明作为基础来设计或修改用于实施与本人所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中他们可以做出多种变化、替换以及改变。
Claims (20)
1.一种半导体器件制造的方法,包括:
在衬底上形成第一鳍和第二鳍,所述第一鳍具有第一栅极区域并且所述第二鳍具有第二栅极区域;
在所述第一栅极区域和所述第二栅极区域上方形成金属栅极线,其中,所述金属栅极线从所述第一鳍延伸至所述第二鳍,并且其中,所述金属栅极线包括牺牲金属部分;以及
实施线切割工艺以将所述金属栅极线分隔成第一金属栅极线和第二金属栅极线,其中,所述牺牲金属部分防止所述线切割工艺期间的介电层的横向蚀刻。
2.根据权利要求1所述的方法,其中,实施所述线切割工艺包括:
在所述金属栅极线上方形成图案化的硬掩模,其中,所述图案化的硬掩模限定开口;以及
通过所述开口蚀刻所述金属栅极线。
3.根据权利要求1所述的方法,其中,所述牺牲金属部分包括牺牲钨(W)层。
4.根据权利要求1所述的方法,其中,所述金属栅极线包括N型功函金属(NWFM),并且其中,在所述N型功函金属(NWFM)的沉积之前实施所述线切割工艺。
5.根据权利要求1所述的方法,其中,所述金属栅极线包括P型功函金属(PWFM),并且其中,在所述P型功函金属(PWFM)的沉积之后实施所述线切割工艺。
6.根据权利要求1所述的方法,其中,所述线切割工艺包括湿蚀刻工艺。
7.根据权利要求1所述的方法,其中,所述线切割工艺形成具有线切割区域侧壁的线切割区域,其中,所述金属栅极线在所述第一栅极区域和所述第二栅极区域的每个上方均具有第一厚度,并且其中,所述金属栅极线在所述线切割区域侧壁的每个处均具有第二厚度。
8.根据权利要求7所述的方法,其中,所述第二厚度小于所述第一厚度。
9.根据权利要求7所述的方法,其中,所述金属栅极线包括沉积在所述第一栅极区域和所述第二栅极区域的每个上方的P型功函金属(PWFM)和N型功函金属(NWFM),并且其中,所述金属栅极线包括沉积在所述线切割区域侧壁的每个处的N型功函金属(NWFM)。
10.一种半导体器件制造的方法,包括:
形成从衬底延伸的多个鳍元件,所述多个鳍元件的每个均包括栅极区域,其中,介电层设置在每个邻近的所述栅极区域之间;
在所述多个鳍元件的每个的所述栅极区域上方沉积第一功函金属层;
在所述第一功函金属层上方形成牺牲金属层;
在形成所述牺牲金属层之后,使用图案化的硬掩模层限定切割区域,其中,所述图案化的硬掩模层包括对应于限定的切割区域的开口;以及
通过所述图案化的硬掩模层中的所述开口实施蚀刻工艺,以去除所述牺牲金属层和所述第一功函金属层,其中,所述牺牲金属层防止实施所述蚀刻工艺期间的所述介电层的去除。
11.根据权利要求10所述的方法,还包括:
在实施所述蚀刻工艺之后,在通过所述蚀刻工艺形成的线切割内沉积介电层;以及
去除所述牺牲金属层。
12.根据权利要求11所述的方法,还包括:
在所述第一功函金属层上方并且至少部分地在所述线切割内沉积的所述介电层的侧壁上方沉积第二功函金属层。
13.根据权利要求12所述的方法,还包括:
在所述多个鳍元件的每个的所述栅极区域上方沉积胶层;以及
在所述胶层上方形成金属层。
14.根据权利要求10所述的方法,其中,所述第一功函金属层包括P型功函金属(PWFM)。
15.根据权利要求12所述的方法,其中,所述第二功函金属层包括N型功函金属(NWFM)。
16.根据权利要求10所述的方法,其中,所述图案化的硬掩模层具有比暴露的栅极堆叠件的邻近的侧壁间隔件之间的距离更大的宽度。
17.一种半导体器件,包括:
第一鳍和第二鳍,从衬底延伸,所述第一鳍具有第一栅极区域并且所述第二鳍具有第二栅极区域;
第一金属层,设置在所述第一栅极区域上方并且沿着介电层的第一侧的第一侧壁,其中,在线切割区域内形成所述介电层;以及
第二金属层,设置在所述第二栅极区域上方并且沿着所述介电层的第二侧的与所述第一侧壁相对的第二侧壁;
其中,所述第一金属层在所述第一栅极区域上方具有第一厚度,并且其中,所述第一金属层沿着所述介电层的所述第一侧的所述第一侧壁具有第二厚度。
18.根据权利要求17所述的半导体器件,其中,所述第二厚度小于所述第一厚度。
19.根据权利要求17所述的半导体器件,其中,所述第二金属层在所述第二栅极区域上方具有所述第一厚度,并且其中,所述第二金属层沿着所述介电层的所述第二侧的所述第二侧壁具有所述第二厚度。
20.根据权利要求17所述的半导体器件,其中,所述第一金属层和所述第二金属层包括位于所述第一栅极区域和所述第二栅极区域的每个上方的P型功函金属(PWFM)和N型功函金属(NWFM),并且其中,所述第一金属层和所述第二金属层包括沉积在所述介电层的所述第一侧壁和所述第二侧壁的每个处的N型功函金属(NWFM)。
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TWI668745B (zh) | 2019-08-11 |
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US20200152757A1 (en) | 2020-05-14 |
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US10535746B2 (en) | 2020-01-14 |
KR102143164B1 (ko) | 2020-08-12 |
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