CN107403715B - 使用掺杂抛光材料控制内部裸片的均匀性 - Google Patents

使用掺杂抛光材料控制内部裸片的均匀性 Download PDF

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CN107403715B
CN107403715B CN201710356596.2A CN201710356596A CN107403715B CN 107403715 B CN107403715 B CN 107403715B CN 201710356596 A CN201710356596 A CN 201710356596A CN 107403715 B CN107403715 B CN 107403715B
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oxide layer
mask
fin
fin structures
silicon
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CN107403715A (zh
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黄海苟
刘金平
刘黄
T·赵
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GlobalFoundries US Inc
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Abstract

本发明涉及使用掺杂抛光材料控制内部裸片的均匀性，各种实施例包括方法以及集成电路结构。在某些情况下，形成一集成电路结构的一方法可包括：形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层；通过一开口注入该氮化层于该掩膜中；移除该掩膜；于移除该掩膜后，抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及形成一氮化层于该鳍片结构组的上方。

Description

使用掺杂抛光材料控制内部裸片的均匀性
技术领域
本发明公开的主题涉及集成电路设备。更具体而言，该主题涉及形成集成电路设备的工艺。
背景技术
随着集成电路(IC)技术的不断进步，这些设备的尺寸也相应减小。特别是，作为设备的规模减小以符合越来越小的封装，更严格的约束应用于它们的尺寸和间距。
更小的集成电路要求用于形成独立的集成电路芯片的该裸片内部具有更好的均匀性。例如，一些产品的限制可能会要求小于两纳米(nm)的内部裸片的均匀性。这些约束可能特别难以满足某些工艺方法，例如化学机械抛光(CMP)，于该工艺方法中，宏观负载(macro-loading)会导致该裸片内部的结构密度的变化。
发明内容
各种实施例包括方法以及集成电路结构。在某些情况下，形成一集成电路的一方法可包括：形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层；通过该掩膜中的一开口将离子注入该氧化层；移除该掩膜；于移除该掩膜后抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及形成一氮化层于该鳍片结构组的上方。
本发明的一第一方面包括形成一集成电路结构的一方法，该方法包括：形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层；通过该掩膜中的一开口将离子注入该氧化层；移除该掩膜；于移除该掩膜后，抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及形成一氮化层于该鳍片结构组的上方。
本发明的一第二方面包括形成一集成电路结构的一方法，该方法包括：形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层；用碳、磷或硼中的至少一种离子通过该掩膜中的一开口注入该氧化层；移除该掩膜；于移除该掩膜后，抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及形成一氮化层于该鳍片结构组的上方，其中该氮化层的一高度于该鳍片结构组上为基本一致。
本发明的一第三方面包括一集成电路(IC)结构，具有：一基板；一鳍片结构组，其覆盖于该基板上，各该鳍片结构组包括一基板基部以及位于该基板基部上方的一硅化层；一氧化物，其位于该鳍片结构组中的相邻鳍片之间；以及一氮化层，其位于该鳍片结构组的上方，其中，该氮化层的一高度于该鳍片结构组上为基本一致。
附图说明
通过以下针对本发明的各个方面的详细描述并结合用于描绘本发明的各种实施例的附图，本发明的这些以及其他特征将变得更容易理解，其中：
图1为根据本发明的各种实施例的一方法中的流程示意图。
图2A为根据本发明的各种实施例所示的通过第一鳍片结构组的一前体结构内部的一第一区域的一示意性截面视图。
图2B显示了图2A的该前体结构中一第二区域的一示意性截面视图，该截面通过一第二鳍片结构组。
图3A为根据各种实施例所示的处于一工艺中的一结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图3B为图3A的该结构的一第二区域的一示意性截面视图，该截面通过一第二鳍片结构组。
图4A为根据各种实施例所示的处于一工艺中的一结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图4B为图4A的该结构的一第二区域的一示意性截面图，该截面通过一第二鳍片结构组。
图5A为根据各种实施例所示的处于一工艺中的一结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图5B为图5A的该结构的一第二区域的一示意性截面图，该截面通过一第二鳍片结构组。
图6A为根据各种实施例所示的处于一工艺中的一结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图6B为图6A的该结构的一第二区域的一示意性截面图，该截面通过一第二鳍片结构组。
图7A为根据各种实施例所示的处于一工艺中的一结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图7B为图7A的该结构的一第二区域的一示意性截面图，该截面通过一第二鳍片结构组。
图8A为根据各种实施例所示的一集成电路(IC)结构的一第一区域的一示意性截面图，该截面通过一第一鳍片结构组。
图8B为图8A的该结构的一第二区域的一示意性截面图，该截面通过一第二鳍片结构组。
应注意的是，本发明的图示不一定按照比例绘制。该图示仅用于描述本发明的典型方面，因此不应被视为限制本发明的范围。在图示中，图示之间相似的编号代表相似的元件。
具体实施方式
如上所述，在此所披露的该主题涉及集成电路(IC)设备。更具体而言，该主题涉及控制集成电路设备中的内部裸片均匀性。
本文所述的该术语“内部裸片均匀性”是指在一给定裸片内的高度及/或密度的一致性。众所周知，形成IC设备的该工艺中，材料层常常在一大的晶圆的上方形成、修饰等等，然后被切割(或切块)以形成独立裸片，其中的每一个被称为一裸片。
与常规方法相比，本发明的各种实施例包括用于在一IC结构或设备的一层中形成具有基本一致的高度的氮化物区域的方法。也就是，根据各种实施例，本文所述的方法可以控制(例如增进)IC结构中的内部裸片的均匀性(例如硅化层中的高度一致性)。
在下面的描述中，所附的图示构成参考的一部分，其通过可以实行的本案的教示以说明具体实施例的方式予以显示。这些实施例通过足够充分详细的描述以使本领域的技术人员能够实践本案的教示，并应理解为其他的实施例方式也可以利用，且可在不脱离当前教示范围的情况下进行变更。因此，下面的描述仅仅是说明性的。
正如本文所述，“沉积”可包括任何适用于材料沉积的现有已知或将来开发的技术，包括但不限于例如：化学气相沉积(CVD)、低压化学气相沉积(LPCVD)、等离子体增强化学气相沉积(PECVD)、半大气化学气相沉积(SACVD)以及高密度等离子体化学气相沉积(HDPCVD)、快热化学气相沉积(RTCVD)、超高真空化学气相沉积(UHVCVD)，限制反应工艺化学气相沉积(LRPCVD)，金属有机物化学气相沉积(MOCVD)，溅射沉积(sputteringdeposition)，离子束沉积(ion beam deposition)，电子束沉积(electron beamdeposition)，激光辅助沉积(laser assisted deposition)，热氧化，热氮化，旋涂(spin-on)方法、物理气相沉积(PVD)、原子层沉积(ALD)，化学氧化法(chemical oxidation)，分子束外延(molecular beam epitaxy；MBE)，电镀，蒸发法(evaporation)。
图1为说明根据本发明的各种实施例所执行的工艺的一流程图。通过图8A及图8B的图2A及图2B为用于说明根据各实施例所执行的工艺的集成电路结构(及前体结构)的区域的截面示意图。应理解的是，在此所列的工艺可以按照在一些实施例中所描述的不同顺序予以执行。此外，并非所有在此列出的工艺都必须根据各实施例予以执行。
转向通过图8A及图8B的图2A及图2B，并继续参考图1，其为根据各实施例所示的执行在前体结构2的一第一区域1(图2A)与前体结构2的一第二区域3上所形成一集成电路(IC)结构26(如图8A及图8B)的工艺的示意图。用数字“A”标注的第一区域1包括相对于用数字“B”标注的一较低密度区域(第二区域3)的一较高密度区域(具有更多数量的鳍片8)。如图2A及图2B所示，前体结构2可包括一鳍片结构组6上方的一氧化层4，其中，该底层鳍片结构组6可包括具有一基板基部10以及覆盖该基板基部10的一硅化层12的多个鳍片8。在各种实施例中，氧化层4可包括二氧化硅(SiO2)。如图2A至图7B所示为关于两个不同的区域1,3(穿过鳍片8的截面)的工艺。
基板基部10可从一基板12形成(例如蚀刻)，基板12可包括硅、掺杂的硅或硅锗。在某些情况下，基板12可包括一个或多个基板材料，例如硅、锗、硅锗、碳化硅，以及本质上由具有由公式AlX1GaX2InX3AsY1PY2NY3SbY4所定义的一个或多个III-V族化合物半导体所组成的那些材料，其中，X1、X2、X3、Y1、Y2、Y3及Y4代表相对比例，其每一个均大于或等于零，且X1+X2+X3+Y1+Y2+Y3+Y4＝1(1为总相对摩尔量)。其他适合的基板包括具有一ZnA1CdA2SeB1TeB2组成的II-VI族化合物半导体，其中，A1、A2、B1、及B2为相对比例，每一者均大于或等于零，且A1+A2+B1+B2＝1(1为一总摩尔量)。此外，基板12的一部分或整体可以形变(strained)。在不同的实施例中，例如，在包括一掺杂硅的基板12中、基板12可包括元素半导体材料(elemental semiconductor materials)(例如，硅、锗、碳、或其合金)，III-V族半导体材料，或II-VI族半导体材料。根据各种实施例，该(掺杂的)硅基板12沉积为一块状硅，最后进行离子化以掺杂该体硅材料(bulk silicon material)。在其他情况下，基板12的一部分被电离(例如，受到电离辐射)以形成一掺杂的硅层。在不同的实施例中，一传统的掩膜及蚀刻工艺用于形成鳍片8，例如从基板基部10，例如包括于基板基部10的上方形成一硬掩膜并使用该掩膜蚀刻该底层硅(例如掺杂硅)以移除该基板基部10位于该多个鳍片8之间的部分。然而，应理解的是，鳍片8可根据本领域中各种已知的方法而形成。在非限制性的示例中，鳍片8可通过图案化基板基部12上方的鳍片8的部分等方式以外延生长基板12上方的鳍片8的至少一部分而形成。
如图所示，根据不同实施例中的工艺可包括：
如图2A至图2B以及图3A至图3B所说明的工艺P1A(根据不同实施例的一可选预处理工艺)，包括：抛光氧化层4，其中，氧化层4包括该抛光(图3A，图3B)之前的表面轮廓(surface contours)14(图2A，图2B)。在不同的实施例中，表面轮廓14可包括形成氧化层4的一不均匀上表面的凸块或凸起。在不同的实施例中，抛光氧化层4包括执行本领域中的一传统的化学机械抛光(平坦化)技术，例如使用一抛光设备以及一化学浆料以移除部分氧化层4。如图2A及图2B所示，在抛光之前，表面轮廓14可能由于氧化层4形成于底层鳍片8的上方以及那些鳍片8之间的空隙而存在。表面轮廓14可对应于在一特定区域中的鳍片8的一密度，例如，由于当相比于第二区域3时，第一区域1的鳍片8的密度更高，而使其可能具有一更大浓度的表面轮廓14。
工艺P1(在不同的实施例中，图3A及图4A所示的工艺P1A之后)：于氧化层4以及一底层鳍片结构组8的上方形成一掩膜16。在不同的实施例中，掩膜16可包括一传统光阻及/或掩膜材料，例如一氮化物，如氮化硅。在某些情况下，使用传统的沉积技术沉积掩膜16于氧化层4的上方，然后，在其他情况下，掩膜16可以外延生长或其他方式形成于氧化层4的上方。在某些情况下，掩膜16可使用传统的光刻技术而形成，包括但不限于深紫外线(DUV)或极端紫外线(EUV)工艺，侧壁成像转移工艺，或多个图案化工艺。在各种实施例中，如图4A及图4B的并行比较所示，掩膜16可以选择性的仅形成于一区域(例如第一区域1)的上方，且未形成于其他一个或多个区域(例如第二区域3)的上方。
工艺P2(如图5A及图5B所示)：通过掩膜16中的一开口18(将离子17)注入氧化层4。如图5A及图5B所示，掩膜16可形成于第一区域1中的鳍片8的上方，留下鳍片结构6于通过一个或多个开口18而暴露的第二区域3中(例如在具有一较低浓度的鳍片8的区域中，其中，鳍片8相邻于大氧化区域20)。在各种实施例中，通过传统的离子注入技术在氧化物4以及氧化区域20(例如分离相邻的多组鳍片结构6)中注入离子17。掩膜16可以防止注入至氧化层4及鳍片8的底层区域中。在某些情况下，使用碳(C)，磷(P)或硼(P)的至少一种的离子进行离子注入。相比于第一区域1中的非注入氧化物4，使用C,P或B离子的注入可以减少后续第二区域3中氧化物4的移除率(例如抛光率)。
工艺P3(如图6A及图6B所示的后注入)：移除掩膜16，例如通过传统蚀刻技术，如湿蚀刻或干蚀刻。在某些情况下，可以使用一化学蚀刻工艺将掩膜16从第一区域1移除。例如，剩余的掩膜16可以通过干等离子灰化或(选择性的)湿法清洗(如使用过氧化硫酸)而移除。如图所示，在先前暴露于掩膜16之间的第二区域3中的氧化层4的一部分21中注入离子。
工艺P4(图7A，图7B)：在移除掩膜16之后，抛光覆盖该鳍片结构组6的氧化层4以暴露该鳍片结构组6的一上表面23。在各种实施例中，抛光氧化层4包括执行本技术领域中已知的一传统的化学机械抛光(平坦化)技术，例如使用一抛光设备及一化学浆料以移除部分氧化层4。在某些情况下，是在穿过第一区域1以及第二区域3的一单一工艺中执行抛光，因此，无需针对相比于较高密度区域(例如第一区域1)的较低密度区域(例如第二区域3)的附加工艺。
工艺P5(图8A，图8B)：形成一氮化层22于该鳍片结构组6上方。在各种实施例中，氮化层22可包括氮化硅(SiN)。根据一些实施例，形成氮化层22可包括形成(如沉积)一硅(如薄层)于暴露的鳍片结构组6以及氧化层4的一剩余部分24的上方，以及将硅暴露于氮气并加热以将该硅转化为SiN。根据各种实施例，例如为在低密度区域(第二区域3)的大氧化区域20中注入氧化物4，可以减少这些区域中的该氧化物4的该移除率，并且允许氮化层22在相邻鳍片8之间的一宽间隙上水平形成。
也就是，抛光工艺(P4)是减少氧化层4内游离氧化物残基的一个重要工艺。然而，如本文所述，大的氧化区域的存在之处，例如第二区域3中的氧化物4，来自抛光的宏观负载会导致传统氧化结构的抛光速率不同，非理想的快。根据本发明的各种实施例，这些区域(例如第二区域3中的大的氧化区域20)中的氧化物4被离子注入，以相比于在更密集封装区域(如第一区域1)中的氧化物4，减少其氧化物4的移除(如抛光)率。相比于第一区域1中氧化物4，通过减少第二区域3中的大的氧化区域20的该移除率，可以在该两个区域1,3之间形成一更均匀的上表面，允许IC结构26中的氮化层22的水平形成。
根据各种实施例，如图8A及图8B所示的该IC结构26中，氮化层22的一高度(h)于该鳍片结构组6上基本一致，例如氮化层22具有于该鳍片结构6以及氧化物4上的一基本一致的厚度。换句话说，通过一平面(p)来衡量，该基本一致的高度(h)被定义为在该鳍片结构组6与氧化物4上方的氮化层上具有小于约2纳米的一偏差。如本文所述，形成氮化层22以使其具有在IC结构26中的一高度一致性，可以帮助克服与传统集成电路中的非均匀密度相关的性能问题。
应了解的是，在此所述的方法可以在形成集成电路的任意阶段予以执行，例如，前道工序(FEOL)，后道工序(BEOL)及/或中间工序(MOL)工艺。如本领域技术人员所悉知，FEOL可包括在设备制造至第一金属化的过程中，于该半导体裸片上进行的操作，BEOL可包括在设备制造后的第一金属化的过程中，于该半导体裸片上进行的操作，以及MOL可包括第一金属化期间，于该半导体裸片上进行的操作。
当一个元件或层被称为在另一元件或层“上”，或“接合”、“连接”或“耦接”至另一元件或层时，其可能直接位于该另一元件或层上，直接接合、连接或耦接至另一元件或层，或者可能存在中间元件或层。相反的，当一元件被称为直接位于另一元件或层“上”，或“直接接合”、“直接连接”或“直接耦接”至另一元件或层，可能不存在中间元件或层。用于描述元件之间的关系的其他的词应该以类似的方式来解释(例如，“之间”对“直接之间”，“邻接”对“直接邻接”等)。如本文所述，该术语“及/或”包括该一个或多个相关联的列表项的任意以及所有组合。
空间相关术语，如“内”、“外”、“下”、“下方”、“低于”、“上方”、“上”等，可易于描述图示中一个元件或特征与另一元件或特征的关系描述。空间上的相对术语可包括使用或操作中的该设备的不同方向，除了在图中描绘的方向。例如，如果图中的该设备被翻转，被描述为位于其他元件或特征“下”或“下面”的元件则将转为位于该其他元件或特征的“上方”。因此，该设备或可以旋转(旋转90度或其他方向)，且本文所使用的该空间上的相关描述亦作此相应的解释。
本文所使用的该术语仅用于描述特定的实施例的目的，但并非用于限制本发明。本文所使用的，该单数形式的“一”、“一个”和“该”也可包括复数形式，除非上下文有清楚的表明。还应了解的是，在本说明书中使用的该术语“包括”及/或“包含”用于指定声明的特征、整数、步骤、操作、元件、及/或组件的存在，但不排除存在或添加一个或多个其他的特征、整数、步骤、操作、元件、组件、及/或上述各项的组合。还应了解的是，该术语“前”和“后”并不意味着限制，并在适当的地方可以进行互换。
此书面说明书所使用的实施例用于揭示本发明，包括最好的模式，可用于使本领域的任何技术人员可实践本发明，包括制造和使用任何设备或系统，以及执行任何并入方法。本发明的可专利范围是由权利要求书所定义，并可包括其他发生在这些技术领域的实施例。如果具有与该权利要求书的字面语言并非不同的结构元件，或包括与该权利要求的字面语言存在无实质差异的等效性结构元件，这些其他的实施例亦应在权利要求的保护范围内。
本发明的各种实施例的描述仅用于说明，其并非详尽且并不局限于所揭示的这些实施例。在不背离所述实施例的范围及精神下，各种修改或变更对于本领域的技术人员而言将是显而易见的。本文所使用的术语被用于最好地解释各实施例的原则，在市场上发现的技术的实际应用或技术改进，或使本领域的其他技术人员了解本文所揭示的实施例。

Claims (16)

1.一种形成一集成电路（IC）结构的方法，该方法包括：
形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层，该鳍片结构组在该掩膜下方的该氧化层的第一区域中具有相较于该掩膜中的一开口下方的该氧化层的第二区域中较高的鳍片密度；
将离子通过该掩膜中的该开口注入该氧化层；
移除该掩膜；
于移除该掩膜后，抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及
形成一氮化层于该鳍片结构组的上方。
2.根据权利要求1所述的方法，其中，该氮化层的一高度于该鳍片结构组上为一致。
3.根据权利要求2所述的方法，其中，该一致的高度被定义为在该鳍片结构组上方的该氮化层上具有小于2纳米的一偏差。
4.根据权利要求1所述的方法，还包括在形成该掩膜之前抛光该氧化层，其中该氧化层包括于该抛光之前的表面轮廓。
5.根据权利要求1所述的方法，其中，将离子注入该氧化层包括使用碳、磷或硼的至少一种进行离子注入。
6.根据权利要求1所述的方法，其中，该氮化层包括氮化硅（SiN）。
7.根据权利要求6所述的方法，其中，形成该氮化层包括形成一硅于暴露的该鳍片结构组以及该氧化层的一剩余部分的上方，以及将该硅暴露于氮气并加热以将硅转化为氮化硅。
8.根据权利要求1所述的方法，其中，该基板基部包括硅或硅锗。
9.根据权利要求1所述的方法，其中，该氧化层包括二氧化硅（SiO2）。
10.一种形成一集成电路（IC）结构的方法，该方法包括：
形成一掩膜于一氧化层以及一底层鳍片结构组的上方，该鳍片结构组包括多个鳍片，各该鳍片具有一基板基部以及位于该基板基部上方的一硅化层，该鳍片结构组在该掩膜下方的该氧化层的第一区域中具有相较于该掩膜中的一开口下方的该氧化层的第二区域中较高的鳍片密度；
用碳、磷或硼中的至少一种离子通过该掩膜中的该开口注入该氧化层；
移除该掩膜；
于移除该掩膜后，抛光覆盖该鳍片结构组的该氧化层以暴露该鳍片结构组；以及
形成一氮化层于该鳍片结构组的上方，其中该氮化层的一高度于该鳍片结构组上为一致。
11.根据权利要求10所述的方法，其中，该一致的高度被定义为在该鳍片结构组上方的该氮化层上具有小于2纳米的一偏差。
12.根据权利要求10所述的方法，还包括于形成该掩膜之前抛光该氧化层，其中该氧化层包括该抛光之前的表面轮廓。
13.根据权利要求10所述的方法，其中，该氮化层包括氮化硅（SiN）。
14.根据权利要求13所述的方法，其中，形成该氮化层包括形成一硅于暴露的该鳍片结构组以及该氧化层的一剩余部分的上方，以及将该硅暴露于氮气并加热以将该硅转化为氮化硅。
15.根据权利要求10所述的方法，其中，该基板基部包括硅或硅锗。
16.根据权利要求10所述的方法，其中，该氧化层包括二氧化硅（SiO2）。
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