CN107039347B - 使用虚设栅极形成具有应力的外延层 - Google Patents

使用虚设栅极形成具有应力的外延层 Download PDF

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CN107039347B
CN107039347B CN201610873305.2A CN201610873305A CN107039347B CN 107039347 B CN107039347 B CN 107039347B CN 201610873305 A CN201610873305 A CN 201610873305A CN 107039347 B CN107039347 B CN 107039347B
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CN107039347A (zh
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E·阿尔普泰金
L·W·利布曼
I·奥克
B·普拉纳萨尔西哈兰
R·拉马钱德兰
S·C·徐
C·V·V·S·苏里塞特特伊
M·H·余
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Abstract

本发明涉及使用虚设栅极形成具有应力的外延层，各种实施例包括方法以及集成电路结构。在一些情况下，形成集成电路结构的方法可包括：在衬底上方形成一掺杂硅层；自该掺杂硅层形成多个鳍片结构；在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；以及在该二个剩余的栅极结构之间的该衬底上方形成外延区域。

Description

使用虚设栅极形成具有应力的外延层
技术领域
本发明揭示的主题涉及集成电路装置。更具体地说，本发明涉及在集成电路装置中形成栅极结构。
背景技术
随着集成电路(IC)技术的进步，该些装置的尺寸也相应减小。特别是，缩小装置的尺寸以符合越来越小的封装，将对它们的尺寸及间隔施加更紧密的限制。
在IC装置中具有应力(stress)的栅极区是一种有效的机构，用于提高流经该些栅极区的信号的效能(例如，速度)。然而，随着装置尺寸减小，相邻的集成电路栅极之间的距离(间距，pitch)被减小。该减小的栅极间距使得形成IC时更难以有效地向栅极区施加应力，对效能产生不利的影响。此外，减小的栅极间距可导致接触电阻降低、接触(contact)至栅极间短路，以及其它不希望的情况。
发明内容
各种实施例包括方法以及集成电路结构。在一些情况下，一种形成集成电路结构的方法可包括：在衬底上方形成一掺杂硅层；自该掺杂硅层形成多个鳍片(fin)结构；在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；以及在该二个剩余的栅极结构之间的该衬底上方形成外延区域。
本发明的第一态样包括一种形成集成电路结构的方法，该方法包括：在衬底上方形成一掺杂硅层；自该掺杂硅层形成多个鳍片结构；在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；以及在该二个剩余的栅极结构之间的该衬底上方形成外延区域。
本发明的第二态样包括一种形成集成电路结构的方法，该方法包括：在衬底上方形成一掺杂硅层；自该掺杂硅层形成多个鳍片结构；在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；在该二个剩余的栅极结构之间的该衬底上方形成第一外延区域；在通过该第一间距分开的该多个栅极结构之间的该衬底上方形成多个外延区域；以及在该第一外延区域上方形成接触以直接接触该第一外延区域。
本发明的第三态样包括一种集成电路(IC)结构，其具有：衬底；多个鳍片结构，在该衬底上方并直接接触该衬底；多个栅极结构，在该多个鳍片结构上方，其中，该多个栅极结构中的二个相邻的栅极结构通过第一间距分开，且其中，该多个栅极结构中的二个不同的相邻的栅极结构通过第二间距分开，该第二间距大于该第一间距；多个外延区域，在该衬底与该多个鳍片结构上方及该多个栅极结构各者之间，该多个外延区域包括：第一外延区域，跨越该二个相邻的栅极结构之间的该第一间距；以及第二外延区域，跨越该二个不同的相邻的栅极结构之间的第二间距；以及接触，直接接触该第二外延区域。
附图说明
本发明的这些及其它特征，将从以下的本发明的各个态样的详细描述，结合描绘本发明的各种实施例的附图，可以更容易地理解，其中：
图1示出根据各种实施例的先导(precursor)结构的示意性剖面图。
图2(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图2(b)示出图2(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图2(c)示出图2(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图3(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图3(b)示出图3(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图3(c)示出图3(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图4(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图4(b)示出图4(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图4(c)示出图4(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图5(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图5(b)示出图5(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图5(c)示出图5(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图6(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图6(b)示出图6(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图6(c)示出图6(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图7(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图7(b)示出图7(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图7(c)示出图7(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图8(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图8(b)示出图8(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。
图8(c)示出图8(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图9(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图9(b)示出图9(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图10(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图10(b)示出图10(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图11(a)示出经历根据各种实施例的制程的结构的示意性顶视图。
图11(b)示出图11(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图12A示出根据各种实施例的集成电路(IC)结构的示意性剖面描绘。
图12B示出根据各种附加实施例的集成电路(IC)结构的示意性剖面描绘。
应注意的是，本发明的附图不一定按比例绘制。附图旨在仅描绘本发明的典型态样，因此不应该被认为是限制本发明的范围。在附图中，相同的编号表示附图之间的类似的组件。
具体实施方式
如上所述，本发明揭示的主题涉及集成电路(IC)装置。更具体地说，本发明涉及在集成电路装置中形成栅极结构。
相比于传统方法，本发明的各种实施例包括用于形成栅极结构的方法，通过形成虚设(dummy)栅极以扩大外延(或epi)区域，并在该区域中建立所欲的应力。该应力有助于在该栅极区域中提高接触电阻率及/或降低接触至栅极间短路。外延(或epi)层或区域，为生长于硅晶圆衬底的抛光表面上的薄的单晶硅层。该外延层来自下方的晶圆、具有不同的成分及电气性能，针对所制造的装置的具体要求而设计。如本发明所述，本发明的各种实施例包括形成IC装置的方法，以及通过该方法所形成的IC装置，其中，使用装置的栅极之间的扩大外延区域来提高效能。
在下面的描述中，参考部分的附图，其中，本发明的教导通过可实践的具体示例性实施例的方式示出。该些实施方案详细地描述以使本领域的技术人员能够实践本发明的教导，且可以理解的是，其他实施例可以被利用，并在不偏离本教导的范围的情况下可以作出改变。因此，以下的说明仅仅是说明性的。
如本发明中所描述的，“沉积”可以包括任何现在已知或以后开发的技术来沉积适合的材料，包括但不限于，例如：化学气相沉积(CVD)、低压CVD(LPCVD)、等离子体增强型CVD(PECVD)、半大气压CVD(SACVD)及高密度等离子体CVD(HDPCVD)、快速加热CVD(RTCVD)、超高真空CVD(UHVCVD)、限制反应制程CVD(LRPCVD)、金属有机CVD(MOCVD)、溅射沉积、离子束沉积、电子束沉积、激光辅助沉积、热氧化、热氮化、旋涂法、物理气相沉积(PVD)、原子层沉积(ALD)、化学氧化，分子束外延(MBE)、电镀、蒸镀。
图1-12B示出执行根据各种实施例的制程的集成电路结构(及先导结构)的示意性横剖面。可以理解的是，本发明所概述的制程与一些实施例中所描述的，可以依不同的顺序执行。此外，不是所有这里所概述的制程需要必然地根据各种实施例执行。
转到图1，示出在先导结构2执行根据各种实施例的制程的示意图。如图所示，该制程可以包括在衬底4上方形成一掺杂硅层6(例如，包括硅及/或二氧化硅)。如图所示，根据各种实施例，掺杂硅层6随后形成鳍片。在各种实施例中，掺杂硅层6可包括元素半导体材料(例如，硅、锗、碳、或其合金)、III-V族半导体材料、或II-VI族半导体材料。根据各种实施例，在衬底上方沉积掺杂硅层6作为块体硅(bulk silicon)，并且随后电离以掺杂该块体硅材料。在其他情况下，一部分的衬底4被离子化(例如，经受电离辐射)以在先前的衬底4的上部形成掺杂硅层6。图2(包括图2(a)、2(b)及2(c))示出随后的制程中，自掺杂硅层6中形成多个鳍片结构8的三个视图(顶视，穿过鳍片(xFin)的横剖面及通过栅极接触(xPC)的横剖面，该栅极接触还没有形成，并且随后垂直于鳍片形成)。图2(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图2(b)示出图2(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。图2(c)示出图2(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。在各种实施方案中，传统的掩模及蚀刻制程可自掺杂硅层6形成鳍片结构8，例如，包括在掺杂硅层6上形成硬掩模并使用该掩模刻蚀下层的掺杂硅层6以移除鳍片结构8之间部分的掺杂硅层。
图3(包括图3(a)、3(b)及3(c))示出根据实施例形成集成电路(IC)结构的中间制程。图3(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图3(b)示出图3(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。图3(c)示出图3(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。如图所示，图3示出的制程包括在鳍片结构8及下层的衬底4上方沉积介电质衬层9，并且在该介电质衬层9上方形成栅极层10。该介电质衬层9可包括二氧化硅、氮化二氧化硅、或是与高K材料的组合。栅极层10可以包括半导体材料(例如，多晶硅或无定形硅)、介电材料、或金属，取决于用于后续形成栅极的图案化方法。在各种实施例中，如果栅极结构是在源极区及漏极区之后形成的，则介电质衬层9及栅极层10是一次性的。可以采用传统的化学机械抛光(CMP)在介电质衬层9上方平坦化栅极层10。图4(包括图4(a)、4(b)及4(c))示出包括在栅极层10上方形成栅极硬掩模11(例如，通过本发明中所描述的传统沉积技术)的附加制程。图4(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图4(b)示出图4(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。图4(c)示出图4(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。栅极硬掩模11可以包括氮化硅、或氮化硅及二氧化硅的组合，或者是有助于形成栅极图案的任何介电层。图5(包括图5(a)、5(b)及5(c))示出的制程包括，在栅极硬掩模11上方形成图案化光刻胶层13，用传统的光刻技术，包括但不限于深紫外光(DUV)或极紫外光(EUV)的制程、侧壁影像转移制程、或多重图案化制程。图5(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图5(b)示出图5(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。图5(c)示出图5(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。图6(包括图6(a)、6(b)及6(c))示出光刻胶层13的图案使用传统的RIE(反应离子蚀刻)转移到硬掩模11，以形成图案化栅极硬掩模14。剩余的光刻胶层13可以通过传统方法，例如通过干式等离子体灰化或(选择性)湿式清洗(例如，使用含硫过氧化物(sulfuric peroxide))移除。图6(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图6(b)示出图6(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面图。图6(c)示出图6(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图7(包括图7(a)、7(b)及7(c))示出包括在栅极硬掩模14及下层的栅极层10上方形成光刻胶16图案化的附加制程，其可使用本发明所述任何传统的光刻技术来进行，例如，包括DUV、EUV、本发明所述的任何侧壁影像转移技术、或本发明中所描述及/或本领域已知的任何多重图案化技术。如本发明进一步所述，形成光刻胶16并图案化光刻胶16以露出栅极硬掩模14的一部分14a并于随后移除。图7(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图7(b)示出图7(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面图。图7(c)示出图7(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。
图8(包括图8(a)、8(b)及8(c))示出另一中间制程，包括使用光刻胶16作为掩模，以干式或湿式蚀刻移除虚设栅极硬掩模的一部分14a。图8(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图8(b)示出图8(a)的结构的示意性剖面图，具有通过鳍片结构的横剖面。图8(c)示出图8(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。光刻胶16可随后被选择性地蚀刻掉，例如，用干式等离子体灰化或湿式清洗，包括但不限于含硫过氧化物类的化学反应。
图9(包括图9(a)及9(b))示出包括图案化栅极层10以形成栅极结构20并露出鳍片结构8的附加制程。图9(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图9(b)示出图9(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。如图所示，栅极结构20包括栅极层10的一部分及栅极硬掩模14的上覆部分。栅极图案化可使用任何传统的图案化方法来执行，例如，用RIE制程，该制程对氮化物及/或氧化物具有选择性。如图所示，鳍片结构8垂直于栅极结构20(在顶视图中可见)。可以理解的是，当比对图9与图8以及前面的图时，图9示出说明一些额外的栅极结构20，目的是为了说明在图9-11中xFin视图的遗漏。
图10(包括图10(a)及10(b))示出的制程包括沉积间隙壁层21，在栅极层10上形成间隙壁21，并凹陷(recessing)在栅极结构20之间的鳍片8以形成凹部22。图10(a)表示经历根据各种实施例的制程的结构的示意性顶视图。图10(b)示出图10(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。间隙壁21可以包括，例如氮化硅、SiBCN、SiOCN、或者任何类型的低K(K<6)材料。可使用各向异性RIE制程来形成间隙壁21。在各种实施例中，该蚀刻制程可以包括使用对该多个鳍片结构8敏感的氮化硅(SiN)蚀刻。如图所示，部分的栅极结构20与其相邻的栅极结构20通过第一间距P1(栅极结构之间的中心到中心的距离，沿轴线垂直于衬底4的上表面)分开，而其它的栅极结构20与其相邻的栅极结构20通过第二间距P2分开，其中，第二间距大于第一间距(由于移除硬掩模14与相对应的栅极结构20)。在部分情况下，P2的值大约二倍于P1的值。
图11(包括图11(a)及11(b))示出的制程包括在栅极结构20之间的鳍片8上方形成(源极/漏极)外延区域24。图11(a)示出经历根据各种实施例的制程的结构的示意性顶视图。图11(b)示出图11(a)的结构的示意性剖面图，具有通过栅极接触结构的横剖面。在各种实施例中，在栅极结构20之间的鳍片8上方形成多个外延区域24，并且在部分情况下，在通过第一间距P1分开的栅极结构20之间形成多个外延区域24。如本发明所述，通过第二(较大的)间距P2分开的二个栅极结构20之间的外延区域24比通过第一(较小的)间距P1分开的栅极结构20之间的外延区域24具有更大的应力位准(内应力)。在各种实施方案中，形成的(源极/漏极)外延区域24的制程包括，选择性地形成(例如，沉积)n型或p型掺杂半导体层包括，IV族、III-V族、II-VI族化合物半导体材料中的至少一者。
图12A及12B示出的附加制程包括，形成于外延区域24上方并直接接触外延区域24的接触26。在一个实施例中(图12A)，形成一个传统基本标准的接触26A以接触外延区域24。图12B示出另一实施方式，其中，形成一个相对较宽的接触26B以接触外延区域24，其中，较宽的接触26B具有的宽度大约二倍于基本标准的接触26A的尺寸。相比于接触26B，接触26A可以具有相对较低的有效电容(Ceff)，而相比于接触26A，接触26B具有较低的有效电阻(Reff)。
图12A及12B分别示出集成电路(IC)结构1100及1110。集成电路结构1100及1110可各别包括：衬底4；衬底4上方的多个鳍片结构8；鳍片结构8及衬底4上方的多个栅极结构20，该多个栅极结构20直接接触鳍片结构8，其中，二个相邻的栅极结构20通过第一间距P1分开，而二个不同的相邻的栅极结构20通过第二间距P2分开，其中，第二间距P2大于第一间距P1。
集成电路结构1100及1110也可以包括多个外延区域24，其位于鳍片结构8及衬底4上方及多个栅极结构20各者之间。该多个外延区域24包括：第一外延区域24A横跨二个相邻的栅极结构20之间的第一间距P1；及第二外延区域24B横跨二个不同的相邻的栅极结构20之间的第二间距P2。集成电路结构1100可进一步包括接触26A，而集成电路结构1110还包括接触26B，其中，各接触26A，26B接触第二外延区域24B。
当组件或层被称为“在上”、“接合至”、“连接至”或“耦合至”另一组件或层时，它可以直接在上、接合、连接或耦合至另一组件或层，或是可以存在中间组件或层。相反，当一个组件被称为“直接在上”、“直接接合至”、“直接连接至”或“直接耦合至”另一组件或层时，可以没有中间组件或层。用于描述组件之间的关系的其他词语应该以类似的方式(例如，“之间”与“直接之间”，“相邻”与“直接相邻”等)进行解释。如本发明中所使用的，术语“及/或”包括一个或多个相关所列的项目的任意组合及所有组合。
使用空间相对术语，例如“内”、“外”、“之下”、“以下”、“下”、“上方”、“上”等，在本发明中可以用于描述，以易于描述一个组件或特征与如图中所示的另一组件或特征的关系。空间相对术语可以旨在除了在附图中描述的方位之外，也包括使用或操作装置的不同取向。例如，如果在附图中的装置被翻转，则被描述为“下方”或“之下”其它组件或特征随后将被“上方”其它组件或特征取向。因此，示例术语“下方”可以包括上方及下方的方位。所述装置可被另外定位(旋转90度或者在其它方位)，并对在这里使用的空间相对描述相应地进行解释。
本发明所用的术语仅用于描述具体实施方案的目的，并不意在限制本发明。如本发明中所使用的，单数形式“一”、“一个”及“该”也意图包括复数形式，除非上下文另外明确指出。将进一步理解，术语“包括”及/或“包含”的存在，并在本说明书中使用时指定所陈述的特征、整数、步骤、操作、组件及/或部件，但不排除存在或附加一个或多个其它特征、整数、步骤、操作、组件、部件及/或它们的组合。还应当理解的是，术语“前”及“后”不旨在是限制性的，并且旨在当合适时为可互换的。
本发明使用实例描述来揭示本发明，包括最佳模式，并且还使任何本领域技术人员能够实践本发明，包括制造及使用任何装置或系统，以及执行任何结合的方法。本发明的专利范围由权利要求限定，并且可包括本领域技术人员想到的其他实施例。如果它们不具有与权利要求的文字语言不同的结构组件，或者如果它们包括与权利要求的字面语言无实质区别的等同结构组件，该些其他实例旨在处于权利要求的范围内。
本发明的各种实施例的描述出于说明的目的，但并非意在穷举或限制于所揭示的实施例。许多修改及变化将不脱离所描述实施例的范围及精神，对于本领域的普通技术人员是显而易见。本发明所选择的术语可最好地用于解释实施例的原理、在业界发现的实际应用或技术改进过的技术，或使本领域的其他的普通技术人员能够理解在此揭示的实施例。

Claims (20)

1.一种形成集成电路结构的方法，该方法包括：
在衬底上方形成一掺杂硅层；
自该掺杂硅层形成多个鳍片结构；
在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；
在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；
移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；以及
在该二个剩余的栅极结构之间的该多个鳍片结构与该衬底上方形成外延区域。
2.如权利要求1所述的方法，还包括形成多个外延区域在通过该第一间距分开的该多个栅极结构之间的该多个鳍片结构与该衬底上方。
3.如权利要求2所述的方法，其中，位于该二个剩余的栅极结构之间的该外延区域比通过该第一间距分开的该多个栅极结构之间的该外延区域具有较大的应力位准。
4.如权利要求1所述的方法，还包括在该外延区域上方形成第一接触以直接接触该外延区域。
5.如权利要求4所述的方法，其中，该第一接触具有第一宽度。
6.如权利要求5所述的方法，还包括在该外延区域上方形成第二接触以直接接触该外延区域，该第二接触具有第二宽度，该第二宽度大致为该第一宽度的二倍。
7.如权利要求1所述的方法，其中，该形成该外延区域包括在该二个剩余的栅极结构之间选择性沉积n型掺杂或p型掺杂半导体层。
8.如权利要求1所述的方法，还包括在形成该外延区域之前，先蚀刻以在该衬底中形成间隙壁凹部，其中，该蚀刻包括使用对该多个鳍片结构敏感的氮化硅(SiN)蚀刻。
9.如权利要求1所述的方法，其中，该移除该多个栅极结构中的该至少一者，包括使用蚀刻制程选择氮化物或氧化物中的至少一者，选择性蚀刻该多个栅极结构中的该至少一者。
10.如权利要求1所述的方法，其中，该形成该多个栅极结构包括：
在该多个鳍片结构上方形成栅极层；
在该栅极层上方形成硬掩模；
蚀刻该硬掩模以移除该硬掩模的一部分，形成修改过的硬掩模；以及
使用该修改过的硬掩模蚀刻该栅极层。
11.一种形成集成电路结构的方法，该方法包括：
在衬底上方形成一掺杂硅层；
自该掺杂硅层形成多个鳍片结构；
在该多个鳍片结构上方形成多个栅极结构，该多个栅极结构各者与相邻的栅极结构通过第一间距分开；
在该多个栅极结构上方形成掩模，露出该多个栅极结构中的至少一者；
移除该多个栅极结构中的该至少一者，其中，在该移除之后，二个剩余的栅极结构通过大于该第一间距的第二间距分开；
在该二个剩余的栅极结构之间的该衬底上方形成第一外延区域；
在通过该第一间距分开的该多个栅极结构之间的该衬底上方形成多个外延区域；以及
在该第一外延区域上方形成接触以直接接触该第一外延区域。
12.如权利要求11所述的方法，其中，该第一外延区域比通过该第一间距分开的该多个栅极结构之间的该多个外延区域具有较大的应力位准。
13.如权利要求11所述的方法，其中，该接触具有第一宽度。
14.如权利要求13所述的方法，还包括在该第一外延区域上方形成第二接触以直接接触该第一外延区域，其中，该第二接触具有第二宽度，该第二宽度大致为该第一宽度的二倍。
15.如权利要求11所述的方法，其中，形成该外延区域包括：
在该二个剩余的栅极结构之间选择性地沉积n型掺杂或p型掺杂半导体层。
16.如权利要求11所述的方法，还包括在形成该外延区域之前，先蚀刻以在该衬底中形成间隙壁凹部，其中，该蚀刻包括使用对该多个鳍片结构敏感的氮化硅(SiN)蚀刻。
17.如权利要求11所述的方法，其中，该移除该多个栅极结构中的该至少一者，包括使用蚀刻制程选择氮化物或氧化物中的至少一者，选择性蚀刻该多个栅极结构中的该至少一者。
18.如权利要求11所述的方法，其中，该形成该多个栅极结构包括：
在该多个鳍片结构上方形成栅极层；
在该栅极层上方形成硬掩模；
蚀刻该硬掩模以移除该硬掩模的一部分，形成修改过的硬掩模；以及
使用该修改过的硬掩模蚀刻该栅极层。
19.一种集成电路结构，包括：
衬底；
多个鳍片结构，在该衬底上方并直接接触该衬底；
多个栅极结构，在该多个鳍片结构上方，其中，该多个栅极结构中的二个相邻的栅极结构通过第一间距分开，且其中，该多个栅极结构中的二个不同的相邻的栅极结构通过第二间距分开，该第二间距大于该第一间距；
多个外延区域，在该衬底与该多个鳍片结构上方及该多个栅极结构各者之间，该多个外延区域包括：
第一外延区域，跨越该二个相邻的栅极结构之间的该第一间距；以及
第二外延区域，跨越该二个不同的相邻的栅极结构之间的该第二间距；以及
接触，直接接触该第二外延区域。
20.如权利要求19所述的集成电路结构，其中，该第二外延区域具有比该第一外延区域较高的应力位准，因该第二间距大于该第一间距。
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