TWI641029B - 在通過不同間距分開的閘極之間形成具有應力的磊晶層 - Google Patents
在通過不同間距分開的閘極之間形成具有應力的磊晶層 Download PDFInfo
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Abstract
各種實施例包括方法以及積體電路結構。在一些情況下,形成積體電路結構的方法可包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片結構;在該多個鰭片結構上方形成多個閘極結構,該多個閘極結構各者與相鄰的閘極結構通過第一間距分開;在該多個閘極結構上方形成遮罩,露出該多個閘極結構中的至少一者;移除該多個閘極結構中的該至少一者,其中,在該移除之後,二個剩餘的閘極結構通過大於該第一間距的第二間距分開;以及在該二個剩餘的閘極結構之間的該基板上方形成磊晶區域。
Description
本發明揭示的主題關於積體電路裝置。更具體地說,本發明關於在積體電路裝置中形成閘極結構。
隨著積體電路(IC)技術的進步,該些裝置的尺寸也相應減小。特別是,縮小裝置的尺寸以符合越來越小的封裝,將對它們的尺寸及間隔施加更緊密的限制。
在IC裝置中具有應力(stress)的閘極區是一種有效的機構,用於提高流經該些閘極區的信號的效能(例如,速度)。然而,隨著裝置尺寸減小,相鄰的積體電路閘極之間的距離(間距,pitch)被減小。該減小的閘極間距使得形成IC時更難以有效地向閘極區施加應力,對效能產生不利的影響。此外,減小的閘極間距可導致接觸電阻降低、接觸(contact)至閘極間短路,以及其它不希望的情況。
各種實施例包括方法以及積體電路結構。在一些情況下,一種形成積體電路結構的方法可包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片(fin)
結構;在該多個鰭片結構上方形成多個閘極結構,該多個閘極結構各者與相鄰的閘極結構通過第一間距分開;在該多個閘極結構上方形成遮罩,露出該多個閘極結構中的至少一者;移除該多個閘極結構中的該至少一者,其中,在該移除之後,二個剩餘的閘極結構通過大於該第一間距的第二間距分開;以及在該二個剩餘的閘極結構之間的該基板上方形成磊晶區域。
本發明的第一態樣包括一種形成積體電路結構的方法,該方法包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片結構;在該多個鰭片結構上方形成多個閘極結構,該多個閘極結構各者與相鄰的閘極結構通過第一間距分開;在該多個閘極結構上方形成遮罩,露出該多個閘極結構中的至少一者;移除該多個閘極結構中的該至少一者,其中,在該移除之後,二個剩餘的閘極結構通過大於該第一間距的第二間距分開;以及在該二個剩餘的閘極結構之間的該基板上方形成磊晶區域。
本發明的第二態樣包括一種形成積體電路結構的方法,該方法包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片結構;在該多個鰭片結構上方形成多個閘極結構,該多個閘極結構各者與相鄰的閘極結構通過第一間距分開;在該多個閘極結構上方形成遮罩,露出該多個閘極結構中的至少一者;移除該多個閘極結構中的該至少一者,其中,在該移除之後,二個剩餘的閘極結構通過大於該第一間距的第二間距分開;在該二個剩餘的
閘極結構之間的該基板上方形成第一磊晶區域;在通過該第一間距分開的該多個閘極結構之間的該基板上方形成多個磊晶區域;以及在該第一磊晶區域上方形成接觸以直接接觸該第一磊晶區域。
本發明的第三態樣包括一種積體電路(IC)結構,其具有:基板;多個鰭片結構,在該基板上方並直接接觸該基板;多個閘極結構,在該多個鰭片結構上方,其中,該多個閘極結構中的二個相鄰的閘極結構通過第一間距分開,且其中,該多個閘極結構中的二個不同的相鄰的閘極結構通過第二間距分開,該第二間距大於該第一間距;多個磊晶區域,在該基板與該多個鰭片結構上方及該多個閘極結構各者之間,該多個磊晶區域包括:第一磊晶區域,跨越該二個相鄰的閘極結構之間的該第一間距;以及第二磊晶區域,跨越該二個不同的相鄰的閘極結構之間的第二間距;以及接觸,直接接觸該第二磊晶區域。
2‧‧‧先導結構
4‧‧‧基板
6‧‧‧摻雜矽層
8‧‧‧鰭片、鰭片結構
9‧‧‧介電質襯層
10‧‧‧閘極層
11‧‧‧閘極硬遮罩
13‧‧‧光刻膠層
14‧‧‧閘極硬遮罩
14a‧‧‧閘極硬遮罩的一部分
16‧‧‧光刻膠
20‧‧‧閘極結構
21‧‧‧間隙壁、間隙壁層
22‧‧‧凹部
24‧‧‧磊晶區域
26A‧‧‧接觸
26B‧‧‧接觸
1100‧‧‧積體電路結構
1110‧‧‧積體電路結構
P1‧‧‧第一間距
P2‧‧‧第二間距
本發明的這些及其它特徵,將從以下的本發明的各個態樣的詳細描述,結合描繪本發明的各種實施例的附圖,可以更容易地理解,其中:第1圖示出根據各種實施例的先導(precursor)結構的示意性剖面圖。
第2(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第2(b)圖示出第2(a)圖的結構的示意性剖面
圖,具有通過鰭片結構的橫剖面。
第2(c)圖示出第2(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第3(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第3(b)圖示出第3(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。
第3(c)圖示出第3(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第4(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第4(b)圖示出第4(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。
第4(c)圖示出第4(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第5(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第5(b)圖示出第5(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。
第5(c)圖示出第5(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第6(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第6(b)圖示出第6(a)圖的結構的示意性剖面
圖,具有通過鰭片結構的橫剖面。
第6(c)圖示出第6(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第7(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第7(b)圖示出第7(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。
第7(c)圖示出第7(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第8(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第8(b)圖示出第8(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。
第8(c)圖示出第8(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第9(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第9(b)圖示出第9(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第10(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第10(b)圖示出第10(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第11(a)圖示出經歷根據各種實施例的製程
的結構的示意性頂視圖。
第11(b)圖示出第11(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第12A圖示出根據各種實施例的積體電路(IC)結構的示意性剖面描繪。
第12B圖示出根據各種附加實施例的積體電路(IC)結構的示意性剖面描繪。
應注意的是,本發明的附圖不一定按比例繪製。附圖旨在僅描繪本發明的典型態樣,因此不應該被認為是限制本發明的範圍。在附圖中,雷同的編號表示附圖之間的類似的組件。
如上所述,本發明揭示的主題關於積體電路(IC)裝置。更具體地說,本發明關於在積體電路裝置中形成閘極結構。
相比于傳統方法,本發明的各種實施例包括用於形成閘極結構的方法,通過形成虛設(dummy)閘極以擴大磊晶(或epi)區域,並在該區域中建立所欲的應力。該應力有助於在該閘極區域中提高接觸電阻率及/或降低接觸至閘極間短路。磊晶(或epi)層或區域,為生長於矽晶圓基板的拋光表面上的薄的單晶矽層。該磊晶層係經設計以具有與下方的晶圓不同的成分及電氣性能,而針對所製造的裝置的具體要求而訂製。如本發明所述,本發明的各種實施例包括形成IC裝置的方法,以及通過該方法所形
成的IC裝置,其使用裝置的閘極之間的擴大磊晶區域來提高效能。
在下面的描述中,參考部分的附圖,其中,本發明的教導通過可實踐的具體示例性實施例的方式示出。該些實施例詳細地描述以使本領域的技術人員能夠實踐本發明的教導,且可以理解的是,其他實施例可以被利用,並在不偏離本教導的範圍的情況下可以作出改變。因此,以下的說明僅僅是說明性的。
如本發明中所描述的,“沉積”可以包括任何現在已知或以後開發的技術而適用於將被沉積的材料,包括但不限於,例如:化學氣相沉積(CVD)、低壓CVD(LPCVD)、等離子體增強型CVD(PECVD)、半大氣壓CVD(SACVD)及高密度等離子體CVD(HDPCVD)、快速加熱CVD(RTCVD)、超高真空CVD(UHVCVD)、限制反應製程CVD(LRPCVD)、金屬有機CVD(MOCVD)、濺射沉積、離子束沉積、電子束沉積、激光輔助沉積、熱氧化、熱氮化、旋塗法、物理氣相沉積(PVD)、原子層沉積(ALD)、化學氧化,分子束磊晶(MBE)、電鍍、蒸鍍。
第1-12B圖示出說明根據各種實施例的製程的積體電路結構(及先導結構)的示意性橫剖面。可以理解的是,本發明所概述的製程與一些實施例中所描述的,可以依不同的順序執行。此外,不是所有這裡所概述的製程需要必然地根據各種實施例執行。
回到第1圖,示出在先導結構2執行根據各
種實施例的製程的示意圖。如圖所示,該製程可以包括在基板4上方形成一摻雜矽層6(例如,包括矽及/或二氧化矽)。如圖所示,根據各種實施例,摻雜矽層6是用於在隨後形成鰭片。在各種實施例中,摻雜矽層6可包括元素半導體材料(例如,矽、鍺、碳、或其合金)、III-V族半導體材料、或II-VI族半導體材料。根據各種實施例,在基板上方沉積摻雜矽層6作為塊體矽(bulk silicon),並且隨後電離以摻雜該塊體矽材料。在其他情況下,一部分的基板4被電離(例如,經受電離輻射)以在先前為基板4者的上部形成摻雜矽層6。第2圖(包括第2(a)、2(b)及2(c)圖)示出隨後的製程中,自摻雜矽層6中形成多個鰭片結構8的三個視圖(頂視,穿過鰭片(xFin)的橫剖面及通過閘極接觸(xPC)的橫剖面,該閘極接觸還沒有形成,並且隨後垂直于鰭片形成)。第2(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第2(b)圖示出第2(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。第2(c)圖示出第2(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。在各種實施例中,可使用傳統的遮罩及蝕刻製程而自摻雜矽層6形成鰭片結構8,例如,包括在摻雜矽層6上形成硬遮罩並使用該遮罩刻蝕下層的摻雜矽層6以移除鰭片結構8之間部分的摻雜矽層。
第3圖(包括第3(a)、3(b)及3(c)圖)示出根據實施例形成積體電路(IC)結構的中間製程。第3(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。
第3(b)圖示出第3(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。第3(c)圖示出第3(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。如圖所示,第3圖示出的製程包括在鰭片結構8及下層的基板4上方沉積介電質襯層9,並且在該介電質襯層9上方形成閘極層10。該介電質襯層9可包括二氧化矽、氮化二氧化矽、或是與高K材料的組合。閘極層10可以包括半導體材料(例如,多晶矽或無定形矽)、介電材料、或金屬,取決於用於後續形成閘極的圖案化方法。在各種實施例中,如果閘極結構是在源極區及漏極區之後形成的,則介電質襯層9及閘極層10是一次性的。可以採用傳統的化學機械拋光(CMP)在介電質襯層9上方平坦化閘極層10。第4圖(包括第4(a)、4(b)及4(c)圖)示出包括在閘極層10上方形成閘極硬遮罩11(例如,通過本發明中所描述的傳統沉積技術)的附加製程。第4(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第4(b)圖示出第4(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。第4(c)圖示出第4(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。閘極硬遮罩11可以包括氮化矽、或氮化矽及二氧化矽的組合,或者是有助於形成閘極圖案的任何介電層。第5圖(包括第5(a)、5(b)及5(c)圖)示出的製程包括,在閘極硬遮罩11上方形成圖案化光刻膠層13,用傳統的光刻技術(包括但不限於深紫外光(DUV)或極紫外光(EUV)的製程、側壁影像轉移製程、或多重圖案化製程)。
第5(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第5(b)圖示出第5(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。第5(c)圖示出第5(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。第6圖(包括第6(a)、6(b)及6(c)圖)示出光刻膠層13的圖案使用傳統的RIE(反應離子等離子體蝕刻)轉移到硬遮罩11,以形成圖案化閘極硬遮罩14。剩餘的光刻膠層13可以通過傳統方法,例如通過乾式等離子體灰化或(選擇性)濕式清洗(例如,使用含硫過氧化物(sulfuric peroxide))移除。第6(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第6(b)圖示出第6(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面圖。第6(c)圖示出第6(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第7圖(包括第7(a)、7(b)及7(c)圖)示出包括在閘極硬遮罩14及下層的閘極層10上方形成光刻膠16圖案化的附加製程,其可使用本發明所述任何傳統的光刻技術來進行,例如,包括DUV、EUV、本發明所述的任何側壁影像轉移技術、或本發明中所描述及/或本領域已知的任何多重圖案化技術。如本發明進一步所述,形成光刻膠16並圖案化光刻膠16以露出閘極硬遮罩14的一部分14a以於隨後移除。第7(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第7(b)圖示出第7(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面圖。第7(c)圖
示出第7(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。
第8圖(包括第8(a)、8(b)及8(c)圖)示出另一中間製程,包括使用光刻膠16作為遮罩,以乾式或濕式蝕刻移除虛設閘極硬遮罩的一部分14a。第8(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第8(b)圖示出第8(a)圖的結構的示意性剖面圖,具有通過鰭片結構的橫剖面。第8(c)圖示出第8(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。光刻膠16可隨後被選擇性地蝕刻掉,例如,用乾式等離子體灰化或濕式清洗,包括但不限於含硫過氧化物類的化學反應。
第9圖(包括第9(a)及9(b)圖)示出包括圖案化閘極層10以形成閘極結構20並露出鰭片結構8的附加製程。第9(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第9(b)圖示出第9(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。如圖所示,閘極結構20包括閘極層10的一部分及閘極硬遮罩14的上覆部分。閘極圖案化可使用任何傳統的圖案化方法來執行,例如,用RIE製程,該製程對氮化物及/或氧化物具有選擇性。如圖所示,鰭片結構8垂直於閘極結構20(在頂視圖中可見)。可以理解的是,當比對第9圖與第8圖以及前面的圖時,第9圖示出說明一些額外的閘極結構20,目的是為了說明在第9-11圖中xFin視圖的遺漏的部分。
第10圖(包括第10(a)及10(b)圖)示出的製
程包括沉積間隙壁層21,在閘極層10上形成間隙壁21,並凹陷(recessing)在閘極結構20之間的鰭片8以形成凹部22。第10(a)圖表示經歷根據各種實施例的製程的結構的示意性頂視圖。第10(b)圖示出第10(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。間隙壁21可以包括,例如氮化矽、SiBCN、SiOCN、或者任何類型的低K(K<6)材料。可使用各向異性RIE製程來形成間隙壁21。在各種實施例中,該蝕刻製程可以包括使用對該多個鰭片結構8敏感的氮化矽(SiN)蝕刻。如圖所示,部分的閘極結構20與其相鄰的閘極結構20通過第一間距P1(閘極結構之間的中心到中心的距離,沿軸線垂直於基板4的上表面)分開,而其它的閘極結構20與其相鄰的閘極結構20通過第二間距P2分開,其中,第二間距大於第一間距(由於硬遮罩14的移除與閘極結構20相對應)。在部分情況下,P2的值大約二倍於P1的值。
第11圖(包括第11(a)及11(b)圖)示出的製程包括在閘極結構20之間的鰭片8上方形成(源極/漏極)磊晶區域24。第11(a)圖示出經歷根據各種實施例的製程的結構的示意性頂視圖。第11(b)圖示出第11(a)圖的結構的示意性剖面圖,具有通過閘極接觸結構的橫剖面。在各種實施例中,在閘極結構20之間的鰭片8上方形成多個磊晶區域24,並且在部分情況下,在通過第一間距P1分開的閘極結構20之間形成多個磊晶區域24。如本發明所述,通過第二(較大的)間距P2分開的二個閘極結構20之間
的磊晶區域24比通過第二(較小的)間距P1分開的閘極結構20之間的磊晶區域24具有更大的應力位準(stress level)(內應力)。在各種實施例中,形成的(源極/漏極)磊晶區域24的製程包括,選擇性地形成(例如,沉積)n型或p型摻雜半導體層,該n型或p型摻雜半導體層包括,IV族、III-V族、II-VI族化合物半導體材料中的至少一者。
第12A及12B圖示出的附加製程包括,形成於磊晶區域24上方並直接接觸磊晶區域24的接觸26。在一個實施例中(第12A圖),形成一個傳統基本標準的接觸26A以接觸磊晶區域24。第12B圖示出另一實施方式,其中,形成一個相對較寬的接觸26B以接觸磊晶區域24,其中,較寬的接觸26B具有的寬度大約二倍於基本標準的接觸26A的尺寸。相比於接觸26B,接觸26A可以具有相對較低的有效電容(Ceff),而相比於接觸26A,接觸26B具有較低的有效電阻(Reff)。
第12A及12B圖分別示出積體電路(IC)結構1100及1110。積體電路結構1100及1110可各別包括:基板4;基板4上方的多個鰭片結構8;鰭片結構8及基板4上方的多個閘極結構20,該多個閘極結構20直接接觸鰭片結構8,其中,二個相鄰的閘極結構20通過第一間距P1分開,而二個不同的相鄰的閘極結構20通過第二間距P2分開,其中,第二間距P2大於第一間距P1。
積體電路結構1100及1110也可以包括多個磊晶區域24,其位於鰭片結構8及基板4上方及多個閘極
結構20各者之間。該多個磊晶區域24包括:第一磊晶區域24A橫跨二個相鄰的閘極結構20之間的第一間距P1;及第二磊晶區域24B橫跨二個不同的相鄰的閘極結構20之間的第二間距P2。積體電路結構1100可進一步包括接觸26A,而積體電路結構1110還包括接觸26B,其中,各接觸26A,26B接觸第二磊晶區域24B。
當組件或層被稱為“在上”、“接合至”、“連接至”或“耦合至”另一組件或層時,它可以直接在上、接合、連接或耦合至另一組件或層,或是可以存在中間組件或層。相反,當一個組件被稱為“直接在上”、“直接接合至”、“直接連接至”或“直接耦合至”另一組件或層時,可以沒有中間組件或層。用於描述組件之間的關係的其他詞語應該以類似的方式(例如,“之間”與“直接之間”,“相鄰”與“直接相鄰”等)進行解釋。如本發明中所使用的,術語“及/或”包括一個或多個相關所列的項目的任意組合及所有組合。
使用空間相對術語,例如“內”、“外”、“之下”、“以下”、“下”、“上方”、“上”等,在本發明中可以用於描述,以易於描述一個組件或特徵與如圖中所示的另一組件或特徵的關係。空間相對術語可以旨在除了在附圖中描述的方位之外,也包括使用或操作裝置的不同方位。例如,如果在附圖中的裝置被翻轉,則被描述為在其它組件或特徵“下方”或“之下”隨後將被定向為其它組件或特徵“上方”。因此,示例術語“下方”可
以包括上方及下方的方位。所述裝置可被另外定位(旋轉90度或者在其它方位),並對在這裡使用的空間相對描述相應地進行解釋。
本發明所用的術語僅用於描述具體實施例的目的,並不意在限制本發明。如本發明中所使用的,單數形式“一”、“一個”及“該”也意圖包括複數形式,除非上下文另外明確指出。將進一步理解,當在本說明書中使用術語“包括”及/或“包含”時,這些術語表明所陳述的特徵、整數、步驟、操作、組件及/或部件的存在,但並未排除一個或多個其它特徵、整數、步驟、操作、組件、部件及/或它們的組合的存在或附加。還應當理解的是,術語“前”及“後”並非意在限制,且旨在當合適時為可互換的。
本發明使用實例描述來揭示本發明,包括最佳模式,並且還使任何本領域技術人員能夠實踐本發明,包括製造及使用任何裝置或系統,以及執行任何合合併的方法。本發明的專利範圍由申請專利範圍限定,並且可包括本領域技術人員想到的其他示例。如果它們不具有與申請專利範圍的文字語言不同的結構組件,或者如果它們包括與申請專利範圍的字面語言無實質區別的等同結構組件,該些其他示例旨在落於申請專利範圍的範圍內。
本發明的各種實施例的描述出於說明的目的,但並非意在窮舉或限制於所揭示的實施例。許多修改及變化對於本領域的普通技術人員將是顯而易見的,且不
背離所描述實施例的範圍及精神。本發明所使用的術語是經揀選而可最好地解釋實施例的原理、實際應用、或在業界發現的技術的技術改良,或使本領域的其他的普通技術人員能夠理解在此揭示的實施例。
Claims (16)
- 一種形成積體電路結構的方法,該方法包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片結構;在該多個鰭片結構上方形成閘極層;在該閘極層上方形成硬遮罩;蝕刻該硬遮罩以移除該硬遮罩的一部分,形成外露該閘極層的一部分的修改過的硬遮罩;使用該修改過的硬遮罩蝕刻該閘極層,以移除該閘極層的外露的該部分並形成多個閘極結構,其中,在移除該閘極層的外露的該部分後,該多個閘極結構中的至少一者通過第一間距自第一相鄰閘極結構分開,且該多個閘極結構中的該至少一者通過大於該第一間距的第二間距自第二相鄰閘極結構分開:以及在通過該第二間距分開的該多個閘極結構中的該至少一者及該第二相鄰閘極結構之間的該多個鰭片結構與該基板上方形成磊晶區域。
- 如申請專利範圍第1項所述的方法,還包括形成額外磊晶區域在通過該第一間距分開的該多個閘極結構中的該至少一者及該第一相鄰閘極結構之間的該多個鰭片結構與該基板上方。
- 如申請專利範圍第2項所述的方法,其中,位於該多個閘極結構中的該至少一者及該第二相鄰閘極結構之間的該磊晶區域比通過該第一間距分開的該多個閘極結構中的該至少一者及該第一相鄰閘極結構之間的該額外磊晶區域具有較大的應力位準。
- 如申請專利範圍第1項所述的方法,還包括在該磊晶區域上方形成第一接觸以直接接觸該磊晶區域。
- 如申請專利範圍第4項所述的方法,其中,該第一接觸具有第一寬度。
- 如申請專利範圍第1項所述的方法,其中,該形成該磊晶區域包括在該多個閘極結構中的該至少一者及該第二相鄰閘極結構之間選擇性沉積n型摻雜或p型摻雜半導體層。
- 如申請專利範圍第1項所述的方法,還包括在形成該磊晶區域之前,先蝕刻以在該基板中形成間隙壁凹部,其中,該蝕刻包括使用對該多個鰭片結構敏感的氮化矽(SiN)蝕刻。
- 如申請專利範圍第1項所述的方法,其中,該移除該閘極層的外露的該部分,包括使用對氮化物或氧化物中的至少一者為選擇性的蝕刻製程,選擇性蝕刻該閘極層的該部分。
- 一種形成積體電路結構的方法,該方法包括:在基板上方形成一摻雜矽層;自該摻雜矽層形成多個鰭片結構;在該多個鰭片結構上方形成閘極層;在該閘極層上方形成硬遮罩;蝕刻該硬遮罩以移除該硬遮罩的一部分,形成外露該閘極層的一部分的修改過的硬遮罩;使用該修改過的硬遮罩蝕刻該閘極層,以移除該閘極層的外露的該部分並形成多個閘極結構,其中,在移除該閘極層的外露的該部分後,該多個閘極結構中的至少一者通過第一間距自第一相鄰閘極結構分開,且該多個閘極結構中的該至少一者通過大於該第一間距的第二間距自第二相鄰閘極結構分開:在通過該第二間距分開的該多個閘極結構中的該至少一者及該第二相鄰閘極結構之間的該基板上方形成第一磊晶區域;在通過該第一間距分開的該多個閘極結構中的該至少一者及該第一相鄰閘極結構之間的該基板上方形成額外磊晶區域;以及在該第一磊晶區域上方形成接觸以直接接觸該第一磊晶區域。
- 如申請專利範圍第9項所述的方法,其中,該第一磊晶區域比該額外磊晶區域具有較大的應力位準。
- 如申請專利範圍第9項所述的方法,其中,該接觸具有第一寬度。
- 如申請專利範圍第9項所述的方法,其中,形成該額外磊晶區域包括:在該多個閘極結構中的該至少一者及該第一相鄰閘極結構之間選擇性地沉積n型摻雜或p型摻雜半導體層。
- 如申請專利範圍第9項所述的方法,還包括在形成該磊晶區域之前,先蝕刻以在該基板中形成間隙壁凹部,其中,該蝕刻包括使用對該多個鰭片結構敏感的氮化矽(SiN)蝕刻。
- 如申請專利範圍第9項所述的方法,其中,該移除該閘極層的外露的該部分,包括使用對氮化物或氧化物中的至少一者為選擇性的蝕刻製程,選擇性蝕刻該閘極層的該部分。
- 一種積體電路結構,包括:基板;多個鰭片結構,在該基板上方並直接接觸該基板;多個閘極結構,在該多個鰭片結構上方,其中,該多個閘極結構中的二個相鄰的閘極結構通過第一間距分開,且其中,該多個閘極結構中的二個不同的相鄰的閘極結構通過第二間距分開,該第二間距大於該第一間距;多個磊晶區域,在該基板與該多個鰭片結構上方及該多個閘極結構各者之間,該多個磊晶區域包括:第一磊晶區域,跨越該二個相鄰的閘極結構之間的該第一間距;以及第二磊晶區域,跨越該二個不同的相鄰的閘極結構之間的該第二間距;以及接觸,直接接觸該第二磊晶區域。
- 如申請專利範圍第15項所述的積體電路結構,其中,因該第二間距大於該第一間距,該第二磊晶區域具有比該第一磊晶區域較高的應力位準。
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US20140027820A1 (en) * | 2012-07-24 | 2014-01-30 | International Business Machines Corporation | Forming facet-less epitaxy with self-aligned isolation |
TW201421695A (zh) * | 2012-11-30 | 2014-06-01 | Samsung Electronics Co Ltd | 在主動鰭之間包括突出絕緣部分的半導體裝置 |
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US9818873B2 (en) | 2017-11-14 |
CN107039347B (zh) | 2020-10-23 |
CN107039347A (zh) | 2017-08-11 |
US20170104100A1 (en) | 2017-04-13 |
TW201715587A (zh) | 2017-05-01 |
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