CN102999455B - 存储器仲裁电路 - Google Patents

存储器仲裁电路 Download PDF

Info

Publication number
CN102999455B
CN102999455B CN201210331469.4A CN201210331469A CN102999455B CN 102999455 B CN102999455 B CN 102999455B CN 201210331469 A CN201210331469 A CN 201210331469A CN 102999455 B CN102999455 B CN 102999455B
Authority
CN
China
Prior art keywords
request
memory
generator
port
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201210331469.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN102999455A (zh
Inventor
R·R-H·胡
俞海明
H-Y·H·周
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Altera Corp
Original Assignee
Altera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corp filed Critical Altera Corp
Publication of CN102999455A publication Critical patent/CN102999455A/zh
Application granted granted Critical
Publication of CN102999455B publication Critical patent/CN102999455B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM

Landscapes

  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Static Random-Access Memory (AREA)
  • Memory System (AREA)
CN201210331469.4A 2011-09-16 2012-09-07 存储器仲裁电路 Active CN102999455B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/234,925 US8867303B2 (en) 2011-09-16 2011-09-16 Memory arbitration circuitry
US13/234,925 2011-09-16

Publications (2)

Publication Number Publication Date
CN102999455A CN102999455A (zh) 2013-03-27
CN102999455B true CN102999455B (zh) 2017-10-27

Family

ID=46799126

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201210331469.4A Active CN102999455B (zh) 2011-09-16 2012-09-07 存储器仲裁电路

Country Status (4)

Country Link
US (1) US8867303B2 (enExample)
EP (1) EP2571027A1 (enExample)
JP (1) JP6317876B2 (enExample)
CN (1) CN102999455B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9876501B2 (en) * 2013-05-21 2018-01-23 Mediatek Inc. Switching power amplifier and method for controlling the switching power amplifier
US9183947B1 (en) * 2014-04-16 2015-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Detecting write disturb in multi-port memories
CN107315703B (zh) * 2017-05-17 2020-08-25 天津大学 双优先级控制型公平仲裁器
US10622043B2 (en) 2017-09-11 2020-04-14 Qualcomm Incorporated Multi-pump memory system access circuits for sequentially executing parallel memory operations
US10652912B2 (en) * 2018-04-30 2020-05-12 Microchip Technology Incorporated Smart radio arbiter with conflict resolution based on timing predictability
US11031075B2 (en) * 2019-05-08 2021-06-08 Qualcomm Incorporated High bandwidth register file circuit with high port counts for reduced bitline delay
CN112749021B (zh) * 2019-10-29 2024-10-22 瑞昱半导体股份有限公司 通信系统以及运作方法
US11264078B2 (en) * 2020-02-04 2022-03-01 Micron Technology, Inc. Metastable resistant latch
US12056375B2 (en) 2022-09-06 2024-08-06 Micron Technology, Inc. Port arbitration
US12079144B1 (en) 2022-09-21 2024-09-03 Apple Inc. Arbitration sub-queues for a memory circuit

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398211A (en) * 1993-10-14 1995-03-14 Integrated Device Technology, Inc. Structure and method for providing prioritized arbitration in a dual port memory
US5781480A (en) * 1997-07-29 1998-07-14 Motorola, Inc. Pipelined dual port integrated circuit memory
US6078527A (en) * 1997-07-29 2000-06-20 Motorola, Inc. Pipelined dual port integrated circuit memory
CN1643502A (zh) * 2002-03-18 2005-07-20 松下电器产业株式会社 信息处理装置

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4796232A (en) 1987-10-20 1989-01-03 Contel Corporation Dual port memory controller
US4937781A (en) 1988-05-13 1990-06-26 Dallas Semiconductor Corporation Dual port ram with arbitration status register
US5047921A (en) 1989-01-31 1991-09-10 International Business Machines Corporation Asynchronous microprocessor random access memory arbitration controller
US5001671A (en) * 1989-06-27 1991-03-19 Vitelic Corporation Controller for dual ported memory
JPH0388196A (ja) * 1989-08-31 1991-04-12 Sony Corp 半導体メモリ
US5384737A (en) * 1994-03-08 1995-01-24 Motorola Inc. Pipelined memory having synchronous and asynchronous operating modes
JPH0981449A (ja) * 1995-09-13 1997-03-28 Fujitsu Ltd 擬似デュアルポートメモリ
US5768211A (en) 1996-07-31 1998-06-16 Cypress Semiconductor Corporation Multi-port arbitration for high performance width expansion
JP4153579B2 (ja) * 1998-01-22 2008-09-24 松下電器産業株式会社 メモリアクセス制御装置
TW451215B (en) * 1998-06-23 2001-08-21 Motorola Inc Pipelined dual port integrated circuit memory
JP3871813B2 (ja) * 1998-08-10 2007-01-24 株式会社ルネサステクノロジ マルチポートメモリ、データプロセッサ及びデータ処理システム
US5973985A (en) 1998-08-11 1999-10-26 Stmicroelectronics, Inc. Dual port SRAM cell having pseudo ground line or pseudo power line
US6388939B1 (en) 1999-09-30 2002-05-14 Cypress Semiconductor Corp. Dual port sram
US6118689A (en) 1999-10-27 2000-09-12 Kuo; James B. Two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
US6816955B1 (en) 2000-09-29 2004-11-09 Cypress Semiconductor Corp. Logic for providing arbitration for synchronous dual-port memory
JP4997663B2 (ja) * 2000-12-27 2012-08-08 富士通セミコンダクター株式会社 マルチポートメモリおよびその制御方法
US6751151B2 (en) 2001-04-05 2004-06-15 International Business Machines Corporation Ultra high-speed DDP-SRAM cache
US6606275B2 (en) 2001-08-23 2003-08-12 Jeng-Jye Shau High performance semiconductor memory devices
JP2005044334A (ja) * 2003-07-09 2005-02-17 Hitachi Ltd 非同期制御回路と半導体集積回路装置
KR100560948B1 (ko) 2004-03-31 2006-03-14 매그나칩 반도체 유한회사 6 트랜지스터 듀얼 포트 에스램 셀
US7349285B2 (en) * 2005-02-02 2008-03-25 Texas Instruments Incorporated Dual port memory unit using a single port memory core
JP2006252656A (ja) 2005-03-10 2006-09-21 Nec Electronics Corp マルチポートメモリ装置
JP4914034B2 (ja) 2005-06-28 2012-04-11 セイコーエプソン株式会社 半導体集積回路
US7533222B2 (en) * 2006-06-29 2009-05-12 Mosys, Inc. Dual-port SRAM memory using single-port memory cell
US7564738B2 (en) 2006-08-11 2009-07-21 Freescale Semiconductor, Inc. Double-rate memory
JP4286295B2 (ja) * 2007-03-02 2009-06-24 Ｏｋｉセミコンダクタ株式会社 調停回路
JP2010044821A (ja) * 2008-08-11 2010-02-25 Hitachi Ulsi Systems Co Ltd 半導体装置とメモリマクロ
TWI425508B (zh) * 2009-04-23 2014-02-01 Orise Technology Co Ltd 具隱藏更新及雙埠能力之ｓｒａｍ相容嵌入式ｄｒａｍ裝置
US8514652B2 (en) * 2011-03-02 2013-08-20 Lsi Corporation Multiple-port memory device comprising single-port memory device with supporting control circuitry

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5398211A (en) * 1993-10-14 1995-03-14 Integrated Device Technology, Inc. Structure and method for providing prioritized arbitration in a dual port memory
US5781480A (en) * 1997-07-29 1998-07-14 Motorola, Inc. Pipelined dual port integrated circuit memory
US6078527A (en) * 1997-07-29 2000-06-20 Motorola, Inc. Pipelined dual port integrated circuit memory
CN1643502A (zh) * 2002-03-18 2005-07-20 松下电器产业株式会社 信息处理装置

Also Published As

Publication number Publication date
CN102999455A (zh) 2013-03-27
US20130073763A1 (en) 2013-03-21
US8867303B2 (en) 2014-10-21
EP2571027A1 (en) 2013-03-20
JP6317876B2 (ja) 2018-04-25
JP2013065391A (ja) 2013-04-11

Similar Documents

Publication Publication Date Title
CN102999455B (zh) 存储器仲裁电路
US7903497B2 (en) Multi-port SRAM implemented with single-port 6-transistor memory cells coupled to an input multiplexer and an output demultiplexer
JP3843145B2 (ja) 同期型半導体記憶装置
CN206097924U (zh) 双端口寄存器组和电子系统
US9298211B2 (en) Time division multiplexed multiport memory implemented using single-port memory elements
JP4603103B2 (ja) 内容参照メモリ
CN101971263A (zh) 伪双端口存储器中的地址多路复用
JP2011048870A (ja) 半導体記憶装置
CN108231106A (zh) 用于与单端口sram一起使用的可配置伪双端口架构
TWI862804B (zh) 位元線預充電技術
JP4282408B2 (ja) 半導体記憶装置
KR100524844B1 (ko) 완전 히든 리프레쉬 다이나믹 랜덤 액세스 메모리
US9311990B1 (en) Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methods
US20230223075A1 (en) Pseudo-triple-port sram datapaths
US9208856B2 (en) Multiport memory with matching address control
Nautiyal et al. An ultra high density pseudo dual-port SRAM in 16nm FINFET process for graphics processors
JP2008004218A (ja) 半導体集積回路装置
US12073912B2 (en) Apparatuses and methods for command decoding with series connected latches
JP3569315B2 (ja) 同期型半導体記憶装置
JP2009087534A (ja) 半導体記憶装置
US12190994B2 (en) Single port memory with multiple memory operations per clock cycle
TWI819702B (zh) 半導體裝置及其操作方法
JP4628319B2 (ja) 同期型半導体記憶装置
US20250259673A1 (en) Circuitry to detect cycle count for increased throughput reads and write operations for memory
JP2010044821A (ja) 半導体装置とメモリマクロ

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant