CN102870209B - 电路装置的制造方法 - Google Patents

电路装置的制造方法 Download PDF

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CN102870209B
CN102870209B CN201180019475.XA CN201180019475A CN102870209B CN 102870209 B CN102870209 B CN 102870209B CN 201180019475 A CN201180019475 A CN 201180019475A CN 102870209 B CN102870209 B CN 102870209B
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semiconductor substrate
temperature
circuit arrangement
layer
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CN102870209A (zh
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齐藤浩一
冈山芳央
柳瀬康行
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Panasonic Intellectual Property Management Co Ltd
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Abstract

在通过晶圆级工艺技术制造电路装置的情况下，抑制半导体衬底的弯曲。为使设于半导体衬底（50）的元件电极（52），和被薄型化前的铜板（200）所连接的突起电极（32）电连接，在以130℃以下的温度（第1温度）贴合半导体衬底（50）和被层叠了绝缘树脂层（20）的铜板（200）后，在将铜板（200）薄膜化为布线层的厚度的状态下，以170℃以上的高温（第2温度）压接半导体衬底（50）和被层叠了绝缘树脂层（20）的铜板（200）。此后，通过使薄膜化后的铜板（200）布线成形，来形成布线层（再布线）。

Description

电路装置的制造方法
技术领域
本发明涉及将热膨胀率不同的半导体衬底和布线衬底贴合来制造电路装置的方法。
背景技术
以往有被称作CSP(ChipSizePackage：芯片尺寸封装)的电路装置。该CSP的电路装置通过对在一个主面上形成有LSI(电路元件)及与其连接的外部连接电极的半导体晶圆(半导体衬底)进行芯片切割、使它们个体化而形成。因此，电路装置能够以和LSI芯片同等的尺寸固定于布线衬底，能够使安装电路装置侧的布线衬底(母插件板：Motherboard)小型化。
近年，随着电子设备的小型化、多功能化，寻求电子设备所使用的电路装置的进一步的小型化。随着这样的电路装置的小型化，用于安装于母插件板的电极之间的窄间距化是不可缺少的。作为电路装置的表面安装方法，已知有在电路装置的外部连接电极处形成焊接球，将焊接球和母插件板的电极片焊接的倒装芯片安装方法。在倒装芯片安装方法中，焊接球自身的大小、焊接时的桥连发生等成为制约，外部连接电极的窄间距化是有限度的。近年来，为了突破这样的限度，通过在电路装置上形成再布线而进行外部连接电极的重新配置。作为这样的重新配置的方法，例如已知有将通过对金属板进行半蚀而形成的突起构造作为电极或者过孔(Via)，介由环氧树脂等绝缘层将电路装置安装在金属板上，使电路装置的外部连接电极连接于突起构造的方法(参照专利文献1)。
在先技术文献
专利文献
专利文献1：日本特开平9-289264号公报
发明内容
发明所要解决的课题
在半导体衬底上配设有多个电路元件的晶圆阶段通过压力(press)加工而形成再布线后，因半导体衬底与构成再布线的金属、例如与铜的热膨胀率的差异，在压力加工后的冷却过程中会发生弯曲。若晶圆发生弯曲，则会出现如下问题：晶圆产生裂痕，在之后所进行的光刻(lithography)工序中，在面内发生焦深上的偏移，无法妥当地进行曝光等。
本发明是鉴于这样的课题而研发的，其目的在于提供一种在利用晶圆级加工技术制造电路装置的情况下，能够抑制半导体衬底的弯曲的技术。
用于解决课题的手段
本发明的一个方案是电路装置的制造方法。该电路装置的制造方法的特征在于，包括：准备在一个面上设有元件电极的半导体衬底，和在一个面上设有金属板、在另一个面上设有与上述元件电极对应的衬底电极的布线衬底的工序，以及将上述金属板薄膜化为布线层的厚度的工序；该电路装置的制造方法中，在准备上述布线衬底的工序后、进行上述薄膜化的工序前，具有为使上述元件电极与上述衬底电极连接而施加第1温度地贴合上述半导体衬底和上述布线衬底的第1压接工序；在上述进行薄膜化的工序后，具有施加比上述第1温度高的第2温度地压接以上述第1温度贴合后的上述半导体衬底和上述布线衬底的第2压接工序，上述第1温度在130℃以下。
通过该方案的电路装置的制造方法，在贴合布线衬底和半导体衬底时将温度定为低温，由此能减少因薄膜化前的金属板与半导体衬底的热膨胀率的不同而施加于半导体衬底的应力。由此，能够抑制半导体衬底出现弯曲和损坏。此外，在以低温使布线衬底和半导体衬底贴合后，将设置于布线衬底的金属板薄膜化，并以高温压接布线衬底和半导体衬底，由此，在高温压接时，热膨胀率相对较大的金属的比例被降低。由此，能够减小加于半导体衬底的应力，抑制半导体衬底出现弯曲和损坏，并提高配线衬底和半导体衬底的粘接强度。
在上述方案的电路装置的制造方法中，可以在上述第2压接工序时，在与元件电极形成面相反侧的上述半导体衬底的面上贴合与被薄膜化了的上述金属板同等厚度的其它金属板。也可以在上述第2压接工序后，还具有将上述被薄膜化后的金属板布线成形而形成布线层的工序。此外，可以在进行上述第2压接工序时，在与元件电极形成面相反侧的上述半导体衬底的面上贴合与被薄膜化后的上述金属板同等厚度的其它金属板，并在上述第2压接工序后，并行地进行将上述被薄膜化后的金属板布线成形而形成布线层的工序和除去上述其它金属板的工序。
发明效果
通过本发明，能够在制造通过贴合半导体衬底和布线衬底而薄型化了的电路装置时，抑制弯曲的产生和半导体衬底的损坏。
附图说明
图1是表示实施方式的电路装置的构成的概略剖面图。
图2是表示实施方式的电路装置的制造方法的工序剖面图。
图3是表示实施方式的电路装置的制造方法的工序剖面图。
图4是表示实施方式的电路装置的制造方法的工序剖面图。
图5是表示实施方式的电路装置的制造方法的工序剖面图。
图6是表示实施方式的电路装置的制造方法的工序剖面图。
图7是表示实施方式的电路装置的制造方法的工序剖面图。
图8是表示实施方式的电路装置的制造方法的工序剖面图。
图9是表示低温贴合时的温度与铜板膜厚的面内偏差的关系的图表。
具体实施方式
下面，参照附图对本发明的实施方式进行说明。在所有附图中，对同样的构成要素附加同样的标号，并适当省略说明。
图1是表示实施方式的电路装置10的构成的概略剖面图。电路装置10具备布线衬底12及与布线衬底12相贴合的半导体衬底50。
布线衬底12具备：绝缘树脂层20，以绝缘性树脂形成；布线层30，被设于绝缘树脂层20的一个主表面；与布线层30电连接的多个突起电极32，从布线层30向绝缘树脂层20侧突起。
作为构成绝缘树脂层20的材料，例如可以例示BT树脂等的三聚氰胺衍生物、液晶聚合物、环氧树脂、PPE树脂、聚酰亚胺树脂、含氟树脂、苯酚树脂、聚酰胺双马来酰亚胺等的热固化性树脂。从提高电路装置10的散热性的角度出发，绝缘树脂层20优选具有高热传导性。因此，绝缘树脂层20优选含有银、铋、铜、铝、镁、锡、锌、及它们的合金、氧化铝等作为高热传导性填充物。
布线层30被设在绝缘树脂层20的一个主表面，由导电材料、优选由轧制金属、更优选由轧制铜形成。布线层30的绝缘树脂层20侧突出地设有多个突起电极32。在本实施方式中，布线层30与突起电极32是一体地形成的，但并不限定于此。
突起电极32例如俯视看是圆形，并具有越接近顶部、直径就越变细地形成的侧面。此外，突起电极32的形状不特别限定，例如也可以是具有预定直径的圆柱状。此外，也可以是俯视看呈四角形等多角形。
突起电极32的顶部面设有Au/Ni层34。Au/Ni层34由作为暴露面的Au层和介于Au层与突起电极32的顶部面之间的Ni层构成。
在与布线层30的绝缘树脂层20相反的一侧的主表面，设有用于防止布线层30的氧化等的保护层70。作为保护层70，能够举出阻焊层等。在保护层70的预定区域，形成有开口部72，通过开口部72，布线层30的一部分暴露。在开口部72内形成作为外部连接电极的焊接球80，焊接球80和布线层30电连接。形成焊接球80的位置、即开口部72的形成区域例如是用再布线(布线层30)所引至的目的地的端部。
元件电极52、Au/Ni层54及保护层56被形成在半导体衬底50的一个主表面。具体来讲，半导体衬底50是P型硅衬底等硅衬底，其热膨胀率与布线层30不同。一般来讲，硅衬底的线膨胀系数比铜要小一个位数左右。在半导体衬底50的一个主表面，形成有预定的集成电路(未图示)及位于其外周边缘部的元件电极52。元件电极52的材料采用铝、铜等金属。在半导体衬底50上的除元件电极52处以外的主表面上，形成有用于保护半导体衬底50的绝缘性保护层56。作为保护层56，采用氧化硅膜(SiO2)、氮化硅膜(SiN)、聚酰亚胺(PI)等。此外，元件电极52上形成有Au层为暴露面的Au/Ni层54。此外，有时也将半导体衬底50叫做半导体元件。
通过设于突起电极32的顶部面的Au/Ni层34的金与设于元件电极52的表面的Au/Ni层54的金进行金-金粘接，突起电极32和与其对应的元件电极52被电连接。此外，Au/Ni层34和Au/Ni层54进行金-金粘接有助于突起电极32和与它对应的元件电极52的电连接的可靠性的提高。
(电路装置的制造方法)
参照图2至图8对实施方式的电路装置10的制造方法进行说明。
首先，如图2的(A)所示的那样，准备作为金属板的铜板200，其具有至少比如图1所示的突起电极32的高度和布线层30的厚度之和大的厚度。铜板200的厚μm如是65μm。作为铜板200，采用由被轧制的铜构成的轧制金属。
接着，如图2的(B)所示的那样，在由切割道(scribeline)L所包围的各区域中，按照与图1所示的突起电极32的形成预定区域对应的图案(pattern)，通过光刻法选择性地形成阻焊部(resist)202。具体来讲，使用层压装置(laminater)将预定膜厚度的阻焊膜贴在铜板200上，使用具有突起电极32的图案的光掩模进行曝光后，通过显影而在铜板200上选择性地形成阻焊部202。此外，为了提高与阻焊部202的紧密性，在层叠阻焊膜之前，优选根据需要而对铜板200的表面施以研磨、冲洗等预处理。此外，优选预先在与设有阻焊部202的面相反侧(在图2的(B)中是上面侧)的整面上形成阻焊保护膜(未图示)，来保护铜板200。
接下来，如图2的(C)所示的那样，通过以阻焊部202为掩模进行使用了氯化铁溶液等药液的湿式蚀刻(Wetetching)处理，来形成从铜板200的表面S突出的预定图案的突起电极32。此时，突起电极32具有越接近其前端部、直径(尺寸)就越变细的锥状的侧面部。此外，突起电极32的高μm如是20μm。
接下来，如图2的(D)所示的那样，使用剥离剂剥离阻焊部202及阻焊保护膜。通过上述所说明的工序，突起电极32被一体地形成于铜板200。
然后，如图3的(A)所示的那样，在突起电极32的顶部面上形成Au/Ni层34。在Au/Ni层34中，Au层是暴露面，Ni层介于Au层和突起电极32的顶部面之间。作为Au/Ni层34的形成方法，可以举出例如在铜板200的表面S侧层叠阻焊部(未图示)，在该阻焊部的与突起电极32的顶部面对应的位置，使用光刻法形成开口部，在该开口部内通过电解电镀法或非电解镀层法来形成Au/Ni层34的方法。在Au/Ni层34中，例如Au层的厚度是0.25μm，Ni层的厚度是1～3μm。此外，也可以使用例如金糊(paste)等导电性糊来代替Au/Ni层34，在突起电极32的顶部面形成金属层。
接下来，如图3的(B)所示的那样，使用辊层压器(rolllaminater)或热压机在设有突起电极32侧的铜板200的表面S上层叠绝缘树脂层20。作为绝缘树脂层20，例如使用热硬化性的环氧系粘接树脂膜。被层叠的绝缘树脂层20的厚度只要是足够覆盖突起电极32的顶部面的厚度即可。在后述的工序中，为了贴合到半导体衬底50，环氧系粘接树脂膜的层叠时的温度优选是环氧系粘接树脂膜不完全硬化的温度(100℃以下)。
接下来，如图3的(C)所示的那样，使用O2等离子蚀刻或研磨处理，将绝缘树脂层20薄膜化，使得突起电极32的顶部面露出，并且突起电极32的顶部面与绝缘树脂层20的下面成为同一面。由此，由铜板200、突起电极32及绝缘树脂层20构成的布线衬底12形成。
接下来，如图4的(A)所示的那样，准备在一个主表面上形成了元件电极52、Au/Ni层54及保护层56的半导体衬底50。具体来讲，对P型硅衬底等半导体衬底50，使用组合了公知的光刻技术、蚀刻技术、离子注入技术、成膜技术、以及热处理技术等的半导体制造工艺，在一个主表面形成预定的集成电路，在其外周边缘部形成元件电极52。元件电极52的材料采用铝、铜等金属。在半导体衬底50上的除这些元件电极52处以外的主表面上，形成有用于保护半导体衬底50的绝缘性的保护层56。作为保护层56，采用氧化硅膜(SiO2)、氮化硅膜(SiN)、聚酰亚胺(PI)等。此外，在元件电极52上形成Au层为暴露面的Au/Ni层54。Au/Ni层54的层结构及形成方法与Au/Ni层34一样，能够通过在形成了具有开口部的掩膜的状态下，在该开口部内进行电解电镀或非电解电镀而形成，所述开口部是使元件电极52的表面露出的开口部。
接下来，如图4的(B)所示的那样，将设于元件电极52的Au/Ni层54和与Au/Ni层54对应地设于突起电极32的顶部面的Au/Ni层34进行对位后，用压力机将布线衬底12和半导体衬底50贴合。将布线衬底12和半导体衬底50贴合时的温度是80℃以上130℃以下的低温(第1温度)，更优选的是90℃以上130℃以下。贴合时的温度比80℃低时，不能够得到足够的贴合强度。贴合时的温度在130℃以上时，半导体衬底50的弯曲会变大。本工序中贴合布线衬底12和半导体衬底50时的贴合时间、压力例如分别是3分钟、1MPa。
接下来，如图5的(A)所示的那样，通过使用了氯化铁溶液等药液的湿式蚀刻处理等，对与设有突起电极32一侧相反侧的铜板200的表面进行凹蚀(etchback)，来使铜板200薄膜化。由此，被加工成预定的厚度(布线层30的厚度)，形成一体地设有预定的突起电极32的铜板200。薄膜化后的铜板200的厚μm如是约15μm。
接下来，如图5的(B)所示的那样，在与半导体衬底50的电极形成面相反侧的面上，介由粘接树脂层210地载置防止弯曲用的铜箔220。铜箔220的厚度与铜板200的厚度相同。
接下来，如图6的(A)所示的那样，用压力机压接布线衬底12和半导体衬底50。这时，介由粘接树脂层210地在与半导体衬底50的电极形成面相反侧的面上通过压接而粘上防止弯曲用的铜箔220。在本工序中，压接布线衬底12和半导体衬底50时的温度是比图4的(B)所示的贴合时的温度高的温度(第2温度)，是绝缘树脂层20完全硬化的温度，换言之是绝缘树脂层20内的树脂的反应速率成为95％以上的温度。虽然压接布线衬底12和半导体衬底50时的温度根据绝缘树脂层20的材料的不同而不同，但典型的是170℃以上。在将压接布线衬底12和半导体衬底50时的温度定为170℃的情况下，压接时间是45分钟，在将压接布线衬底12和半导体衬底50时的温度定为200℃的情况下，压接时间是10分钟。此外，本工序中压接布线衬底12和半导体衬底50时的压力例如是1Mpa。此外，高温的温度范围的上限值是绝缘树脂层20被化学分解的温度，具体来讲是300℃。
图4的(B)所示的贴合工序是临时粘接布线衬底12和半导体衬底50的第1压接工序，图6的(A)所示的压接工序是最终粘接或实粘接布线衬底12和半导体衬底50的第2压接工序。像这样，本实施方式的电路装置的制造方法的特征在于，通过以相对低温进行的第1压接工序和相对高温进行的第2压接工序这两个阶段的压接工序，来进行布线衬底12和半导体衬底50的压接。
接下来，如图6的(B)所示的那样，将使用光刻技术和蚀刻技术薄膜化了的铜板200加工成预定的布线图案，由此形成布线层(再布线)30。由此，被加工成预定的厚度、预定的突起电极32被一体地设置了的布线层30形成。换言之，突起电极32和布线层30被以同一材料连续地形成。此外，与布线成形(patterning)并行地通过蚀刻而除去铜箔220。通过使用同一蚀刻液进行铜板200的布线成形和铜箔220的除去，可以谋求电路装置10的制造时间的缩短和制造成本的降低。
接下来，如图7的(A)所示的那样，在布线层30及露出的绝缘树脂层20的上面层叠保护层(光阻焊层：photosolderresist)70后，通过光刻法在保护层70的预定区域(焊接球承载区域)设置开口部72。保护层70作为布线层30的保护膜而发挥作用。保护层70采用环氧树脂等，其膜厚例如是约30μm。
接下来，如图7的(B)所示的那样，通过进行背研(BackGrind)处理除去粘接树脂层210。然后，在保护层70的开口部72通过网版印刷(screenprint)法装配焊接球80。具体来讲，将使树脂和焊料作成糊状的焊料糊通过网版掩模印刷在所需要的位置，通过加热到焊料熔融温度来形成焊接球80。
接下来，如图8所示的那样，通过沿着切割道L进行切割加工，将电路装置10切割为独立的片。
通过以上的工序，能够制造实施方式1的电路装置10。在上述的电路装置10的制造方法中，在贴合布线衬底12和半导体衬底50之前的阶段中，构成布线衬底12的铜板200没有被薄膜化，具有45μm左右的厚度。因此，能够抑制铜板200发生褶皱，并能够使铜板200自身和设有铜板200的布线衬底12的操作处理(handling)变得容易。
此外，在贴合布线衬底12和半导体衬底50时，通过使温度为低温，能够降低因薄膜化之前的铜板200与半导体衬底50的热膨胀率的不同而施加于半导体衬底50的应力。由此，能够抑制半导体衬底50发生弯曲和损坏。
此外，以低温贴合布线衬底12和半导体衬底50后，将设于布线衬底12的铜板200薄膜化，并以高温压接布线衬底12和半导体衬底50，由此，在高温压接时，热膨胀率相对较大的铜板200的比例被降低了。由此，能够减小加于半导体衬底50的应力，抑制半导体衬底50发生弯曲和损坏，并提高布线衬底12和半导体衬底50的粘接强度。
在以高温压接布线衬底12和半导体衬底50时，通过对半导体衬底50粘贴与被薄膜化后的铜板200同等厚度的铜箔220，由铜板200施加于半导体衬底50的应力因由铜箔220施加于半导体衬底50的应力相抵消，故能够进一步抑制半导体衬底50发生弯曲和损坏。
此外，作为半导体衬底50的弯曲减小的结果，能够提高布线层30的加工精度，能够提高布线层30的线宽度的加工精度，或抑制电阻率的偏差。
(低温贴合时的温度与弯曲的关系)
在此，将以相对低温进行的第1压接工序时的温度称为低温贴合温度。在6英寸的Si晶圆上介由20μm的绝缘树脂层并改变温度地贴合厚度45μm的铜板，计测距Si晶圆的中心75mm处的Si晶圆的弯曲度。将各贴合温度下的Si晶圆的弯曲量表示在表1中。此外，Si晶圆、绝缘树脂层、铜板相当于实施方式的电路装置10的半导体衬底50、绝缘树脂层20、铜板200。
进而，将贴合于Si晶圆的铜板刻蚀，薄膜化到15μm。在薄膜化后的铜板的10个点处计测铜板的膜厚，算出膜厚的面内偏差。该膜厚的面内偏差表示膜厚的测量点10点处的最大值与最小值的差。将在各贴合温度下的刻蚀后的铜板的膜厚表示于表1。此外，将表示低温贴合时的温度(第1温度)与铜板膜厚的面内偏差的关系的图表表示于图9。
〔表1〕
如表1及图9所示的那样，低温贴合时的温度更低者，被认为有薄膜化后的铜板膜厚的面内偏差减小的倾向。尤其发现低温贴合时的温度变为130℃以下时，薄膜化后的铜板膜厚的面内偏差大幅度地减小。认为这是由于贴合温度越低，贴合了铜板后的Si晶圆的弯曲量就越变小的缘故。此外，弯曲量在2.6mm以下时，能够通过因压接而内在的应力，来抑制在压接后的工序中Si晶圆损坏。
从以上的结果来看，适于低温贴合时的温度的范围，优选Si晶圆的弯曲量在2.6mm以下、薄膜化后的铜板的面内偏差被抑制在1.0μm以下的130℃以下。此外，低温贴合时的温度的下限值是绝缘树脂层20呈现粘接功能的80℃左右。
此外，在此，将以相对高温进行的第2压接工序时的温度称为高温贴合温度(第2温度)。该第2温度比第1压接工序时的温度高，并且是在贴合以第1温度贴合后的半导体衬底和配线衬底时，使介于它们之间的绝缘树脂层完全硬化的温度。具体来讲，第2温度在绝缘树脂层是由环氧树脂构成的情况下是170℃以上。
本发明并不限于上述的各实施方式，能基于本领域技术人员的知识而加以各种设计变更等变形，这样的被加以变形的实施方式也包含于本发明的范围内。
例如，在上述的实施方式中，是与铜板200的布线成形并行地除去铜箔220的，但也可以不除去铜箔220，留下它。由此，能够将铜箔220作为散热板而有效运用。此外，在上述的实施方式中，表示了通过背研处理来除去粘接树脂层210的情况，但也可以将粘接树脂层210留在半导体衬底50的背面。由此，能够保护半导体衬底50的背面。
标号说明
10电路装置、20绝缘树脂层、30布线层、32突起电极、50半导体衬底、52元件电极、56保护层、70保护层
工业可利用性
通过本发明的电路装置的制造方法，能够得到抑制了半导体衬底的弯曲的电路装置。

Claims (6)

1.一种电路装置的制造方法，其特征在于，包括：
准备在一个面上设有元件电极的半导体衬底，和在一个面上设有金属板、在另一个面上设有与上述元件电极对应的衬底电极的布线衬底的工序，以及
将上述金属板薄膜化为布线层的厚度的工序；
该电路装置的制造方法中，
在准备上述布线衬底的工序后、进行上述薄膜化的工序前，具有为使上述元件电极与上述衬底电极连接而施加第1温度地贴合上述半导体衬底和上述布线衬底的第1压接工序；
在上述进行薄膜化的工序后，具有施加比上述第1温度高的第2温度地压接以上述第1温度贴合后的上述半导体衬底和上述布线衬底的第2压接工序，
上述第1温度在80℃以上130℃以下。
2.如权利要求1所述的电路装置的制造方法，其特征在于，
在上述半导体衬底和上述布线衬底之间存在绝缘树脂层，上述第2温度是上述绝缘树脂层内的树脂的反应速率在95％以上的温度。
3.如权利要求1或2所述的电路装置的制造方法，其特征在于，
上述第2温度在170℃以上。
4.如权利要求1所述的电路装置的制造方法，其特征在于，
在上述第2压接工序时，在与元件电极形成面相反侧的上述半导体衬底的面上贴合与被薄膜化了的上述金属板同等厚度的其它金属板。
5.如权利要求1所述的电路装置的制造方法，其特征在于，
在上述第2压接工序后，还具有将上述被薄膜化后的金属板布线成形而形成布线层的工序。
6.如权利要求1所述的电路装置的制造方法，其特征在于，
在进行上述第2压接工序时，在与元件电极形成面相反侧的上述半导体衬底的面上贴合与被薄膜化后的上述金属板同等厚度的其它金属板，并且，
并行地进行将上述被薄膜化后的金属板布线成形而形成布线层的工序和除去上述其它金属板的工序。
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