CN102768960A - 封装结构及其制作方法 - Google Patents
封装结构及其制作方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 33
- 238000004806 packaging method and process Methods 0.000 title abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 64
- 239000002184 metal Substances 0.000 claims abstract description 64
- 239000000758 substrate Substances 0.000 claims abstract description 49
- 238000000034 method Methods 0.000 claims abstract description 29
- 239000000084 colloidal system Substances 0.000 claims abstract description 28
- 238000000059 patterning Methods 0.000 claims description 32
- 238000012856 packing Methods 0.000 claims description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 16
- 229910052759 nickel Inorganic materials 0.000 claims description 8
- 238000007747 plating Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
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- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052709 silver Inorganic materials 0.000 claims description 6
- 239000004332 silver Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 3
- 239000010410 layer Substances 0.000 abstract 11
- 239000002335 surface treatment layer Substances 0.000 abstract 3
- 238000009713 electroplating Methods 0.000 abstract 2
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- 230000000694 effects Effects 0.000 description 4
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- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
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- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
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- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
本发明公开一种封装结构的制作方法。提供一已形成有一种子层于其上的金属基板。形成一图案化线路层于种子层的一部分上。形成一第一图案化干膜层于种子层的另一部分上。以第一图案化干膜层为一电镀掩膜,以电镀一表面处理层于图案化线路层上。移除第一图案化干膜层。进行一芯片接合制作工艺,以电连接一芯片至表面处理层上。形成一封装胶体于金属基板上。封装胶体包覆芯片、表面处理层以及图案化线路层。移除金属基板及种子层,以暴露出封装胶体的一底面与图案化线路层的一下表面。
Description
技术领域
本发明涉及一种封装结构及其制作方法,且特别是涉及一种具有较薄厚度的封装结构及其制作方法。
背景技术
芯片封装的目的在于保护裸露的芯片、降低芯片接点的密度及提供芯片良好的散热。常见的封装方法是芯片通过打线接合(wire bonding)或覆晶接合(flip chip bonding)等方式而安装至一封装载板,以使芯片上的接点可电连接至封装载板。因此,芯片的接点分布可通过封装载板重新配置,以符合下一层级的外部元件的接点分布。
一般来说,封装载板的制作通常是以核心(core)介电层作为蕊材,并利用全加成法(fully additive process)、半加成法(semi-additive process)、减成法(subtractive process)或其他方式,将图案化线路层与图案化介电层交错堆叠于核心介电层上。如此一来,核心介电层在封装载板的整体厚度上便会占着相当大的比例。因此,若无法有效地缩减核心介电层的厚度,势必会使封装结构于厚度缩减上产生极大的障碍。
发明内容
本发明提供一种封装结构,具有较薄的封装厚度。
本发明提供一种封装结构的制作方法,用以制作上述的封装结构。
本发明提出一种封装结构的制作方法,其包括下述步骤。提供一金属基板。金属基板具有彼此相对的一第一表面、一第二表面以及一连接第一表面与第二表面的侧表面,且金属基板上已形成有一包覆第一表面、第二表面以及侧表面的种子层。形成一图案化线路层于位于金属基板的第一表面上的种子层的一部分上。形成一第一图案化干膜层于位于金属基板的第一表面上的种子层的另一部分上。以第一图案化干膜层为一电镀掩膜,以电镀一表面处理层于图案化线路层上。移除第一图案化干膜层。进行一芯片接合制作工艺,以电连接一芯片至表面处理层上。形成一封装胶体于金属基板上。封装胶体包覆芯片、表面处理层及图案化线路层。移除金属基板及种子层,以暴露出封装胶体的一底面与图案化线路层的一下表面。
在本发明的一实施例中,上述的形成图案化线路层的的步骤,包括:以第一图案化干膜层为一电镀掩膜,以电镀图案化线路层于第一图案化干膜层所暴露出的种子层的一部分上。
在本发明的一实施例中,上述的形成图案化线路层的步骤,包括:形成一金属层于种子层上,其中金属层包覆种子层;形成一第二图案化干膜层于位于第一表面上的部分金属层上;以第二图案化干膜层为一蚀刻掩膜,移除部分金属层,以暴露出位于第一表面上的种子层的另一部分,并形成图案化线路层;以及移除第二图案化干膜层。
在本发明的一实施例中,上述的表面处理层包括一镍层、一金层、一银层或一镍钯金层。
在本发明的一实施例中,上述的芯片接合制作工艺包括一打线接合制作工艺或一覆晶接合制作工艺。
本发明提出一种封装结构,其包括一图案化线路层、一芯片以及一封装胶体。芯片电连接至图案化线路层。封装胶体包覆芯片及图案化线路层,且暴露出图案化线路层的一下表面。
在本发明的一实施例中,上述的封装结构更包括一表面处理层,配置于图案化线路层上。
在本发明的一实施例中,上述的表面处理层包括一镍层、一金层、一银层或一镍钯金层。
在本发明的一实施例中,上述的芯片通过打线接合或覆晶接合技术与图案化线路层电连接。
在本发明的一实施例中,上述的图案化线路层的下表面与封装胶体的一底面实质上齐平。
基于上述,由于本发明是先以金属基板做为载体,通过电镀法(plating)或减成法来(subtractive process)形成图案化线路层,且待芯片进行完封装后,再将金属基板及种子层移除。如此一来,相比较于现有具有核心介电层的封装结构而言,本发明的封装结构因可具有较薄的封装厚度。再者,由于芯片配置于图案化线路层上,且封装胶体暴露出图案化线路层的下表面。因此,芯片所发出的热可经由图案化线路层而快速地传递至外界。故,本发明的封装结构可具有较佳的散热效果。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附附图作详细说明如下。
附图说明
图1A至图1E为本发明的一实施例的一种封装结构的制作方法的剖面示意图;
图1F为本发明的另一实施例的一种封装结构的剖面示意图;
图2A至图2D为本发明的另一实施例的一种封装结构的制作方法的剖面示意图。
主要元件符号说明
100a、100b、100c:封装结构
110:金属基板
112:第一表面
114:第二表面
116:侧表面
118:定位孔
120、120a:种子层
130、130c:图案化干膜层
130d:干膜层
140、140b、140c:图案化线路层
140a:金属层
142:芯片垫
144:接垫
146、146c:下表面
150:表面处理层
160a、160b、160b:芯片
170:焊线
180:封装胶体
182:底面
具体实施方式
图1A至图1E为本发明的一实施例的一种封装结构的制作方法的剖面示意图。请先参考图1A,依照本实施例的封装结构的制作方法,首先,提供一金属基板110,其中金属基板110上已形成有一种子层120。详细来说,在本实施例中,金属基板110具有彼此相对的一第一表面112与一第二表面114、一连接第一表面112与第二表面114的侧表面116以及至少一贯穿第一表面112与第二表面114的定位孔118(tooling hole)。金属基板110的材质包括具有高导热性的金属,例如是铜或铝,合金,例如是铜合金或铝合金,但不以此为限。种子层120例如是一化学铜层,其是通过电镀法电镀于金属基板110的第一表面112、第二表面114、侧表面116以及定位孔118的内壁上。
接着,请参考图1B,形成一图案化干膜层130于种子层120上,其中图案化干膜层130暴露出部分种子层120。详细来说,图案化干膜层130完全覆盖位于金属基板110的第二表面114上方的种子层120以及定位孔118的两端,并暴露出位于金属基板110的第一表面112上方的部分种子层120。
接着,请再参考图1B,形成一图案化线路层140于图案化干膜层130所暴露出的部分种子层120上。在本实施例中,例如是通过图案化干膜层130来进行一电镀制作工艺,以电镀图案化线路层140于金属基板110的第一表面112上方被图案化干膜层130所暴露出的种子层120上。其中,本实施例可通过图案化干膜层130来控制图案化线路层140的线宽与厚度。于此,图案化线路层140的线宽例如是小于30微米,因此相比较于一般线路层的线宽而言,本实施例的图案化线路层140可视为一微细线路层。
接着,请参考图1C,形成一表面处理层150于图案化线路层140上,其中表面处理层150例如是一镍层、一金层、一银层、一镍钯金层或其他适当的材料层,在此并不加以限制。接着,移除图案化干膜层130,以暴露出位于金属基板110的第一表面112上、第二表面114上及定位孔118的内壁上的种子层120。
接着,请参考图1D,进行一芯片接合制作工艺,以电连接一芯片160a至位于图案化线路层140上方的表面处理层150,其中本实施例的芯片接合制作工艺例如是一打线接合制作工艺。详细来说,图案化线路层140包括一芯片垫142以及至少一接垫144,其中芯片160a配置于芯片垫142上,且芯片160a通过一焊线170电连接至接垫144上。芯片160a例如是一发光二极管芯片、一激光二极管芯片、一绘图芯片、一存储器芯片、一半导体芯片等单一芯片或是一芯片模块。
然后,请再参考图1D,形成一封装胶体180于金属基板110上,其中封装胶体180包覆芯片160a、焊线170、表面处理层150、图案化线路层140以及种子层120。
最后,请同时参考图1D与图1E,进行一单体化制作工艺,以沿着定位孔118切割金属基板110。并且,移除金属基板110及覆盖于金属基板110的第一表面112上、第二表面114上以及定位孔118的内壁上的种子层120,以暴露出封装胶体180的一底面182与图案化线路层140的一下表面146。至此,已完成封装结构100a的制作。
在结构上,请再参考图1E,本实施例的封装结构100a包括图案化线路层140、表面处理层150、芯片160a、焊线170以及封装胶体180。图案化线路层140包括芯片垫142以及接垫144。芯片160a配置于芯片垫142上且通过焊线170电连接至图案化线路层140。表面处理层150配置于图案化线路层140上,且部分表面处理层150位于芯片160a与芯片垫142之间,而焊线170连接于芯片160a与接垫144上方的表面处理层150之间。表面处理层150例如是一镍层、一金层、一银层、一镍钯金层或其他适当的材料层。封装胶体180包覆芯片160a、焊线170、表面处理层150及图案化线路层140,且暴露出图案化线路层140的下表面146。特别是,图案化线路层140的下表面146与封装胶体180的底面182实质上齐平。
由于本实施例的封装结构100a的制作方法是进行完芯片160a的封装后,意即形成封装胶体180,再移除金属基板110及覆盖金属基板110上的种子层120。如此一来,相较于现有具有核心介电层的封装结构而言,本实施例的封装结构100a因不具有金属基板110,因而可具有较薄的封装厚度。此外,移除后的金属基板110也可重复利用,相较于现有采用核心介电层的封装结构而言,本实施例的封装结构100a也有降低材料成本的优势。再者,由于芯片160a配置于图案化线路层140上,且封装胶体180暴露出图案化线路层140的下表面146。因此,芯片160a所发出的热可经由图案化线路层140而快速地传递至外界。故,本实施例的封装结构100a可具有较佳的散热效果。此外,由于本实施例可通过图案化干膜层130来控制图案化线路层140的线宽与厚度,因此可制作出所需的微细线路层。
值得一提的是,本发明并不限定芯片160a与图案化线路层140的接合形态,虽然此处所提及的芯片160a具体化是通过打线接合而电连接至接垫144(即图案化线路层140)上方的表面处理层150上。不过,在另一实施例中,请参考图1F的封装结构100b,其中芯片160b也可通过覆晶接合的方式而电连接至位于图案化线路层140b上方的表面处理层150上。由此可知,上述的芯片160a与图案化线路层140的接合形态仅为举例说明之用,并非用以限定本发明。
以下将再利用一实施例来说明封装结构100c及其制作方法。在此必须说明的是,下述实施例沿用前述实施例的元件标号与部分内容,其中采用相同的标号来表示相同或近似的元件,并且省略了相同技术内容的说明。关于省略部分的说明可参考前述实施例,下述实施例不再重复赘述。
图2A至图2D为本发明的另一实施例的一种封装结构的制作方法的剖面示意图。请先参考图2A,依照本实施例的封装结构的制作方法,首先,首先,提供一金属基板110,其中金属基板110上已形成有一种子层120a,且种子层120a是由一电镀种子层122以及一包覆电镀种子层122的镍层124所组成。于此,种子层120a包覆金属基板110的第一表面112、第二表面114以及侧表面116。
接着,请再参考图2A,形成一金属层140a于种子层120a的镍层124上,其中金属层140a包覆种子层120a,且金属层140a的厚度大于种子层120a的厚度。
接着,请同时参考图2A与2B,形成一图案化干膜层130c于位于金属基板110的第一表面112上的部分金属层140a上。并且,以图案化干膜层130c为一蚀刻掩膜,移除部分金属层140a,以暴露出位于第一表面112上的种子层120a的一部分,并形成一图案化线路层140c。意即,本实施例使采用减成法的方式来形成图案化线路层140c。接着,移除图案化干膜层130c以暴露出图案化线路层140c。
然后,请参考图2C,形成一图案化干膜层130于图案化线路层140c所暴露出位于第一表面112上的种子层120a的部分上,以及形成一干膜层130d于位于第二表面114上的种子层120a上。其中,干膜层130d完全覆盖位于第二表面114上的种子层120a。并且,以图案化干膜层130为一电镀掩膜,以电镀一表面处理层150于图案化线路层上140c。
最后,依据进行移除图案化干膜层130及干膜层130d、进行一芯片接合制作工艺(其例如是打线接合制作工艺),以电连接一芯片160c至表面处理层150上、形成一封装胶体180于金属基板110上,以包覆芯片160c、表面处理层150以及图案化线路层140c以及移除金属基板110及种子层120a,以暴露出封装胶体180的底面182与图案化线路层140c的一下表面146c,而完成图2D的封装结构100c的制作。此时,图案化线路层140c的下表面146c与封装胶体180的底面182实质上齐平。
由于本实施例的封装结构100c的制作方法是进行完芯片160c的封装后,意即形成封装胶体180,再移除金属基板110及覆盖金属基板110上的种子层120a。如此一来,相比较于现有具有核心介电层的封装结构而言,本实施例的封装结构100c因不具有金属基板110,因而可具有较薄的封装厚度。此外,移除后的金属基板110也可重复利用,相较于现有采用核心介电层的封装结构而言,本实施例的封装结构100c也有降低材料成本的优势。再者,由于芯片160c配置于图案化线路层140c上,且封装胶体180暴露出图案化线路层140c的下表面146c。因此,芯片160c所发出的热可经由图案化线路层140c而快速地传递至外界。故,本实施例的封装结构100c可具有较佳的散热效果。
综上所述,由于本发明是先以金属基板做为载体,通过电镀法(plating)或减成法来(subtractive process)形成图案化线路层,且待芯片进行完封装后,再将金属基板及种子层移除。如此一来,相比较于现有具有核心介电层的封装结构而言,本发明的封装结构因不具有载体,因而可具有较薄的封装厚度。再者,由于芯片配置于图案化线路层上,且封装胶体暴露出图案化线路层的下表面。因此,芯片所发出的热可经由图案化线路层而快速地传递至外界。故,本发明的封装结构可具有较佳的散热效果。此外,本发明可通过图案化干膜层来控制图案化线路层的线宽与厚度,以可制作出所需的微细线路层。
虽然结合以上实施例揭露了本发明,然而其并非用以限定本发明,任何所属技术领域中熟悉此技术者,在不脱离本发明的精神和范围内,可作些许的更动与润饰,故本发明的保护范围应以附上的权利要求所界定的为准。
Claims (10)
1.一种封装结构的制作方法,包括:
提供一金属基板,该金属基板具有彼此相对的一第一表面、一第二表面以及一连接该第一表面与该第二表面的侧表面,且该金属基板上已形成有一包覆该第一表面、该第二表面以及该侧表面的种子层;
形成一图案化线路层于位于该金属基板的该第一表面上的该种子层的一部分上;
形成一第一图案化干膜层于该金属基板的该第一表面上的该种子层的另一部分上;
以该第一图案化干膜层为一电镀掩膜,以电镀一表面处理层于该图案化线路层上;
移除该第一图案化干膜层;
进行一芯片接合制作工艺,以电连接一芯片至该表面处理层上;
形成一封装胶体于该金属基板上,该封装胶体包覆该芯片、该表面处理层以及该图案化线路层;以及
移除该金属基板及该种子层,以暴露出该封装胶体的一底面与该图案化线路层的一下表面。
2.如权利要求1所述的封装结构的制作方法,其中形成该图案化线路层的步骤,包括:
以该第一图案化干膜层为一电镀掩膜,以电镀该图案化线路层于该第一图案化干膜层所暴露出的该种子层的该一部分上。
3.如权利要求1所述的封装结构的制作方法,其中形成该图案化线路层的步骤,包括:
形成一金属层于该种子层上,其中该金属层包覆该种子层;
形成一第二图案化干膜层于位于该第一表面上的部分该金属层上;
以该第二图案化干膜层为一蚀刻掩膜,移除部分该金属层,以暴露出位于该第一表面上的该种子层的该另一部分,并形成该图案化线路层;以及
移除该第二图案化干膜层。
4.如权利要求1所述的封装结构的制作方法,其中该表面处理层包括一镍层、一金层、一银层或一镍钯金层。
5.如权利要求1所述的封装结构的制作方法,其中该芯片接合制作工艺包括一打线接合制作工艺或一覆晶接合制作工艺。
6.一种以权利要求1所述的封装结构的制作方法所制作的封装结构,包括:
图案化线路层;
芯片,电连接至该图案化线路层;以及
封装胶体,包覆该芯片及该图案化线路层,且暴露出该图案化线路层的一下表面。
7.如权利要求6所述的封装结构,还包括一表面处理层,配置于该图案化线路层上。
8.如权利要求6所述的封装结构,其中该表面处理层包括一镍层、一金层、一银层或一镍钯金层。
9.如权利要求6所述的封装结构,其中该芯片通过打线接合或覆晶接合技术与该图案化线路层电连接。
10.如权利要求6所述的封装结构,其中该图案化线路层的该下表面与该封装胶体的一底面实质上齐平。
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JP (1) | JP5442777B2 (zh) |
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Cited By (4)
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CN106783631A (zh) * | 2016-12-22 | 2017-05-31 | 深圳中科四合科技有限公司 | 一种二极管的封装方法及二极管 |
CN106783632A (zh) * | 2016-12-22 | 2017-05-31 | 深圳中科四合科技有限公司 | 一种三极管的封装方法及三极管 |
WO2018113746A1 (zh) * | 2016-12-22 | 2018-06-28 | 深圳中科四合科技有限公司 | 一种分立器件的封装方法及分立器件 |
CN108807325A (zh) * | 2017-05-04 | 2018-11-13 | 无锡天芯互联科技有限公司 | 一种新型的芯片封装结构及其制作方法 |
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TWI533380B (zh) * | 2011-05-03 | 2016-05-11 | 旭德科技股份有限公司 | 封裝結構及其製作方法 |
US9892952B2 (en) | 2014-07-25 | 2018-02-13 | Semiconductor Components Industries, Llc | Wafer level flat no-lead semiconductor packages and methods of manufacture |
DE102015114662A1 (de) * | 2015-09-02 | 2017-03-02 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Halbleiter-Bauteils, optoelektronisches Halbleiter-Bauteil, Temporärer Träger |
CN107146774A (zh) * | 2017-04-19 | 2017-09-08 | 深圳市环基实业有限公司 | 一种ic封装用载板及其封装工艺 |
CN113973431B (zh) * | 2020-07-23 | 2023-08-18 | 宏启胜精密电子(秦皇岛)有限公司 | 电路板及其制作方法 |
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Also Published As
Publication number | Publication date |
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TWI533380B (zh) | 2016-05-11 |
JP2012235083A (ja) | 2012-11-29 |
US8893379B2 (en) | 2014-11-25 |
JP5442777B2 (ja) | 2014-03-12 |
TW201246411A (en) | 2012-11-16 |
CN102768960B (zh) | 2014-12-31 |
US20120279772A1 (en) | 2012-11-08 |
US8420951B2 (en) | 2013-04-16 |
US20130095615A1 (en) | 2013-04-18 |
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