CN102760700A - 形成自对准接触物的方法及具有自对准接触物的集成电路 - Google Patents

形成自对准接触物的方法及具有自对准接触物的集成电路 Download PDF

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CN102760700A
CN102760700A CN2011101654112A CN201110165411A CN102760700A CN 102760700 A CN102760700 A CN 102760700A CN 2011101654112 A CN2011101654112 A CN 2011101654112A CN 201110165411 A CN201110165411 A CN 201110165411A CN 102760700 A CN102760700 A CN 102760700A
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何家铭
陈逸男
刘献文
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Nanya Technology Corp
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Abstract

一种形成自对准接触物的方法，包括：提供基板，其上具有晶体管，其中该晶体管包括罩幕层及形成于该罩幕层相对侧的一对绝缘间隔物；在该基板之上形成介电层，并覆盖该晶体管；移除该介电层的部份，以露出该晶体管的顶部；在该介电层与该晶体管的该顶部上顺应地形成阻障层；蚀刻该阻障层，在该晶体管的该一对绝缘间隔物中的一个上部边角处留下保护阻障物；施行蚀刻程序，将该保护阻障物与该罩幕层用做蚀刻罩幕，进而形成露出该晶体管的源极/汲极区的自对准接触开口及由该保护阻障物所覆盖的介电间隔物；以及在该自对准接触开口内形成导电层以接触该晶体管该源极/汲极区。

Description

形成自对准接触物的方法及具有自对准接触物的集成电路
技术领域
本发明涉及半导体的制作，且特别涉及一种形成自对准接触物的方法。
背景技术
随着特征尺寸的缩减及芯片上的装置密度(device density)的增加，用于半导体装置的可靠接触结构的制作越显困难。举例来说，随着装置密度的增加，接触结构的深宽比(即深度与宽度的比例)也随之增加。因此，在施行接触蚀刻至一既定深度时很难不使用横向的过度蚀刻(lateral overetching)。
为了在较高密度下较为可靠地制作较小的半导体装置结构，需要使用自对准接触物(self-aligned contacts)。自对准接触物不仅改善了接触物的物理特性，且改善了电性特性。自对准接触物使用了其结构的材料特性而避免或降低了部份制程错误的发生。
已知的形成自对准接触物的方法之一包括：先提供其上具有至少两金氧半导体装置(MOS devices)的基板，并接着在此两金氧半导体装置之上形成如氧化硅的绝缘层。这些金氧半导体装置分别包括导电闸(conductivegate)及位于此导电闸的数个侧壁上的间隔物(spacer)。此两金氧半导体装置具有位于此两金氧半导体装置的导电闸间的共享源极/汲极区。经过图案化上述绝缘层而形成自对准接触开口以露出此共享源极/汲极区。接着在此自对准接触开口内形成导电层从而形成自对准接触物。
然而，随着这些金氧半导体装置的特征尺寸的降低，介于相邻金氧半导体装置之间的间距(pitch)也随着缩减以增加装置密度，进而使得为此自对准接触开口所露出金氧半导体装置的间隔物会在形成自对准接触开口时被部份移除，因而可能会露出导电闸。在自对准接触开口形成后的露出导电闸情形为不期望的，这可能在接触开口内形成导电层之后在导电闸与自对准接触物之间产生短路现象。
发明内容
因此，需要一种较佳的形成自对准接触物的方法及具有自对准接触物的集成电路以解决上述问题。
依据一实施例，本发明提供了一种形成自对准接触物的方法，包括：
提供基板，该基板上具有晶体管，其中该晶体管包括罩幕层及形成于该罩幕层相对侧的一对绝缘间隔物；在该基板之上形成介电层，并覆盖该晶体管；移除该介电层的部份，以露出该晶体管的顶部；在该介电层与该晶体管的该顶部之上形成阻障层；蚀刻该阻障层，于该晶体管的该一对绝缘间隔物中的一个上部边角处留下保护阻障物；施行蚀刻程序，采用该保护阻障物与该罩幕层做为蚀刻罩幕，进而形成露出该晶体管的源极/汲极区的自对准接触开口以及由该保护阻障物所覆盖的介电间隔物；以及在该自对准接触开口内形成导电层以接触该晶体管的该源极/汲极区。
依据一实施例，本发明提供了一种具有自对准接触物的集成电路，包括：
基板，其上具有晶体管，其中该晶体管包括罩幕层以及形成于该罩幕层相对侧的一对绝缘间隔物；介电间隔物，部份地覆盖至少该晶体管的该一对绝缘间隔物中的一个；保护阻障物，位于该介电间隔物之上；以及导电层，形成于该罩幕层、该保护阻障物、该介电间隔物、该绝缘间隔物及该介电间隔物之上，以做为接触该晶体管的源极/汲极区的自对准接触物。
为让本发明之上述目的、特征及优点能更明显易懂，下文特举较佳实施例，并配合所附的图式，作详细说明如下。
附图说明
图1-6为一系列剖面图，显示了依据本发明的一实施例的形成自对准接触物的方法；以及
图7为一剖面图，显示了依据本发明一实施例的具有数个自对准接触物的集成电路。
主要组件符号说明
100～基板；            102～闸介电层；
104～闸电极；          106～罩幕层；
108～闸结构；          110～绝缘间隔物；
112～源极/汲极区；     114～介电层；
114a～介电间隔物；     115～蚀刻程序；
116～阻障层；          116a～保护阻障物；
118～蚀刻程序；        120～图案化罩幕层；
122～开口；            124～蚀刻程序；
126～自对准接触开口；  128～导电层；
T～晶体管；            D～距离；
P～间距。
具体实施方式
图1-6显示了依据本发明的一实施例的形成自对准接触物的方法。
请参照图1，首先提供具有两晶体管T形成于其上的基板100。此基板100可为例如P型半导体基板的基板，而每一晶体管T分别包括形成于半导体基板100上的闸结构108以及形成于邻近每一晶体管T的对称侧的半导体基板100内的一对源极/汲极区112。在此实施例中，此两晶体管T共享一个源极/汲极区112，而该源极/汲极区112可为例如形成于基板100内的n型掺杂区。该晶体管T的闸结构108分别包括依序形成于基板100上的闸介电层102、闸电极104与罩幕层106，及形成于闸结构108的相对侧上的一对绝缘间隔物110。闸介电层102例如为二氧化硅层。闸电极104可包括例如经掺杂多晶硅、金属或其组合的材料。罩幕层106可包括例如氮化硅的材料，而绝缘间隔物110可包括如氮化硅的材料。
请参照图2，接着在基板100之上坦覆地形成介电层114以覆盖这些晶体管T。介电层114可包括例如由四乙氧基硅烷(TEOS)所形成的二氧化硅、硼磷硅酸玻璃(BPSG)或旋涂介电材料(SOG)，因此可由例如化学气相沉积(CVD)或旋转涂布等方法所形成。因此，介电层114可具有平坦顶面。接着，针对介电层114施行例如干蚀刻的蚀刻程序115，以部分地移除介电层114的一部分直到部分地露出晶体管T的顶部，如图3所示。
请参照图3，介电层114的厚度经过减低后，介电层114的顶面距晶体管T的闸结构108的顶面的距离D约为2-15奈米。接着，顺应地在介电层114及晶体管T的露出表面上形成阻障层116，以覆盖绝缘间隔物110与罩幕层106的露出部。此阻障层116由例如氮化硅(SiN)或氮氧化硅(SiON)等材料所形成且具有约2-10奈米的厚度，而上述距离D不小于阻障层116的厚度。接着，施行例如干蚀刻程序的蚀刻程序118以回蚀刻(etch back)阻障层116，进而形成保护阻障物116a邻近于每一绝缘间隔物110的上部边角处并再次露出了介电层114的顶面，如图4所示。
请参照图4，接着在基板100上形成在其内部包括开口122的图案化罩幕层120，，其部分地覆盖了这些晶体管T与介电层114。此开口122部分地露出了介于两晶体管T之间的区域以及此区域内的介电层114。在本实施例中，露出了邻近每一晶体管T的绝缘间隔物110的保护阻障物116a。接着，施行例如干蚀刻程序的蚀刻程序124，并将罩幕层120用作蚀刻罩幕以完全地移除由开口122所露出的介电层114。在一实施例中，蚀刻程序124包括过度蚀刻(over etching)步骤以确保由开口122所露出的介电层114可完全被移除以及露出其下方的源极/汲极区112为露出的。上述图案化罩幕层120可包括阻剂材料。
请参照图5，在蚀刻程序124之后移除此图案化罩幕层120，因而留下位于两晶体管T之间的自对准接触开口126，而此自对准接触开口126露出了由此两晶体管T所共享的源极/汲极区112。在本实施例中，由于保护阻障物116a形成于邻近自对准接触开口126的绝缘间隔物110的上部边角，因而在蚀刻程序124中形成了由介电层114的一部分所组成的介电间隔物114a，如图4所示。此外，在形成自对准接触开口126时，两晶体管T的绝缘间隔物110由介电间隔物114a与保护阻障物116a所保护，因而在形成自对准接触开口126时不会遭受到蚀刻。这样，由自对准接触开口126所露出的此两晶体管T的绝缘间隔物110a基于介电间隔物114a与保护阻障物116a的保护而在形成自对准接触开口126时不会受到蚀刻，故两晶体管T之间的间距P可更为缩减，并可避免后续形成的自对准接触物与晶体管T之间的短路情形。
请参照图6，接着在基板100上坦覆地形成例如铝的一层导电材料，以覆盖介电层114、介电间隔物114a、晶体管T与保护阻障物116a并填满此自对准接触开口126。接着，图案化此层导电材料以形成导电层128，其部分地覆盖了邻近自对准接触开口126的晶体管T并填满此自对准接触开口126(参见图5)，以作为接触这些晶体管T的源极/汲极区112的自对准接触物。
如图6所示，本发明的一实施例中提供了一种具有自对准导电接触物的集成电路，包括：
基板(例如基板200)，其上具有晶体管(例如晶体管T中的一个)，其中该晶体管包括罩幕层(例如罩幕层106)以及形成于该罩幕层对称侧上的一对绝缘间隔物(例如绝缘间隔物110)；一介电间隔物(例如介电间隔物114a)，部份地覆盖至少该晶体管的该一对绝缘间隔物中的一个；保护阻障物(例如保护阻障物116a)，位于该介电间隔物之上；以及导电层(例如导电层128)，形成于该罩幕层、该保护阻障物、该介电间隔物、该绝缘间隔物及该介电间隔物之上，以作为用于接触该晶体管的源极/汲极区的自对准接触物。
请参照图7，显示了依据本发明一实施例的具有数个自对准接触物的集成电路。
如图7所示，在基板100上形成有相似于图6所示的自对准接触物128a的数个自对准接触物128a，而每一自对准接触物128a位于每一源极/汲极区112上并与其实体接触。这些自对准接触物128的制作相似于如图1-6所示实施的情形，但同时在介电层114中形成用于露出每一源极/汲极区112的数个自对准接触开口126，且可在每一自对准接触开口126中依照如图6-7所示程序而形成自对准接触物128a。在本实施例中，在晶体管T的两侧留下有相邻的保护阻障物116a与介电间隔物114a，而由自对准接触开口126所露出的绝缘间隔物110由此保护阻障物116a与此介电间隔物114a所保护，因此可进一步缩减相邻晶体管T之间的间距，且可避免晶体管T与自对准接触物128a间的短路情形。
虽然本发明已公开了上述较佳实施例，但本发明并不限于此，本领域技术人员应当理解，在不脱离本发明精神和范围内，可对本发明作更动与润饰，因此本发明的保护范围应当以权利要求书所界定的范围为准。

Claims (14)

1.一种形成自对准接触物的方法，包括：
提供基板，所述基板上具有晶体管，其中所述晶体管包括罩幕层及形成于所述罩幕层的相对侧的一对绝缘间隔物；
在所述基板上形成介电层，并覆盖所述晶体管；
移除所述介电层的部份，以露出所述晶体管的顶部；
在所述介电层与所述晶体管的所述顶部上形成阻障层；
蚀刻所述阻障层，在所述晶体管的所述一对绝缘间隔物中的一个上部边角处留下保护阻障物；
施行蚀刻程序，将所述保护阻障物与所述罩幕层用做蚀刻罩幕，进而形成露出所述晶体管的源极/汲极区的自对准接触开口以及由所述保护阻障物所覆盖的介电间隔物；以及
在所述自对准接触开口内形成导电层以接触所述晶体管的所述源极/汲极区。
2.根据权利要求1所述的形成自对准接触物的方法，其中所述罩幕层与所述一对绝缘间隔物包括氮化硅。
3.根据权利要求1或2所述的形成自对准接触物的方法，其中所述阻障层包括氮化硅或氮氧化硅。
4.根据权利要求1或2所述的形成自对准接触物的方法，其中所述介电层包括二氧化硅、硼磷硅酸玻璃或旋涂介电材料。
5.根据权利要求1或2所述的形成自对准接触物的方法，其中所述阻障层具有约2-10奈米的厚度。
6.根据权利要求1或2所述的形成自对准接触物的方法，其中所述蚀刻程序包括过度蚀刻步骤。
7.根据权利要求1或2所述的形成自对准接触物的方法，其中所述导电层包括铝。
8.一种具有自对准接触物的集成电路，包括：
基板，所述基板上具有晶体管，所述晶体管包括罩幕层以及形成于所述罩幕层相对侧的一对绝缘间隔物；
介电间隔物，部份地覆盖至少所述晶体管的所述一对绝缘间隔物中的一个；
保护阻障物，位于所述介电间隔物上；以及
导电层，形成于所述罩幕层、所述保护阻障物、所述介电间隔物、所述绝缘间隔物及所述介电间隔物上，以做为接触所述晶体管的源极/汲极区的自对准接触物。
9.根据权利要求8所述的具有自对准接触物的集成电路，其中所述罩幕层与所述一对绝缘间隔物包括氮化硅。
10.根据权利要求8或9所述的具有自对准接触物的集成电路，其中所述保护阻障物包括氮化硅或氮氧化硅。
11.根据权利要求8或9所述的具有自对准接触物的集成电路，其中所述介电间隔物包括二氧化硅、硼磷硅酸玻璃或旋涂介电材料。
12.根据权利要求8或9所述的具有自对准接触物的集成电路，其中所述导电层包括铝。
13.根据权利要求8或9所述的具有自对准接触物的集成电路，还包括形成在所述基板上的另一介电间隔物，所述另一介电间隔物部份地覆盖另一绝缘间隔物。
14.根据权利要求13所述的具有自对准接触物的集成电路，还包括另一保护阻障层，形成于部份地覆盖所述另一绝缘间隔物的所述介电间隔物上。
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