TWI434353B - 形成自對準接觸物之方法及具有自對準接觸物之積體電路 - Google Patents

形成自對準接觸物之方法及具有自對準接觸物之積體電路 Download PDF

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TWI434353B
TWI434353B TW100115044A TW100115044A TWI434353B TW I434353 B TWI434353 B TW I434353B TW 100115044 A TW100115044 A TW 100115044A TW 100115044 A TW100115044 A TW 100115044A TW I434353 B TWI434353 B TW I434353B
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aligned contact
layer
transistor
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TW201243956A (en
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Jar Ming Ho
Yi Nan Chen
Hsien Wen Liu
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Nanya Technology Corp
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Description

形成自對準接觸物之方法及具有自對準接觸物之積體 電路
本發明係關於半導體的製作，且特別是關於一種形成自對準接觸物之方法。
隨著特徵尺寸的縮減及晶片上之裝置密度(device density)的增加，用於半導體裝置的可靠接觸結構的製作便越顯困難。舉例來說，隨著裝置密度的增加，接觸結構的深寬比(即深度與寬度的比例)亦隨之增加。因此，於施行接觸蝕刻至一既定深度時很難不使用橫向的過度蝕刻(lateral over etching)。
為了於較高密度下較為可靠地製作較小的半導體裝置結構，便需要自對準接觸物(self-aligned contacts)的使用。自對準接觸物不僅改善了接觸物的物理特性，且改善了電性特性。自對準接觸物使用了其結構之材料特性而避免或降低了部份製程錯誤的發生。
習知形成自對準接觸物的方法之一包括了先提供其上具有至少兩金氧半導體裝置(MOS devices)之一基板，並接著形成如氧化矽之一絕緣層於此兩金氧半導體裝置之上。此些金氧半導體裝置分別包括一導電閘(conductive gate)及位於此導電閘的數個側壁上之一間隔物(spacer)。此兩金氧半導體裝置具有位於此兩金氧半導體裝置之導電閘間之一共用源極/汲極區。經過圖案化上述絕緣層而形成一自對準 接觸開口以露出此共用源極/汲極區。接著於此自對準接觸開口內形成一導電層而形成一自對準接觸物。
然而，隨著此些金氧半導體裝置的特徵尺寸的降低，介於相鄰金氧半導體裝置之間的間距(pitch)亦隨著縮減以增加裝置密度，進而使得為此自對準接觸開口所露出金氧半導體裝置的間隔物會於形成自對準接觸開口時被部份移除，因而可能會露出導電閘。於自對準接觸開口形成後的導電閘露出情形為不期望的，如此可能於接觸開口內形成導電層之後於導電閘與自對準接觸物之間產生短路現象。
因此，便需要一種較佳之形成自對準接觸物之方法及具有自對準接觸物之積體電路以解決上述問題。
依據一實施例，本發明提供了一種形成自對準接觸物之方法，包括：提供一基板，該基板上具有一電晶體，其中該電晶體包括一罩幕層及形成於該罩幕層之相對側之一對絕緣間隔物；形成一介電層於該基板之上，並覆蓋該電晶體；移除部份該介電層，以露出該電晶體之一頂部；形成一阻障層於該介電層與該電晶體之該頂部之上；蝕刻該阻障層，於該電晶體之該些絕緣間隔物之一上部邊角處留下一保護阻障物；施行一蝕刻程序，採用該保護阻障物與該罩幕層做為一蝕刻罩幕，進而形成露出該電晶體之一源極/汲極區之一自對準接觸開口及為該保護阻障物所覆蓋之一介電間隔 物；以及形成一導電層於該自對準接觸開口內以接觸該電晶體之該源極/汲極區。
依據一實施例，本發明提供了一種具有自對準接觸物之積體電路，包括：一基板，其上具有一電晶體，其中該電晶體包括一罩幕層以及形成於該罩幕層之相對側之一對絕緣間隔物；一介電間隔物，部份覆蓋至少該電晶體之該些絕緣間隔物之一；一保護阻障物，位於該介電間隔物之上；以及一導電層，形成於該罩幕層、該保護阻障物、該介電間隔物、該絕緣間隔物及該介電間隔物之上，以做為接觸該電晶體之一源極/汲極區之一自對準接觸物。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下：
第1-6圖顯示了依據本發明之一實施例之一種形成自對準接觸物之方法。
請參照第1圖，首先提供具有兩電晶體T形成於其上之一基板100。此基板100可為如P型半導體基板之一基板，而每一電晶體T分別包括形成於半導體基板100上之一閘結構108以及形成於鄰近每一電晶體T的對稱側的半導體基板100內之一對源極/汲極區112。於此實施例中， 此兩電晶體T共用了一源極汲極區112，而此些源極/汲極區112可為如形成於基板100內之n型摻雜區。此些電晶體T之閘結構108分別包括依序形成於基板100上之一閘介電層102、一閘電極104與一罩幕層106，及形成於閘結構108的相對側上之一對絕緣間隔物110。閘介電層102例如為二氧化矽層。閘電極104可包括如經摻雜多晶矽、金屬或其組合之材料。罩幕層106可包括如氮化矽之材料，而絕緣間隔物110可包括如氮化矽之材料。
請參照第2圖，接著於基板100之上坦覆地形成一介電層114以覆蓋此些電晶體T。介電層114可包括如由四乙氧基矽烷(TEOS)所形成之二氧化矽、硼磷矽酸玻璃(BPSG)或旋塗介電材料(SOG)，因此可由如化學氣相沈積(CVD)或旋轉塗佈等方法所形成。因此，介電層114可具有一平坦頂面。接著，針對介電層114施行如乾蝕刻之一蝕刻程序115，以部分移除介電層114之一部直到部分露出電晶體T的一頂部，如第3圖所示。
請參照第3圖，介電層114之厚度經過減低後，介電層114的頂面距電晶體T的閘結構108之頂面的距離D則約為2-15奈米。接著，順應地形成一阻障層116於介電層114及電晶體T之露出表面之上，以覆蓋絕緣間隔物110與罩幕層106之露出部。此阻障層116係由如氮化矽(SiN)或氮氧化矽(SiON)等材料所形成且具有約2-10奈米之一厚度，而上述距離D不少於阻障層116之厚度。接著，施行如乾蝕刻程序之一蝕刻程序118以回蝕刻(etch back)阻障 層116，進而形成一保護阻障物116a鄰近於每一絕緣間隔物110之一上部邊角處並再次露出了介電層114的頂面，如第4圖所示。
請參照第4圖，接著於基板100之上形成具有一開口122於其內之一圖案化罩幕層120，其部分覆蓋了此些電晶體T與介電層114。此開口122部分露出了介於兩電晶體T間之一區域及此區域內之介電層114。於本實施例中，露出了鄰近於每一電晶體T之一絕緣間隔物110的一保護阻障物116a。接著，施行如乾蝕刻程序之一蝕刻程序124，並採用了罩幕層120作為蝕刻罩幕以完全地移除為開口122所露出之介電層114。於一實施例中，蝕刻程序124包括一過度蝕刻(over etching)步驟以確保為開口122所露出之介電層114可完全被移除以及露出其下方之源極/汲極區112為露出的。上述之圖案化罩幕層120可包括阻劑材料。
請參照第5圖，於蝕刻程序124之後移除此圖案化罩幕層120，因而留下位於兩電晶體T間之一自對準接觸開口126，而此自對準接觸開口126露出了為此兩電晶體T所共用之一源極/汲極區112。於本實施例中，由於保護阻障物116a係形成於鄰近自對準接觸開口126之絕緣間隔物110的上部邊角，因而於蝕刻程序124中形成了由介電層114之一部所組成之一介電間隔物114a，如第4圖所示。此外，於形成自對準接觸開口126時，兩電晶體T之絕緣間隔物110係為介電間隔物114a與保護阻障物116a所保護，因而於形成自對準接觸開口126時不會遭受到蝕刻。 如此，為自對準接觸開口126所露出之此兩電晶體T的絕緣間隔物110基於介電間隔物114a與保護阻障物116a的保護而於形成自對準接觸開口126時不會受到蝕刻，故兩電晶體T之間的間距P可更為縮減，並可避免後續形成之自對準接觸物與電晶體T之間的短路情形。
請參照第6圖，接著於基板100上坦覆地形成如鋁之一層導電材料，以覆蓋介電層114、介電間隔物114a、電晶體T與保護阻障物116a並填滿此自對準接觸開口126。接著，圖案化此層導電材料以形成一導電層128，其部分覆蓋了鄰近於自對準接觸開口126之電晶體T並填滿此自對準接觸開口126(見於第5圖)，以做為接觸此些電晶體T之源極/汲極區112之一自對準接觸物。
如第6圖所示，本發明之一實施例中提供了一種具有一自對準導電接觸物之一積體電路，包括：一基板(例如基板200)，其上具有一電晶體(例如電晶體T之一)，其中該電晶體包括一罩幕層(例如罩幕層106)以及一對絕緣間隔物(例如絕緣間隔物110)形成於該罩幕層之對稱側上；一介電間隔物(例如介電間隔物114a)，部份覆蓋至少該電晶體之該些絕緣間隔物之一；一保護阻障物(例如保護阻障物116a)，位於該介電間隔物之上；以及一導電層(例如導電層128)，形成於該罩幕層、該保護阻障物、該介電間隔物、該絕緣間隔物及該介電間隔物之上，以做為用於接觸該電晶體之一源極/汲極區之一自對準接觸物。
請參照第7圖，顯示了依據本發明一實施例之具有數 個自對準接觸物之一積體電路。
如第7圖所示，於基板100上形成有相似於如第6圖所示之自對準接觸物128之數個自對準接觸物128，而每一自對準接觸物128係位於每一源極/汲極區112之上並實體接觸之。此些自對準接觸物128的製作相似於如第1-6圖所示實施情形，但係同時於介電層114中形成用於露出每一源極/汲極區112之數個自對準接觸開口126，且可於每一自對準接觸開口126中依照如第6-7圖所示程序而形成一自對準接觸物128。於本實施例中，於電晶體T的兩側留下有相鄰之保護阻障物116a與介電間隔物114a，而為自對準接觸開口126所露出之絕緣間隔物110係為此保護阻障物116a與此介電間隔物114a所保護，因此可更縮減相鄰電晶體T間之一間距，且可避免電晶體T與自對準接觸物128a間的短路情形。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此項技藝者，在不脫離本發明之精神和範圍內，當可作更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧基板
102‧‧‧閘介電層
104‧‧‧閘電極
106‧‧‧罩幕層
108‧‧‧閘結構
110‧‧‧絕緣間隔物
112‧‧‧源極/汲極區
114‧‧‧介電層
114a‧‧‧介電間隔物
115‧‧‧蝕刻程序
116‧‧‧阻障層
116a‧‧‧保護阻障物
118‧‧‧蝕刻程序
120‧‧‧圖案化罩幕層
122‧‧‧開口
124‧‧‧蝕刻程序
126‧‧‧自對準接觸開口
128‧‧‧導電層
T‧‧‧電晶體
D‧‧‧距離
P‧‧‧間距
第1-6圖為一系列剖面圖，顯示了依據本發明之一實施例之一種形成自對準接觸物之方法；以及第7圖為一剖面圖，顯示了依據本發明一實施例之具有數個自對準接觸物之一積體電路。
100‧‧‧基板
102‧‧‧閘介電層
104‧‧‧閘電極
106‧‧‧罩幕層
108‧‧‧閘結構
110‧‧‧絕緣間隔物
112‧‧‧源極/汲極區
114‧‧‧介電層
114a‧‧‧介電間隔物
116a‧‧‧保護阻障物
126‧‧‧自對準接觸開口
128‧‧‧導電層

Claims (13)

  1. 一種形成自對準接觸物之方法，包括：提供一基板，該基板上具有一電晶體，其中該電晶體包括一罩幕層及形成於該罩幕層之相對側之一對絕緣間隔物；形成一介電層於該基板之上，並覆蓋該電晶體；移除部份該介電層，以露出該電晶體之一頂部；形成一阻障層於該介電層與該電晶體之該頂部之上；蝕刻該阻障層，於該電晶體之該些絕緣間隔物之一上部邊角處留下一保護阻障物；施行一蝕刻程序，採用該保護阻障物與該罩幕層做為一蝕刻罩幕，完全地移除該介電層之露出部分，進而形成露出該電晶體之一源極/汲極區之一自對準接觸開口且留下該介電層之一剩餘部，以作為該保護阻障物所覆蓋之一介電間隔物；以及形成一導電層於該自對準接觸開口內以接觸該電晶體之該源極/汲極區。
  2. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該罩幕層與該些絕緣間隔物包括氮化矽。
  3. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該阻障層包括氮化矽或氮氧化矽。
  4. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該介電層包括包括二氧化矽、硼磷矽酸玻璃或旋塗介電材料。
  5. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該阻障層具有約2-10奈米之厚度。
  6. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該蝕刻程序包括一過度蝕刻步驟。
  7. 如申請專利範圍第1項所述之形成自對準接觸物之方法，其中該導電層包括鋁。
  8. 一種具有自對準接觸物之積體電路，包括：一基板，其上具有一電晶體，該電晶體包括一罩幕層以及形成於該罩幕層之相對側之一對絕緣間隔物；一介電間隔物，部份覆蓋至少該電晶體之該些絕緣間隔物之一，其中該介電間隔物包括二氧化矽、硼磷矽酸玻璃或旋塗介電材料；一保護阻障物，位於該介電間隔物之上；以及一導電層，形成於該罩幕層、該保護阻障物、該介電間隔物、該絕緣間隔物及該介電間隔物之上，以做為接觸該電晶體之一源極/汲極區之一自對準接觸物。
  9. 如申請專利範圍第8項所述之具有自對準接觸物之積體電路，其中該罩幕層與該些絕緣間隔物包括氮化矽。
  10. 如申請專利範圍第8項所述之具有自對準接觸物之積體電路，其中該保護阻障物包括氮化矽或氮氧化矽。
  11. 如申請專利範圍第8項所述之具有自對準接觸物之積體電路，其中該導電層包括鋁。
  12. 如申請專利範圍第8項所述之具有自對準接觸物之積體電路，更包括另一介電間隔物形成於該基板上，部份 覆蓋另一絕緣間隔物。
  13. 如申請專利範圍第12項所述之具有自對準接觸物之積體電路，更包括另一保護阻障層，形成於部份覆蓋該另一絕緣間隔物之該介電間隔物之上。
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