CN102694013B - 采用耗尽模式GaN基FET的串叠电路 - Google Patents
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Abstract
一种电路包括输入漏极节点、输入源极节点和输入栅极节点。该电路还包括III族氮化物耗尽模式FET,其具有源极、漏极和栅极,其中,耗尽模式FET的栅极联接到使耗尽模式FET保持在其导通状态的电势。另外,该电路还包括增强模式FET,其具有源极、漏极和栅极。耗尽模式FET的源极串联联接到增强模式FET的漏极。耗尽模式FET的漏极用作输入漏极节点,增强模式FET的源极用作输入源极节点,并且增强模式FET的栅极用作输入栅极节点。
Description
本申请是申请日为2008年3月20日、名称为“采用耗尽模式GaN基FET的串叠电路”的第200880009064.0号发明专利申请的分案申请。
相关申请的交叉引用
该申请涉及与其同日提交的序列号为No.11/725,823且名为“Termination and Contact Structures For A High Voltage GaN-BasedHeterojunction Transistor”的共同待决美国专利申请,并且通过引用将其内容合并于此。
该申请还涉及与其同日提交的序列号为No.11/725,820且名为“High-Voltage GaN-Based Heterojunction Transistor Structure andMethod ofForming Same”的共同待决美国专利申请,并且通过引用将其内容合并于此。
技术领域
本发明大体上涉及诸如GaN基FET的III族氮化物化合物半导体FET,更具体来讲,涉及采用耗尽模式GaN基FET并且用作增强模式FET的电路。
背景技术
使用诸如GaN、AlGaN、InGaN、AlGaN、AlInGaN等宽带隙半导体的GaN基FET作为高功率应用的功率器件已经备受关注,这是因为它们的导通电阻比使用Si或GaAs的FET在大小上小一个或者更多数量级,由此可以以更大电流在更高温度下操作并且可以经受高压应用。
在图1中示出了传统的GaN基FET的一个实例。如所示出的,在诸如蓝宝石衬底的半绝缘衬底91上形成异质结结构。该异质结结构包括GaN缓冲层92,例如,未掺杂的GaN层93和未掺杂的AlGaN层94,其中,未掺杂的AlGaN层94通常比未掺杂的GaN层93薄得多。未掺杂的GaN层93用作沟道层。可选的,在未掺杂的AlGaN层94上设置两个n-AlGaN接触层95。源极电极S和漏极电极D布置在它们各自的接触层95上。栅极电极G形成在未掺杂的AlGaN层94上,并且位于源极电极S和漏极电极D之间。如果在源极电极S和漏极电极D与下面的半导体层之间可以建立满意的欧姆接触,则接触层95可以不是必需的。
通过在具有大带隙的AlGaN层和具有较窄带隙的GaN层之间的异质结界面上形成量子阱,GaN基FET器件能够将电子迁移率最大化。结果,电荷被捕获在量子阱里。通过未掺杂的GaN层中的二维电子气96来表现所捕获的电子。通过向栅极电极施加电压来控制电流量,栅极电极与半导体肖特基接触,以使得电子沿着源极电极和漏极电极之间的沟道流动。
即使当栅极电压为0时,在沟道中也将产生电子,这是因为形成了从衬底向着器件表面延伸的压电场。因此,GaN基FET用作耗尽模式(即,常导通型)器件。出于多种原因,期望的是提供增强模式(即,常截止型)GaN基FET。例如,当采用耗尽模式FET作为功率源极的开关器件时,必须连续向栅极电极施加至少等于栅极阈值的偏置电压,以保持开关处于截止状态。这样的布置会消耗过多的功率。另一方面,如果采用增强模式FET,则即使在没有施加电压的情况下也可以保持开关处于截止状态,由此消耗的功率较少。遗憾的是,虽然已经尝试制造GaN基增强模式FET,但是通常不令人满意,这是由于存在诸如导通状态电导差且击穿电压差的问题。
发明内容
根据本发明,一种电路包括输入漏极节点、输入源极节点和输入栅极节点。该电路还包括具有源极、漏极和栅极的III族氮化物耗尽模式FET,其中,耗尽模式FET的栅极联接到使耗尽模式FET保持在其导通状态的电势。另外,该电路还包括具有源极、漏极和栅极的增强模式FET。耗尽模式FET的源极串联联接到增强模式FET的漏极。耗尽模式FET的漏极用作输入漏极节点,增强模式FET的源极用作输入源极节点,并且增强模式FET的栅极用作输入栅极节点。
根据本发明的一个方面,III族氮化物可以包括GaN。
根据本发明的另一个方面,耗尽模式FET可以是额定电压大于约100V的高压FET。
根据本发明的另一个方面,III族氮化物耗尽模式FET可以包括:衬底;第一有源层,所述第一有源层设置在所述衬底的上方;以及第二有源层,所述第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层高的带隙,使得在所述第一有源层和所述第二有源层之间产生二维电子气层。在所述第二有源层上设置快闪层,并且在所述快闪层上设置源极接触、栅极接触和漏极接触。
根据本发明的另一个方面,所述第一有源层可以包含GaN,并且所述第二有源层可以包含III族氮化物半导体材料。
根据本发明的一个方面,所述第二有源层可以包含AlxGa1-xN,其中0<X<1。
根据本发明的另一个方面,所述第二有源层可以选自由AlGaN、AlInN和AlInGaN组成的组。
根据本发明的另一个方面,在所述衬底和所述第一有源层之间还可以设置成核层。
根据本发明的另一个方面,所述快闪层可以包含金属Al。
根据本发明的另一个方面,所述快闪层可以包含金属Ga。
根据本发明的另一个方面,所述快闪层可以是形成自然氧化物层的经退火的快闪层。
根据本发明的另一个方面,所述第二有源层和所述快闪层可以包括形成在其内的第一凹进部和第二凹进部,并且所述源极接触和所述漏极接触可以分别设置在所述第一凹进部和所述第二凹进部中。
附图说明
图1示出传统GaN基FET的一个实例。
图2示出根据本发明构建的电路的一个实例。
图3和图4示出图2中所示电路的电流-电压特性曲线。
图5示出图2中所示电路的电流与栅源电压的对比。
图6示出图2中所示电路中可以采用的氮化镓基FET的一个实例。
图7和图8示出图2中所示电路中可以采用的氮化镓(GaN)FET的可供选择的实例。
具体实施方式
本发明的发明者已经认识到,使用具有类似操作特性的GaN基耗尽模式结构来替代制造半导体GaN基的增强模式FET半导体结构,可以容易实现这种结构的理想操作特性。即,如以下所详述的,本发明将GaN基耗尽模式FET与一个或多个其它组件相结合,使得所得器件用作增强模式FET。例如,在本发明的一个具体实施例中,将GaN基耗尽模式FET与增强模式FET串联布置,从而提供了在其它方面具有GaN基耗尽模式FET的特性的增强模式器件。
可以采用例如共源极、共栅极、共漏极、源极跟随器等的各种已知方式来连接单独的FET器件,以提供所期望的不同操作特性,从而符合特定目的的要求。也可以将两个这样的器件连接在一起,以提供只用一个器件不能得到的多种可能的输入和输出特性。这样的一个实例是通常使用的“串叠”构造,在该构造中,第一级器件以共源极构造连接,并且其输出转到第二器件的输入,第二器件以共栅极构造连接。所得结构是具有高输入阻抗、低噪声且高增益的器件。
图2示出根据本发明构建的电路100的一个实例。GaN基耗尽模式FET 110的源极连接到增强模式FET 120的漏极。增强模式FET 120可以是,例如,通用的硅基或者GaAs基器件。耗尽模式FET 100的栅极接地,使得FET 110一直导通。在图2的实例中,通过将FET 110的栅极接地来保持FET 120的导通状态。增强模式FET 120的源极接地。耗尽模式FET 110的漏极用作电路100的漏极D。增强模式FET 120的源极用作电路100的源极S。同样,增强模式FET 120的栅极用作电路100的栅极G。
可以参照图3和图4中所示的电流-电压特性曲线来说明电路100的操作。只是出于示例的目的而不是对本发明的限制,FET 110和120都是n-型,但是可供选择的,也可以使用p-型器件。图3示出增强模式FET 120的电流-栅源电压。在该实例中示出FET 120的夹断电压是5V。图4示出耗尽模式FET 110的电流与栅源电压的对比。在该实例中示出耗尽模式FET 110的夹断电压是-6V。
图4示出的是,如果栅源电压VGS是0V或更大,则耗尽模式FET110将保持导通状态。由于在该实例中示出FET 110的栅极接地,因此耗尽模式FET一直导通。图3示出的是,如果施加5V或更大的栅源电压VGS,则增强模式FET 120一直导通。由于电流需要沿着从耗尽模式FET 110的漏极D向增强模式FET 120的源极S的路径流动,因此通过将栅极电压G变为5V或更大的值,电路将处于其导通状态,由此如同增强模式FET一样作用。以此方式,增强模式FET 120的栅极G将以增强模式FET的方式调节通过电路100的电流,而耗尽模式FET110的阻挡电压提供对整个电路100的阻挡能力。因此,电路100如同600V GaN基增强模式FET一样作用。图5示出了电路100的电流与栅源电压的对比。
在以上所表现的实例中,GaN基耗尽模式FET 110具有600V的额定电压,并且FET 120的额定电压是20V。更一般地,在本发明的一些实施例中,耗尽模式FET是任何合适的高压(例如,高于约100V的电压)FET。电路100的输出电压通常将大约等于耗尽模式FET 110和增强模式FET 120之间的额定电压差。因此,为了将电路100的额定电压最大化,优选地选择尽可能小的增强模式FET 120的额定电压。诸如其额定电流和其导通状态下的漏源电阻的电路100的其余特性将与耗尽模式FET 110的类似。
图6至图8示出电路100中可以采用的耗尽模式FET 110的一些具体实例。当然,本发明不限于这些结构,这些结构只是为了示例的目的而示出。在图6中,耗尽模式FET 10包括衬底12、成核(过渡)层18、GaN缓冲层22、氮化铝镓(AlxGa1-xN;0<x<l)肖特基层24和覆盖层或终止层16。另外,FET 10包括源极接触27、栅极接触28和漏极接触30。
通常使用外延生长工艺来制造FET 10。例如,可以使用反应溅射工艺,在该工艺中,在毗邻衬底设置的金属靶和衬底都处于包括氮和一个或多个掺杂物的气氛中时,从金属靶溢出诸如镓、铝和/或铟的半导体的金属组分。可供选择的,可以采用金属有机化学气相沉积(MOCVD),其中,在将衬底保持在升高的温度,通常在700℃至1100℃左右下的同时,将衬底暴露于包含金属的有机化合物的气氛,以及诸如氨的反应含氮气体和含掺杂物气体中。气体化合物分解,并且在衬底302的表面上形成晶体材料膜的形式的掺杂的半导体。然后将衬底和生长的膜冷却。作为另外可供选择的,可以使用诸如分子束外延(MBE)或原子层外延的其它外延生长方法。可以采用的另外的技术包括,但不限于流量调制有机金属气相外延(FM-OMVPE)、有机金属气相外延(OMVPE)、氢化物外延(HVPE)和物理气相沉积(PVD)。
为了开始生长结构,在衬底12上沉积成核层18。衬底12可以由各种材料形成,所述各种材料包括但不限于蓝宝石或碳化硅(SiC)。成核层18可以是,例如,诸如AlxGa1-xN的富铝层,其中,X在0至1的范围内。成核层18操作用于校正GaN缓冲层22和衬底12之间的晶格不匹配。通常,当一层中的原子之间的间距与相邻层中原子之间的间距不匹配时,产生晶格不匹配。由于晶格不匹配,导致相邻层中的原子之间的结合弱,并且相邻层会断裂、分离或者具有大量的晶体缺陷。因此,通过在衬底12的晶体结构和GaN缓冲层22的晶体结构之间产生界面,成核层18操作用于校正GaN缓冲层22和衬底12之间的晶格不匹配。
在沉积了成核层18之后,在成核层18上沉积GaN缓冲层22,并且在GaN缓冲层22上沉积AlxGa1-xN肖特基层24。作为薄的高迁移率沟道的二维导电沟道26,其将载流子限制在GaN缓冲层22和AlxGa1-xN肖特基层24之间的界面区域。在AlxGa1-xN肖特基层24上沉积覆盖层或终止层16,覆盖层或终止层16用于在FET 10的制造和操作过程中保护AlxGa1-xN肖特基层24以免其发生诸如氧化的表面反应。因为肖特基层24包含铝,所以如果AlxGa1-xN肖特基层24暴露于空气中并且没有以其它方式受保护,则会发生氧化。
在衬底12上生长了外延层18、22和24以及终止层16之后,通过分别在终止层16上沉积源极接触27、栅极接触28和漏极接触30来完成FET 10。接触件27、28和30中的每个是金属接触件。优选地,栅极接触28是诸如,但不限于镍、金的金属材料,并且源极接触27和漏极接触30都是诸如,但不限于钛、金或铝的金属材料。
在本发明的一个实施例中,终止层16是形成在AlxGa1-xN肖特基层24上的InGaN层。InGaN层16用于两个目的,第一个目的是用于提供不包含Al的上层,从而减小氧化。此外,因为诸如InGaAlN的含铝化合物通常需要较高的生长温度来提供足够的均匀度和光滑度,所以通过使用InGaN材料来替代包含铝的材料,可以简化生长工艺。另外,InGaN层24略微降低了表面的势垒,这样可以减少表面电荷的增多并且降低了结构表面上的漏电流。
在本发明的另一个实施例中,终止层16是包含Al金属的快闪层(flash layer)。利用材料的极短猝发来形成快闪层。这样将在结构表面上方形成非常薄(例如,材料的1-2单分子层)但是平的覆盖。该快闪层通常是原位执行的。为了确保形成的是金属Al而不是AlN,不存在当形成AlN时将会存在的反应含氮气体(例如,氨)。可以在高温或低温下形成Al快闪层。在其形成之后,可以接着对Al进行退火,以形成薄的氧化物层。由于Al快闪层非常薄,因此它可以被完全氧化,由此在材料上产生初始的“自然”氧化物,该氧化物随后保护肖特基层24,使其不发生处理过程中通常看到的任何类型的劣化。这可以用作额外的势垒材料,用于降低漏电流并且增大击穿电压,这对于HEMT性能都是重要的。快闪层可以包含其它金属,例如镓或甚至铟,以替代铝。还可以将Ga或In快闪层氧化以在结构上形成均匀的“自然”氧化物。
在本发明的其它实施例中,覆盖层或终止层16可以由其它材料形成,诸如高度Fe掺杂的GaN、Si掺杂的GaN、FeN或SiN。可以是外延、非外延或者甚至无定形的这些层可以用作初始钝化层或者用作额外的势垒材料,用于降低漏电流并且增大击穿电压。例如,向GaN添加Fe导致了可以降低漏电流的材料,这是因为该材料更绝缘并且降低了电子迁移率。
在本发明的其它实施例中,可以在AlxGa1-xN肖特基层24上形成薄AlN层。该层提供了另外的肖特基势垒层,以有助于更有效地调节电荷,由此降低了漏电流并且增大了器件的击穿电压。AlN层还可以用作结构的初始钝化层,这是由于AlN可以容易地被湿法蚀刻,以沉积欧姆接触件。可供选择的,可以氧化AlN层以形成钝化层。
在一些实施例中,终止层16的厚度大致为1至5纳米。因此,电子可以容易地隧穿终止层16。结果,终止层16没有增加栅极接触28和AlxGa1-xN肖特基层24之间的肖特基势垒高度,其中,肖特基势垒高度限定了栅极接触28和AlxGa1-xN肖特基层24的界面上的由电子遭遇的电势能量势垒。另外,终止层16没有影响源极接触27和漏极接触30的形成。
图7示出了FET 10的又一个实施例,在该实施例中,欧姆接触件27和28位于AlxGa1-xN肖特基层24中形成的凹进部中。通过根据传统技术蚀刻AlxGa1-xN肖特基层24来形成凹进部。凹进部可以部分或完全地延伸穿过AlxGa1-xN肖特基层24。例如,在一些情况下,凹进部可以延伸到约5nm至15nm深的深度,由此使得AlxGa1-xN肖特基层24能够保持足够的厚度来产生沟道层26。通过以此方式使接触件凹进,降低了表面的接触电阻和光滑度,从而增大了被沉积用于形成欧姆接触件的金属的渗透性。表面粗糙的增加导致金属更好地迁移到半导体中。对于需要低导通电阻的器件来说,该布置在实现可能最低的导通电阻方面会效果显著。虽然没有示出,但是本发明的该实施例还可以采用诸如以上讨论的覆盖层或终止层。在这种情况下,其中设置有接触件27和28的凹进部也将延伸穿过终止层。
图8示出了FET 10的另一个实施例,在该实施例中,势垒层24由代替AlxGa1-xN的AlInGaN形成。例如,如在GAAS99中由M.AsifKhan等人所著的“Strain Energy B and Engineering in AlGaInN/GaNHeterostructure Field Effect Transistors”中所讨论的,采用了AlxInyGa(1-x-y)N结,其势垒厚度小于50nm且合金组分在x等于0.1至0.2而y等于0.00至0.02的范围内变化。另外,Khan等人陈述的是,基于晶格常数的线性插值,为5的Al/In比率应该几乎与GaN晶格匹配。通过使用AlInGaN,可以与带隙无关地控制张力,由此使得材料的带隙能够关于临界厚度更自由地变化。对于功率器件,在没有过度对材料施加应力和缩短器件寿命的情况下,在沟道中得到最多电荷是至关重要的,其中,随着时间流逝当材料驰豫时会产生器件寿命的缩短。
虽然本文具体示出和描述了各种实施例,但是应该理解的是,在不脱离本发明的精神和意图范围的情况下,本发明的修改形式和变形形式可以被以上教导覆盖并且在所附权利要求的范围内。例如,虽然已经将耗尽模式FET描述为GaN基器件,但是本发明更通常地包括由任何III族氮化物化合物半导体形成的耗尽模式FET,在III族氮化物化合物半导体中,III族元素可以是镓(Ga)、铝(Al)、硼(B)或铟(In)。
Claims (15)
1.一种电路,包括:
输入漏极节点、输入源极节点和输入栅极节点;
具有源极、漏极和栅极的III族氮化物耗尽模式FET,其中,所述耗尽模式FET是具有大于100V的额定电压的高压FET,
其中,所述耗尽模式FET的栅极联接到使所述耗尽模式FET保持在其导通状态的电势,
其中,所述耗尽模式FET具有二维高迁移率沟道,该二维高迁移率沟道将载流子限制在III族氮化物层和肖特基层之间的界面区域;
具有源极、漏极和栅极的增强模式FET,其中,所述增强模式FET是硅基器件或者GaAs基器件,并且其中,所述耗尽模式FET的所述源极串联联接到所述增强模式FET的所述漏极,并且
其中,所述耗尽模式FET的所述漏极用作所述输入漏极节点,所述增强模式FET的所述源极用作所述输入源极节点,并且所述增强模式FET的所述栅极用作所述输入栅极节点。
2.根据权利要求1所述的电路,其中,所述III族氮化物包括GaN。
3.根据权利要求1所述的电路,其中,所述III族氮化物耗尽模式FET包括:
衬底;
设置在所述衬底的上方的第一有源层;
设置在所述第一有源层上的第二有源层,所述第二有源层具有比所述第一有源层高的带隙以使得在所述第一有源层和所述第二有源层之间产生二维电子气层;
设置在所述第二有源层上的快闪层;以及
设置在所述快闪层上的源极接触、栅极接触和漏极接触。
4.根据权利要求3所述的电路,其中,所述第一有源层包含GaN并且所述第二有源层包含III族氮化物半导体材料。
5.根据权利要求4所述的电路,其中,所述第二有源层包含AlxGa1-xN,其中0<X<1。
6.根据权利要求4所述的电路,其中,所述第二有源层选自由AlGaN、AlInN和AlInGaN组成的组。
7.根据权利要求3所述的电路,还包括设置在所述衬底和所述第一有源层之间的成核层。
8.根据权利要求3所述的电路,其中,所述快闪层包含金属Al。
9.根据权利要求3所述的电路,其中,所述快闪层包含金属Ga。
10.根据权利要求3所述的电路,其中,所述快闪层是形成自然氧化物层的退火的快闪层。
11.根据权利要求3所述的电路,其中,所述第二有源层和所述快闪层包括形成在其内的第一凹进部和第二凹进部,并且所述源极接触和所述漏极接触分别设置在所述第一凹进部和所述第二凹进部中。
12.根据权利要求1所述的电路,其中,所述III族氮化物耗尽模式FET包括:
衬底;
设置在所述衬底的上方的第一有源层;
设置在所述第一有源层上的第二有源层,所述第二有源层具有比所述第一有源层高的带隙以使得在所述第一有源层和所述第二有源层之间产生二维电子气层;
形成在所述第二有源层的上方的AlN层;以及
设置在所述AlN层的上方的源极接触、栅极接触和漏极接触。
13.根据权利要求1所述的电路,其中,所述III族氮化物耗尽模式FET包括:
衬底;
设置在所述衬底的上方的第一有源层;
设置在所述第一有源层上的第二有源层,所述第二有源层具有比所述第一有源层高的带隙以使得在所述第一有源层和所述第二有源层之间产生二维电子气层,其中所述第二有源层包括形成在其内的第一凹进部和第二凹进部;
分别设置在所述第一凹进部和所述第二凹进部中的源极接触和漏极接触;以及
设置在所述第二有源层的上方的栅极电极。
14.根据权利要求1-13中任一权利要求所述的电路,其中,所述增强模式FET具有20V的额定电压。
15.根据权利要求1-13中任一权利要求所述的电路,其中,所述增强模式FET是GaAs基器件。
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CN (2) | CN101689570B (zh) |
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KR101497725B1 (ko) | 2015-03-04 |
EP2140497A2 (en) | 2010-01-06 |
CN102694013A (zh) | 2012-09-26 |
JP5580602B2 (ja) | 2014-08-27 |
EP2140497A4 (en) | 2011-09-21 |
CN101689570A (zh) | 2010-03-31 |
HK1142996A1 (en) | 2010-12-17 |
US7501670B2 (en) | 2009-03-10 |
US20080230784A1 (en) | 2008-09-25 |
WO2008116038A2 (en) | 2008-09-25 |
JP2014209659A (ja) | 2014-11-06 |
WO2008116038A3 (en) | 2008-11-20 |
CN101689570B (zh) | 2012-06-27 |
KR20100015747A (ko) | 2010-02-12 |
JP2010522432A (ja) | 2010-07-01 |
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