WO2016185745A1 - 複合型半導体装置 - Google Patents
複合型半導体装置 Download PDFInfo
- Publication number
- WO2016185745A1 WO2016185745A1 PCT/JP2016/055085 JP2016055085W WO2016185745A1 WO 2016185745 A1 WO2016185745 A1 WO 2016185745A1 JP 2016055085 W JP2016055085 W JP 2016055085W WO 2016185745 A1 WO2016185745 A1 WO 2016185745A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- fet
- semiconductor device
- gan
- composite semiconductor
- drain current
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 239000002131 composite material Substances 0.000 title claims abstract description 154
- 230000006378 damage Effects 0.000 claims description 7
- 230000007935 neutral effect Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 19
- 230000007423 decrease Effects 0.000 description 7
- 238000001514 detection method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 5
- 229920006395 saturated elastomer Polymers 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000001771 impaired effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 125000005842 heteroatom Chemical group 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000036314 physical performance Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0828—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in composite switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/10—Modifications for increasing the maximum permissible switched voltage
- H03K17/107—Modifications for increasing the maximum permissible switched voltage in composite switches
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/567—Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04034—Bonding areas specifically adapted for strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73221—Strap and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/83801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/1033—Gallium nitride [GaN]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13064—High Electron Mobility Transistor [HEMT, HFET [heterostructure FET], MODFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/003—Constructional details, e.g. physical layout, assembly, wiring or busbar connections
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K2017/6875—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors using self-conductive, depletion FETs
Definitions
- the present invention relates to a composite semiconductor device.
- Si silicon
- Si-FETs normally-off type FETs
- a normally-off type FET is a transistor in which a drain-source is turned on when a gate voltage is applied between the gate and the source, and a drain-source is turned off when no gate voltage is applied between the gate and the source. It is.
- GaN-FETs have high utility voltage, high breakdown voltage, high temperature operation, and low on-resistance due to heterojunction, which can be realized relatively easily.
- the GaN-FET is normally a normally-on type FET and is difficult to use as a normally-off type.
- a normally-on type FET In a normally-on type FET, it is turned on even if the gate voltage is 0 V (volt). As a power device, a normally-off type operation is strongly demanded from the viewpoint of safety. Therefore, there has been proposed a composite semiconductor device that realizes a normally-off type semiconductor switch as a whole device by connecting a normally-on type FET and a normally-off type FET in series to form a cascode configuration. Since the cascode configuration suppresses the mirror effect as is well known, the high-speed operation of the normally-on type FET is not impaired.
- Patent Document 1 discloses a composite semiconductor device having a cascode configuration in which a normally-on switching element and a normally-off switching element are connected in series. Voltage clamp means is provided as a protection circuit between the drain (or collector) and gate (or base) of the normally-off switching element.
- Patent Document 2 discloses a composite semiconductor device having a cascode configuration in which a normally-on type power semiconductor switching element constituted by a wide gap semiconductor and a plurality of normally-off type metal insulating film semiconductor field effect transistors are connected in series. Has been. A high-speed diode connected in parallel with the cascode element is provided to reduce the switching loss due to the reverse recovery current.
- Patent Document 3 discloses a composite semiconductor device having a cascode configuration in which normally-on GaN semiconductor FETs manufactured in various configurations and normally-off FETs are connected in series.
- Japanese Patent Publication Japanese Patent Laid-Open No. 2006-324839 (published on November 30, 2006)” Japanese Patent Publication “Japanese Patent Laid-Open Publication No. 2006-158185 (published on June 15, 2006)” Japanese Patent Gazette “Special Table 2010-522432 Gazette (published July 1, 2010)”
- a load short-circuit state may occur due to an excessive load or malfunction.
- an overcurrent is detected using a shunt resistor or the like, if the normally-off FET can be shut off at high speed, the breakdown of the composite semiconductor device due to a load short circuit can be suppressed.
- the overcurrent detection speed response speed of the circuit that detects the overcurrent
- the probability of erroneous detection increases due to the effects of switching noise, etc., which can lead to malfunction of the entire system. The speed cannot be increased too much.
- the present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a composite semiconductor device having a low on-resistance and high resistance to a load short circuit.
- a composite semiconductor device includes a normally-on first FET and a normally-off second FET that are cascode-connected to each other.
- the voltage applied to the drain of the first FET is 400 V
- the elapsed time from the timing when the short circuit of the load connected to the composite semiconductor device starts is defined as an elapsed time T after the short circuit, and the on-resistance of the second FET Is RonQ2
- the threshold voltage of the first FET is VTHQ1
- the drain current of the first FET in the saturation state of the first FET when the gate voltage of the first FET is 0 V Idmax1, and the elapsed time after short circuit T ⁇ 2 ⁇ sec.
- FIG. 1 is a circuit diagram showing a specific configuration of a composite semiconductor device according to Embodiment 1 of the present invention and a configuration around a composite semiconductor device. It is a figure which shows the Vds-Id characteristic in each Vgs of GaN-FET in the said composite type semiconductor device. It is a graph which shows the Vds-Id characteristic in each Vgs of the said composite type semiconductor device. 6 is a graph showing the relationship between the maximum drain current flowing through the composite semiconductor device and the on-resistance of the Si-FET at each threshold voltage of the GaN-FET of the composite semiconductor device.
- a circuit configuration of a cascode device including a GaN-FET (first FET) Q1 and a Si-FET (second FET) Q2 as a composite semiconductor device (composite switching element) will be described.
- first FET GaN-FET
- second FET Si-FET
- composite semiconductor device composite switching element
- the gate voltage in an arbitrary FET refers to the gate potential based on the source potential of the FET.
- ON means that the drain and source of the FET are in a conductive state
- OFF means that the drain and source of the FET are in a disconnected state.
- FIG. 1 is a circuit diagram showing a specific configuration of the composite semiconductor device 10 according to the first embodiment and a configuration around the composite semiconductor device 10.
- the composite semiconductor device 10 of this embodiment includes a GaN-FET Q1 and a Si-FET Q2 connected in series, a drain terminal Td connected to the drain of the GaN-FET Q1, and a source terminal connected to the source of the Si-FET Q2. Ts, a gate terminal Tg connected to the gate of the Si-FET Q2, and a resistor 4 are provided.
- the GaN-FET Q1 and the Si-FET Q2 are both N-channel FETs.
- the voltage source 1 is connected to the drain terminal Td
- the control circuit 2 is connected to the gate terminal Tg
- the load 3 is connected to the source terminal Ts
- the load 3 is grounded. Has been.
- the composite semiconductor device 10 is specifically configured as follows.
- the drain terminal Td is connected to the drain of the GaN-FET Q1, and the source of the GaN-FET Q1 is connected to the drain of the Si-FET Q2.
- the gate of the Si-FET Q2 is connected to the gate terminal Tg.
- the source of the Si-FET Q2 is connected to the source terminal Ts and to one end of the resistor 4.
- the other end of the resistor 4 is connected to the gate of the GaN-FET Q1. That is, the source of the Si-FET Q2 is connected to the gate of the GaN-FET Q1 via the resistor 4.
- the source of the Si-FET Q2 and the gate of the GaN-FET Q1 may be directly connected without passing through the resistor 4.
- the GaN-FET Q1 and the Si-FET Q2 are cascode-connected (connected in a cascode configuration). That is, the composite semiconductor device 10 has a configuration in which a GaN-FET Q1 as a gate grounded FET is stacked on a Si-FET Q2 as a grounded source FET.
- the GaN-FET Q1 includes a group III nitride semiconductor (compound semiconductor) represented by GaN (GalliumalNitride), AlGaN, InGaN, and the like.
- a GaNFET that is, a normally-on type FET formed of a GaN semiconductor. It is. In a normally-on type FET, the FET is turned on even when the gate voltage is 0 V (volt). Accordingly, the GaN-FET Q1 is turned on when the gate voltage to the GaN-FET Q1 is equal to or higher than a predetermined threshold voltage VTHQ1 having a zero or negative voltage value, and is turned off when lower than the threshold voltage VTHQ1.
- the Si-FET Q2 is a SiMOSFET (Si-Metal Oxide Semiconductor Semiconductor Field Effect Transistor), that is, an insulated gate FET formed of a silicon semiconductor, and is a normally-off FET.
- the Si-FET Q2 may be formed of a Schottky gate type FET.
- an appropriate FET may be selected as appropriate according to the characteristics required for the composite semiconductor device 10, thereby reducing restrictions on the design of the composite semiconductor device 10. In a normally-off type FET, it is turned off when the gate voltage is 0 V (volt).
- the Si-FET Q2 is turned on when the gate voltage to the Si-FET Q2 is equal to or higher than the threshold voltage VTHQ2, and is turned off when it is lower than the threshold voltage VTHQ2.
- the threshold voltage VTHQ2 is a positive voltage value.
- the Si-FET Q2 has a built-in parasitic diode whose forward direction is from the source to the drain.
- the voltage source 1 applies a DC power supply voltage VDD with respect to the ground to the drain terminal Td (VDD> 0).
- the control circuit 2 supplies the gate voltage VgsQ2 to the Si-FET Q2 via the gate terminal Tg, and controls the gate voltage VgsQ2 of the Si-FET Q2. Thereby, ON / OFF of the Si-FET Q2 is controlled.
- the Si-FET Q2 When the Si-FET Q2 is on, a current flows from the drain terminal Td of the composite semiconductor device 10 to the source terminal Ts. At this time, since the voltage drop in the Si-FET Q2 is approximately 0 V (volt), the gate voltage VgsQ1 applied as a reverse voltage to the normally-on GaN-FET Q1 is also approximately 0 V. Therefore, the GaN-FET Q1 is kept on.
- the gate voltage VgsQ2 supplied from the control circuit 2 to the Si-FET Q2 is set to the threshold voltage VTHQ2 or less and the Si-FET Q2 is turned off, the drain potential of the Si-FET Q2 rises. Therefore, the drain-source voltage VdsQ2 of the Si-FET Q2 increases.
- the drain-source voltage VdsQ2 of the Si-FET Q2 is applied as a reverse voltage to the gate voltage VgsQ1 of the GaN-FET Q1. Thereby, when the gate voltage VgsQ1 of the GaN-FET Q1 becomes lower than the threshold voltage VTHQ1, the GaN-FET Q1 is turned off.
- the Si-FET Q2 is turned on (conducted) and turned off when the Si-FET Q2 is turned off ( It will be in the cut-off state). That is, the composite semiconductor device 10 realizes the operation of one normally-off FET as the entire device.
- a current flowing from the drain terminal Td to the source terminal Ts is defined as a drain current Id.
- the drain current Id corresponds to the drain current when the composite semiconductor device 10 is regarded as one normally-off FET, and coincides with the drain current of the GaN-FET Q1 and the drain current of the FET Q2.
- the drain current Id is supplied to the load 3 via the source terminal Ts and flows into the ground.
- the type of the load 3 is arbitrary, and when the inverter circuit is formed using the composite semiconductor device 10, the arm of the inverter circuit can be included in the load 3.
- the control circuit 2 can also perform switching control for alternately turning on and off the Si-FET Q2. However, unless otherwise specified, a gate voltage for turning on the Si-FET Q2 is supplied to the Si-FET Q2. Think of the state you are in.
- FIG. 2 is a diagram showing Vds-Id characteristics at each gate voltage VgsQ1 of the GaN-FET Q1 in the composite semiconductor device 10.
- Vds means a drain-source voltage
- Id means a drain current
- the drain current Id flowing through the GaN-FET Q1 increases as the drain-source voltage VdsQ1 of the GaN-FET Q1 increases from 0 V to a constant value, and the drain-source voltage VdsQ1 becomes constant.
- the increase in the current value is almost eliminated due to saturation of the GaN-FET Q1.
- a state in which an arbitrary FET is saturated is referred to as a saturated state.
- the drain current Id flowing through the GaN-FET Q1 increases as the difference between the threshold voltage VTHQ1 of the GaN-FET Q1 and the gate voltage VgsQ1 increases. Therefore, as shown in FIG. 2, as the gate voltage VgsQ1 increases from ⁇ 7V to 0V, the drain current Id increases, and the drain current Id that flows in the saturation state of the GaN-FET Q1 also increases. I understand that
- the drain current Id in the saturation state is Idmax1.
- this Idmax1 is also referred to as the maximum drain current at the time of overcurrent.
- the gate voltage VgsQ1 applied to the GaN-FET Q1 is the reverse voltage of the potential difference between the drain and the source of the Si-FET Q2, and is expressed by the following formula (2).
- Equation (3) VTHQ1 is a negative value and is expressed with an absolute value.
- Id gm ( ⁇ RonQ2 * Id +
- ) ⁇ Id (1 + gm * RonQ2) gm *
- ⁇ Id gm *
- FIG. 3 is a graph showing the Vds-Id characteristics at each gate voltage Vgs of the composite semiconductor device 10.
- the GaN-FET Q1 becomes saturated as shown in FIG.
- the short circuit of the load 3 that is, the source terminal Ts becomes a ground potential of 0 V
- the load short circuit is one of the factors that cause the drain current Id to become an overcurrent.
- the control circuit 2 detects the current value of the drain current Id using a shunt resistor (not shown) or a pulse transformer (not shown) inserted in series in the path through which the drain current Id flows, and the overcurrent is based on the detected current value. Corresponding processing can be performed.
- the control circuit 2 determines that an overcurrent has occurred in the composite semiconductor device 10 when the detected current value is equal to or greater than a predetermined overcurrent determination threshold value I LIM , and the drain current The path where Id flows is blocked.
- the interruption is realized by turning off the Si-FET Q2 or turning off a switch (a semiconductor switching element other than the Si-FET Q2 or a mechanical relay) inserted in series in the path through which the drain current Id flows.
- the control circuit 2 is formed so that the occurrence of overcurrent is detected at a timing when a predetermined overcurrent detection response time has elapsed after the drain current Id has actually exceeded the overcurrent determination threshold value ILIM. ing. Therefore, a time of several ⁇ sec is generally required as a time from when the drain current Id becomes an overcurrent due to a load short-circuit until the control circuit 2 interrupts the path through which the drain current Id flows. That is, the composite semiconductor device 10 having the cascode configuration is required to withstand a load short circuit for a certain period of time in practice.
- the drain current Id flowing through the composite semiconductor device when the load is short-circuited can be withstood until the control circuit 2 cuts off the path through which the drain current Id flows, that is, the GaN-FET Q1 does not break for a certain period of time. It is necessary to limit the maximum drain current Idmax.
- the GaN-FET Q1 of the composite semiconductor device 10 may be destroyed immediately. Therefore, it is necessary for the composite semiconductor device 10 to withstand a certain amount of time without breaking when the load is short-circuited.
- the composite semiconductor device 10 is required to withstand at least 2 ⁇ sec, preferably 5 ⁇ sec, without being destroyed. Such a short-circuit withstand capability when a load is short-circuited is not generally listed as a specification in a high-speed switching device.
- the composite semiconductor device 10 of the present embodiment has a drain that flows to the GaN-FET Q1 when the load is short-circuited by the absolute values of the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET Q1 satisfying the relationship described later.
- the current Id is limited to the maximum drain current Idmax that prevents the destruction of the GaN-FET Q1 for a certain period of time.
- the value of the on-resistance of the Si-FET Q2 (on-resistance RonQ2 described later) or the threshold voltage VTHQ1 of the GaN-FET Q1 is the short circuit of the load 3 connected to the composite semiconductor device 10 by using the drain current Id of the GaN-FET Q1.
- the maximum drain current Idmax is limited so as to prevent the destruction of the GaN-FET Q1 due to the occurrence of a certain period of time.
- VdsQ2 RonQ2 ⁇ Idmax It becomes.
- the gate voltage Vgs of the composite semiconductor device 10 that is, the gate voltage VgsQ2 of the Si-FET Q2 is high and a lot of drain current Id can flow through the composite semiconductor device 10, the on-resistance of the Si-FET Q2 when the load is short-circuited.
- RonQ2 a reverse voltage corresponding to the voltage drop in the Si-FET Q2 is applied to the GaN-FET Q1.
- the drain current Id flowing through the GaN-FET Q1 is limited to the maximum drain current Idmax. Therefore, the drain current Id flowing through the composite semiconductor device 10 is limited to the maximum drain current Idmax as shown in FIG.
- the on-resistance Ron of the composite semiconductor device 10 is the sum of the on-resistance RonQ1 of the GaN-FET Q1 and the on-resistance RonQ2 of the Si-FET Q2.
- Ron RonQ1 + RonQ2 Therefore, if the on-resistance RonQ2 of the Si-FET Q2 is too high, the on-resistance Ron of the composite semiconductor device 10 becomes too high. It is important to limit the drain current Id to the maximum drain current Idmax within the range satisfying the following relational expression so that the advantage of the low on-resistance of the GaN-FET Q1 is utilized and the GaN-FET Q1 is not destroyed when the load is short-circuited. .
- the saturation current of the drain current Id flowing through the GaN-FET Q1 increases as the threshold voltage VTHQ1 increases, in other words, as the absolute value of the threshold voltage VTHQ1 decreases. The value is reduced.
- the voltage VTHQ1 can withstand at least 2 ⁇ sec, preferably 5 ⁇ sec, without being destroyed. Therefore, when the load is short-circuited, the control circuit 2 can cut off the path through which the drain current Id flows before the GaN-FET Q1 is destroyed.
- Idmax Idmax1 / (1 + gm / RonQ2)
- Idmax Idmax1 / (1+ (Idmax1 /
- the maximum drain current Idmax1 at the time of overcurrent in the GaN-FET Q1 can take various values. Among them, there is a problem when the maximum drain current Idmax1 at the time of overcurrent of the GaN-FET Q1 is a current value that may destroy the GaN-FET Q1.
- the above formula (7) By satisfying this relationship, the drain current Id flowing through the composite semiconductor device 10 can be limited to the maximum drain current Idmax, and the destruction of the GaN-FET Q1 can be prevented for a certain period of time.
- FIG. 4 shows the relationship between the maximum drain current Idmax flowing through the composite semiconductor device 10 and the on-resistance RonQ2 of the Si-FET Q2 at each threshold voltage VTHQ1 of the GaN-FET Q1 of the composite semiconductor device 10 as a result.
- the allowable maximum current value of the GaN-FET Q1 is 200 A
- the on-resistance RonQ2 of the Si-FET Q2 and the threshold value VTHQ1 of the GaN-FET Q1 are set so that the maximum drain current Idmax ⁇ 200A. And it is sufficient.
- the maximum drain current Idmax in the composite semiconductor device 10 of the present embodiment is less than or equal to the allowable maximum current value of the GaN-FET Q1.
- This allowable maximum current value varies depending on the specific specifications of the GaN-FET Q1 and the length of time required as the endurance time from the load short circuit until the GaN-FET Q1 breaks, as will be described later. That is, the allowable maximum current value means a current value at which the GaN-FET Q1 is not destroyed or deteriorated in characteristics for a desired period of time, specifically, for example, 2 ⁇ sec, as will be described later.
- the maximum drain current Idmax1 at the time of overcurrent flowing through the GaN-FET Q1 when the load is short-circuited can take various values.
- the voltage applied to the GaN-FET Q1 is fixed to 400 V will be described.
- the voltage actually applied to the GaN-FET Q1 can naturally have various voltage values depending on the circuit configuration in which the composite semiconductor device 10 of the present embodiment is incorporated.
- the composite semiconductor device 10 of the present embodiment satisfies the following relational expression in a state where a voltage of 400 V is applied to the GaN-FET Q1 no matter what circuit is incorporated. ing.
- the maximum drain current Idmax1 at the time of overcurrent flowing through the GaN-FET Q1 when the load is short-circuited can take various values.
- the allowable maximum current value obtained as the maximum drain current Idmax obtained by limiting the drain current Id flowing through the GaN-FET Q1 when the load is short-circuited is the maximum drain current Idmax1 value at the time of overcurrent and the GaN-FET Q1 is destroyed due to the load short-circuit. It varies depending on the length of time required as the endurance time.
- the maximum drain current Idmax to be limited is obtained based on the value of the maximum drain current Idmax1 at the time of overcurrent and the length of time required as the endurance time from the load short-circuit until the GaN-FET Q1 breaks down.
- the condition that the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET must satisfy is expressed by the above equation (6). To be determined. This will be described below with reference to FIGS.
- FIG. 5 shows the maximum drain current Idmax1 at the time of overcurrent of the GaN-FET Q1, the breakdown time Tp at each short-circuit, and the restrictions on the flow through the composite semiconductor device 10 when the load connected to the composite semiconductor device 10 is short-circuited.
- 6 is a table showing the conditions to be satisfied by the maximum drain current Idmax, the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET obtained therefrom.
- the breakdown time Tp at the time of short circuit is a time as described below.
- the composite semiconductor device 10 is required to withstand a certain amount of time without breaking the GaN-FET Q1 even when a voltage of 400 V is applied to the GaN-FET Q1 due to a load short circuit.
- an elapsed time from the timing when the load is short-circuited is defined as an elapsed time T after the short-circuit, and a time until the GaN-FET Q1 is destroyed when a certain maximum drain current Idmax flows is defined as a short-circuit destruction time Tp.
- the short-circuit breaking time Tp means the time that the GaN-FET Q1 can withstand without being broken when the load is short-circuited.
- each maximum drain current Idmax of the composite semiconductor device 10 is determined by the short-circuit breakdown time Tp as described later. Assuming that the maximum drain current Idmax determined by the short-circuit breakdown time Tp is the allowable maximum current value, the value of the maximum drain current Idmax1 at the time of overcurrent and the allowable maximum current value are expressed in the above equation (6). By substituting, a condition to be satisfied by the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET Q1 is determined.
- the load on the load when the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET Q1 satisfy the relationship of Expression (6) under various conditions.
- the GaN-FET Q1 can withstand without breaking for a desired elapsed time T after the short circuit.
- each maximum drain current Idmax of the composite semiconductor device 10 based on the desired short-circuit breakdown time Tp in FIG. 5 will be described below with reference to FIG.
- FIG. 6 is a graph showing the relationship between the maximum drain current Idmax flowing through the composite semiconductor device 10 and the time from when the maximum drain current Idmax starts to flow until the GaN-FET Q1 breaks down.
- the short-circuit breaking time Tp decreases.
- the maximum drain current Idmax should be 300 A.
- the maximum drain current Idmax should be 230 A.
- the maximum drain current Idmax should be 180 A.
- the short-circuit breakdown time Tp is at least 2 ⁇ sec or more, but the short-circuit breakdown time Tp required for the composite semiconductor device 10 is the composite semiconductor device 10.
- the short-circuit breaking time Tp is preferably 5 ⁇ sec or more.
- the short-circuit breaking time Tp Is preferably 3 ⁇ sec or more.
- the maximum drain current Idmax1 at the time of overcurrent in the GaN-FET Q1 can be various values, for example, 250A, 300A, 350A, or of course other current values.
- the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET Q1 are in a trade-off relationship.
- RonQ2 ⁇ 9.4 m ⁇ may be satisfied
- 10 V
- RonQ2 ⁇ 15.6 m ⁇ may be satisfied
- 20V, RonQ2 ⁇ 31,2 m ⁇ . That's fine.
- the maximum drain current Idmax in the above equation (6) may satisfy the relationship of the following equation (9) from 230A.
- the threshold voltage VTHQ1 of the GaN-FET Q1 preferably satisfies
- the on-resistance Ron of the entire composite semiconductor device 10 is preferably 60 m ⁇ or less.
- the threshold voltage VTHQ1 of the GaN-FET Q1 is preferably
- the on-resistance RonQ1 of the GaN-FET Q1 is approximately 31 m ⁇ .
- RonQ2 ⁇ 3.5 m ⁇ is sufficient from the above relational expression, and at this time, Ron ⁇ 35 m ⁇ .
- RonQ2 ⁇ 15.6 m ⁇ is sufficient from the above relational expression, and at this time, Ron ⁇ 47 m ⁇ .
- 20V
- the current value of the maximum drain current Idmax1 at the time of overcurrent in the GaN-FET Q1 may be, for example, 300 A, 350 A, or other current values.
- the relationship as shown in FIG. 6 can be obtained, and based on this, the maximum drain current Idmax that provides a desired short-circuit breakdown time can be obtained.
- the on-resistance RonQ2 of the Si-FET Q2 and the threshold voltage VTHQ1 of the GaN-FET Q1 satisfy the relationship of the relational expression (6).
- the control of the on-resistance Ron as described above can be performed, for example, by increasing the drift resistance, increasing the junction resistance, or the like, and may be performed using other methods.
- a super junction type MOSFET can be used in order to achieve a low on-resistance.
- a planar type or trench type SiMOSFET may be used, and the manufacturing cost can be reduced.
- the circuit configuration of the composite semiconductor device 10 that includes the normally-on GaN-FET Q1 and the normally-off Si-FET Q2 and limits the maximum drain current of the GaN-FET Q1 by the on-resistance RonQ2 of the Si-FET Q2.
- the present embodiment a specific configuration of a composite semiconductor device in which the GaN-FET Q1 and the Si-FET Q2 are mounted in one TO (Transistor-Outline) type package will be described.
- FIG. 7A is a top view showing a specific configuration of the composite semiconductor device according to the present embodiment
- FIG. 7B is a side view.
- the composite semiconductor device 100 includes a normally-on type field effect transistor 101 (hereinafter simply referred to as the transistor 101) and a normally-off type field effect transistor 102 ( Hereinafter, the transistor 102 is simply provided), a first terminal 103 (drain terminal), a second terminal 104 (gate terminal), a die pad 106 that functions as a source terminal of the composite semiconductor device 100, and a sealing member 107.
- the transistor 101 is made of, for example, a GaN-FET Q1, and has a higher breakdown voltage than the transistor 102.
- the transistor 102 is, for example, a Si-FET Q2.
- the die pad 106 only needs to be formed of a conductive material, and is not limited to other conditions.
- the sealing member 107 is made of, for example, resin.
- the transistor 101 and the transistor 102 are cascode-connected.
- the transistor 101 and the transistor 102 are disposed on the die pad 106. Further, the transistor 101 and the transistor 102 are sealed with a sealing member 107.
- the die pad 106, the transistor 101, and the transistor 102 each have a first main surface and a second main surface, as shown in FIG. 7B.
- the upper surface and the lower surface of the transistor 101 are referred to as a first main surface S1 and a second main surface S4, respectively.
- the upper surface and the lower surface of the transistor 102 are referred to as a first main surface S2 and a second main surface S5, respectively.
- the upper surface and the lower surface of the die pad 106 are referred to as a first main surface S3 and a second main surface S6, respectively.
- the transistor 101 has a lateral structure, and the gate electrode 110, the drain electrode 111, and the source electrode 112 are disposed on the first main surface S1. And the electrode is not formed in 2nd main surface S4. Note that an electrode may be formed on the second main surface S4 in consideration of heat dissipation, and mounting using solder may be performed on the electrode.
- the transistor 102 has a horizontal structure, and has a source electrode as a back electrode, and has a vertical structure in appearance. Alternatively, the transistor 102 has a vertical structure. And the gate electrode 120 and the drain electrode 121 are arrange
- Part of the first main surface S3 of the die pad 106 also serves as the third terminal 105 of the composite semiconductor device 100.
- the source electrode 112 disposed on the first main surface S1 of the transistor 101 and the drain electrode 121 disposed on the first main surface S2 of the transistor 102 are electrically connected by a conductor 113.
- the drain electrode 111 disposed on the first main surface S 1 of the transistor 101 and the first terminal 103 are electrically connected by a conductor 114.
- the gate electrode 120 disposed on the first main surface S2 of the transistor 102 and the second terminal 104 are electrically connected by a conductive member 116.
- the gate electrode 110 disposed on the first main surface S1 of the transistor 101 and the first main surface S3 of the die pad 106 are electrically connected by a conductive member 115.
- the source electrode 122 disposed on the second main surface S5 of the transistor 102 and the first main surface S3 of the die pad 106 are electrically connected.
- the first main surface S3 of the die pad 106 and the second main surface S5 of the transistor 102 are opposed to and in contact with each other. Further, the first main surface S3 of the die pad 106 and the second main surface S4 of the transistor 101 are opposed to and in contact with each other.
- the second main surface S4 of the transistor 101 is die-bonded on the first main surface S3 of the die pad 106 using a thermally conductive die bond material. Since the die bond material has thermal conductivity, heat generated in the transistor 101 can be radiated to the die pad 106. Note that since the transistor 101 and the die pad 106 do not need to be electrically connected to each other, the die bonding material may not have conductivity.
- the second main surface S5 of the transistor 102 is die-bonded on the first main surface S3 of the die pad 106 with solder or the like. The solder has a function of electrically bonding the transistor 102 and the die pad 106 together with a function of die-bonding the transistor 102 to the die pad 106. Instead of solder, a conductive paste having a high die bond performance may be used.
- the GaN-FET Q1 (transistor 101) and the Si-FET Q2 (transistor 102) are arranged on the same lead frame.
- the gate electrode 110 of the transistor 101 is connected to the source electrode 122 and the third terminal 105 of the transistor 102 and has the same potential.
- the Si-FET Q2 when a load is connected to the third terminal 105 of the composite semiconductor device 100, the Si-FET Q2 is on and the drain current Id is flowing, when the load is short-circuited, the gate voltage of the GaN-FET Q1 is A reverse voltage of the drain-source voltage of the Si-FET Q2 is applied.
- the composite semiconductor device 100 according to the present embodiment since the on-resistance RonQ2 of the Si-FET Q2 is high, the maximum drain current flowing through the GaN-FET Q1 is such that the breakdown of the GaN-FET Q1 is prevented. Limited to.
- the absolute value of the threshold voltage VTHQ1 of the GaN-FET Q1 is low, the difference between the gate voltage VgsQ1 of the GaN-FET Q1 and the threshold voltage VTHQ1 is small, and the maximum drain current Idmax is limited.
- the die pad 106 functions as a source terminal, and both the transistors 101 and 102 are mounted on the die pad 106 that is a source frame.
- the specific configuration of the composite semiconductor device 100 in which the GaN-FET Q1 and the Si-FET Q2 are mounted in one TO type package has been described.
- an inverter / bridge circuit 200 to which the composite semiconductor device 100 is applied will be described.
- FIG. 8 is a circuit diagram showing a specific configuration applied to the inverter / bridge circuit 200 of the composite semiconductor device 100 according to the present embodiment.
- the inverter / bridge circuit 200 includes a positive electrode P having a positive potential, a negative electrode N having a lower potential than the positive electrode P, a positive electrode P, and a negative electrode. And four cascode GaN transistors T1 to T4 connected to N, a load 201 connected to the cascode GaN transistors T1 to T4, and two coils L1 and L2 connected to the load 201.
- the composite semiconductor device 100 is used for the cascode GaN transistors T1 to T4. That is, in each of the cascode GaN transistors T1 to T4, the GaN-FET Q1 and the Si-FET Q2 have a cascode configuration.
- the gate voltage of the Si-FET Q2 of each cascode GaN transistor T1 to T4 is controlled by a control device (not shown), thereby controlling the on / off of each cascode GaN transistor T1 to T4.
- the load 201 is connected to the cascode GaN transistors T1 and T2 via the coil L1, and is connected to the cascode GaN transistors T3 and T4 via the coil L2.
- the positive electrode P is connected to the cascode GaN transistors T1 and T3, and the negative electrode N is connected to the cascode GaN transistors T2 and T4.
- the inverter / bridge circuit 200 converts direct current into alternating current by controlling each of the cascode GaN transistors T1 to T4. Such an inverter / bridge circuit 200 is required to withstand a load when a load is short-circuited due to an excessive load or malfunction.
- the inverter / bridge circuit 200 of the present embodiment has high resistance against load short-circuiting by using the composite semiconductor device 100 for each of the cascode GaN transistors T1 to T4.
- the absolute value of the threshold voltage VTHQ1 of the GaN-FET Q1 is low, the difference between the gate voltage VgsQ1 of the GaN-FET Q1 and the threshold voltage VTHQ1 is small, and the maximum drain current Idmax is limited.
- a composite semiconductor device includes a normally-on first FET (GaN-FET Q1) and a normally-off second FET (Si-FET Q2) that are cascode-connected to each other.
- the voltage applied to the drain of the first FET is 400 V
- the elapsed time from the timing when the short circuit of the load connected to the composite semiconductor device starts is defined as an elapsed time T after the short circuit, and the second FET is turned on.
- the resistance value is RonQ2
- the threshold voltage of the first FET is VTHQ1
- the drain current limited to an extent that prevents the destruction of the first FET is Idma Satisfy the following expression when the.
- the on-resistance of the second FET and the threshold voltage of the first FET satisfy the above relational expression.
- the on-resistance of the second FET is slightly higher, and when the load connected to the composite semiconductor device is short-circuited, the voltage drop in the second FET becomes larger, and the reverse voltage corresponding to this voltage drop becomes the first voltage. It is applied as a gate voltage to one FET, and the maximum drain current of the first FET can be limited.
- the absolute value of the threshold voltage of the first FET is slightly lower, and the difference between the gate voltage of the first FET and the threshold voltage of the first FET is small when the load connected to the composite semiconductor device is short-circuited.
- the maximum drain current of the first FET can be limited. Thereby, when the load is short-circuited, the first FET can be prevented from being destroyed while the post-short-circuit elapsed time T is at least 2 ⁇ sec. Further, even if the on-resistance of the second FET is slightly high, the overall on-resistance of the composite semiconductor device does not need to be so high that the advantage of the low on-resistance in the composite semiconductor device is impaired. Therefore, it is possible to provide a composite semiconductor device having a low on-resistance and high resistance when a load is short-circuited.
- the composite semiconductor device according to aspect 2 of the present invention satisfies the following formula in aspect 1 above.
- the short-circuit breaking time Tp when a certain maximum drain current Idmax flows, if the time until the first FET is destroyed after the load is short-circuited is the short-circuit breaking time Tp, the overcurrent of the first FET
- the composite semiconductor device according to aspect 3 of the present invention satisfies the following formula in aspect 1 above.
- the maximum drain current Idmax can be made smaller than 180 A
- the short-circuit breakdown time Tp is 5 ⁇ sec. This can be done.
- the composite semiconductor device according to aspect 4 of the present invention satisfies
- the on-resistance RonQ2 of the second FET for satisfying the above relational expression need not be too large.
- the on-resistance value RonQ2 is 7.0 m ⁇ or more.
- the short-circuit breakdown time Tp can be set to 3 ⁇ sec or more.
- the on-resistance value RonQ2 is 31.2 m ⁇ or more.
- the short-circuit breakdown time Tp can be set to 5 ⁇ sec or more.
- the threshold voltage VTHQ1 satisfies
- the on-resistance RonQ2 of the second FET need not be too large. Therefore, it is easy to set the on-resistance of the entire composite semiconductor device to 60 m ⁇ or less.
- the on-resistance value RonQ2 is 3.5 m ⁇ or more.
- RonQ1 of the GaN-FET Q1 when the on-resistance RonQ1 of the GaN-FET Q1 is approximately 31 m ⁇ , Ron ⁇ 35 m ⁇ and the short-circuit breaking time Tp can be 3 ⁇ sec or more.
- the on-resistance value RonQ2 is 15.6 m ⁇ or more.
- RonQ1 of the GaN-FET Q1 when the on-resistance RonQ1 of the GaN-FET Q1 is approximately 31 m ⁇ , Ron ⁇ 47 m ⁇ and the short-circuit breaking time Tp can be set to 5 ⁇ sec or more.
- the second FET may be formed of an insulated gate FET or a Schottky gate FET.
- the second FET may be appropriately selected according to the characteristics required for the composite semiconductor device, thereby reducing the restrictions on the design of the composite semiconductor device.
- the first FET may be formed of a gallium nitride semiconductor.
- the first FET and the second FET may be mounted in one package.
- a compact composite semiconductor device can be provided.
- the present invention can be used for a composite semiconductor device in which a normally-on type first field effect transistor (FET) and a normally-off type second FET are cascode-connected.
- FET normally-on type first field effect transistor
- the present invention can be used for a composite semiconductor device in which a GaN-FET and a Si-FET are cascode-connected.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computing Systems (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Power Conversion In General (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Junction Field-Effect Transistors (AREA)
- Inverter Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本発明の一実施形態について図1~6に基づいて説明すれば、以下のとおりである。
本実施の形態の複合型半導体装置10の構成について、図1に基づいて説明する。図1は、本実施の形態1に係る複合型半導体装置10の具体的な構成及び複合型半導体装置10周辺の構成を示す回路図である。
ここでは、本実施の形態の複合型半導体装置10に含まれるノーマリオン型のGaN-FETQ1の各ゲート電圧VgsQ1における、Vds-Id特性について図2を用いて説明する。図2は、複合型半導体装置10内のGaN-FETQ1の各ゲート電圧VgsQ1における、Vds-Id特性を示す図である。ここで、Vdsは、ドレイン-ソース間電圧、Idはドレイン電流を意味している。
本実施の形態の複合型半導体装置10における、GaN-FETQ1を流れる電流特性について説明する。複合型半導体装置10がオンとなっており、電源電圧VDDが固定され、ドレイン端子Tdからソース端子Tsへとドレイン電流Idが流れているときの、GaN-FETQ1を流れるドレイン電流Idは、一般的に下記数式(1)で表される。
ここで、gmは相互コンダクタンスを示す。また、ノーマリオン型GaN-FETQ1の閾値電圧VTHQ1は負の値である。ここで、上述のように、GaN-FETQ1に印加されるゲート電圧VgsQ1は、Si-FETQ2のドレイン-ソース間の電位差の逆電圧であるため、下記数式(2)で表される。
数式(2)を数式(1)に代入すると、下記数式(3)が導かれる。ここで、VTHQ1は負の値であり、絶対値をつけて表す。
⇔Id(1+gm*RonQ2)=gm*|VTHQ1|
⇔Id=gm*|VTHQ1|/(1+gm*RonQ2) ・・・(3)
上記数式(3)より、GaN-FETQ1を流れるドレイン電流Idは、RonQ2が大きいほど、又は閾値電圧VTHQ1の絶対値が小さいほど低減されることがわかる。
以下に、複合型半導体装置10に接続する負荷3が短絡した場合における、複合型半導体装置10に流れるドレイン電流Idの制限作用について図2~6を用いて説明する。図3は、複合型半導体装置10の各ゲート電圧Vgsにおける、Vds-Id特性を示すグラフである。
(i)RonQ2を高くすることによる最大ドレイン電流Idmaxの制限について
負荷短絡時において、従来のSi-FETQ2では、オン抵抗RonQ2≒0Ωのため、Si-FETQ2における電圧降下は略0V(ボルト)であり、GaN-FETQ1に印加されるゲート電圧VgsQ1も略0Vになる。そのため、負荷短絡時に、GaN-FETQ1には、過電流時の最大ドレイン電流Idmax1が流れてしまう。
VdsQ2=RonQ2×Idmax
となる。このとき、GaN-FETQ1に逆電圧として印加されるゲート電圧VgsQ1は、
VgsQ1=-VdsQ2=-RonQ2×Idmax<0
となる。これにより、例えばVgsQ1=-2Vとなる場合には、図2に示すように、負荷短絡時にGaN-FETQ1に流れる最大ドレイン電流を、Idmax1からIdmaxへ低減できる。
そのため、Si-FETQ2のオン抵抗RonQ2を高くしすぎると、複合型半導体装置10のオン抵抗Ronが高くなりすぎてしまう。GaN-FETQ1の低オン抵抗のメリットを活かし、かつ負荷短絡時にGaN-FETQ1が破壊しないように、後述の関係式を満たす範囲で、ドレイン電流Idを最大ドレイン電流Idmaxに制限することが重要となる。
(ii)GaN-FETQ1の閾値電圧VTHQ1の絶対値を小さくすることによる最大ドレイン電流Idmaxの制限について
負荷短絡時において、GaN-FETQ1には電源電圧が印加され、例えば、ドレイン-ソース間電圧VdsとしてVds=400Vの電圧が印加される。このとき、GaN-FETQ1を流れるドレイン電流Idは、飽和状態となる。GaN-FETQ1のゲート電圧VgsQ1が例えば0Vであるとき、GaN-FETQ1を流れるドレイン電流Idの飽和状態の電流値は、GaN-FETQ1の閾値電圧VTHQ1の絶対値の値に依存する。すなわち、GaN-FETQ1の閾値電圧VTHQ1は負の値を有するので、閾値電圧VTHQ1が大きいほど、換言すれば閾値電圧VTHQ1の絶対値が小さいほど、GaN-FETQ1を流れるドレイン電流Idの飽和状態の電流値は低減される。
(iii)Si-FETQ2のオン抵抗RonQ2、及びGaN-FETQ1の閾値電圧VTHQ1の絶対値が満たす関係について
以下に、本実施の形態の複合型半導体装置10における、Si-FETQ2のオン抵抗RonQ2、及びGaN-FETQ1の閾値電圧VTHQ1の絶対値が満たす関係について、詳細に説明する。
数式(4)を、上述の数式(3)に代入し、式を変形すると、以下の数式(5)となる。
⇔Idmax=Idmax1/(1+(Idmax1/|VTHQ1|)*RonQ2)
・・・(5)
上記の数式(5)を変形すると、以下の数式(6)が導かれる。
本発明の他の実施の形態について図7に基づいて説明すれば、以下のとおりである。尚、本実施の形態において説明すること以外の構成は、前記実施の形態1と同じである。また、説明の便宜上、前記の実施の形態1の図面に示した部材と同一の機能を有する部材については、同一の符号を付し、その説明を省略する。
本発明の他の実施の形態について図8に基づいて説明すれば、以下のとおりである。尚、本実施の形態において説明すること以外の構成は、前記実施の形態1と同じである。また、説明の便宜上、前記の実施の形態1の図面に示した部材と同一の機能を有する部材については、同一の符号を付し、その説明を省略する。
本発明の態様1に係る複合型半導体装置は、互いにカスコード接続されたノーマリオン型の第1FET(GaN-FETQ1)及びノーマリオフ型の第2FET(Si-FETQ2)を備えている複合型半導体装置において、前記第1FETのドレインに印加されている電圧が400Vである場合、前記複合型半導体装置に接続された負荷の短絡が開始したタイミングからの経過時間を短絡後経過時間Tとし、前記第2FETのオン抵抗の値をRonQ2、前記第1FETの閾値電圧をVTHQ1、前記第1FETのゲート電圧が0Vのときの、前記第1FETの飽和状態における前記第1FETのドレイン電流をIdmax1とし、短絡後経過時間T≧2μsecの間、前記第1FETの破壊を防ぐ程度に制限したドレイン電流をIdmaxとするときに以下の式の関係を満たす。
2 制御回路
3 負荷
10、100 複合型半導体装置
Id ドレイン電流
Q1 GaN-FET(第1FET)
Q2 Si-FET(第2FET)
Ron 複合型半導体装置全体のオン抵抗
RonQ1 GaN-FETのオン抵抗
RonQ2 Si-FETのオン抵抗
VTHQ1、VTHQ2 閾値電圧
Claims (5)
- 互いにカスコード接続されたノーマリオン型の第1FET及びノーマリオフ型の第2FETを備えている複合型半導体装置において、
前記第1FETのドレインに印加されている電圧が400Vである場合、
前記複合型半導体装置に接続された負荷の短絡が開始したタイミングからの経過時間を短絡後経過時間Tとし、
前記第2FETのオン抵抗の値をRonQ2、前記第1FETの閾値電圧をVTHQ1、前記第1FETのゲート電圧が0Vのときの、前記第1FETの飽和状態における前記第1FETのドレイン電流をIdmax1とし、
短絡後経過時間T≧2μsecの間、前記第1FETの破壊を防ぐ程度に制限したドレイン電流をIdmaxとするときに以下の式の関係を満たすことを特徴とする複合型半導体装置。
- 前記閾値電圧VTHQ1は、|VTHQ1|≦20Vを満たすことを特徴とする請求項1~3のいずれか1項に記載の複合型半導体装置。
- 前記閾値電圧VTHQ1は、|VTHQ1|≦10Vを満たすことを特徴とする請求項1~4のいずれか1項に記載の複合型半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/564,138 US10128829B2 (en) | 2015-05-15 | 2016-02-22 | Composite semiconductor device |
JP2017519031A JP6408146B2 (ja) | 2015-05-15 | 2016-02-22 | 複合型半導体装置 |
CN201680027806.7A CN107667422A (zh) | 2015-05-15 | 2016-02-22 | 复合型半导体装置 |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2015100530 | 2015-05-15 | ||
JP2015-100530 | 2015-05-15 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2016185745A1 true WO2016185745A1 (ja) | 2016-11-24 |
Family
ID=57319853
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2016/055085 WO2016185745A1 (ja) | 2015-05-15 | 2016-02-22 | 複合型半導体装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US10128829B2 (ja) |
JP (1) | JP6408146B2 (ja) |
CN (1) | CN107667422A (ja) |
WO (1) | WO2016185745A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019102596A (ja) * | 2017-11-30 | 2019-06-24 | 株式会社東芝 | 半導体装置 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102018207308B4 (de) * | 2018-05-09 | 2020-07-02 | Infineon Technologies Ag | Halbleiterbauteil mit integriertem shunt-widerstand und verfahren zu dessen herstellung |
CN110277383A (zh) * | 2019-05-30 | 2019-09-24 | 同辉电子科技股份有限公司 | 一种减小GaN HEMT功率模块封装寄生电感的DBC板布局方法 |
CN117155359B (zh) * | 2023-10-26 | 2024-02-09 | 深圳智芯微电子科技有限公司 | GaN HEMT器件预处理方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006324839A (ja) * | 2005-05-18 | 2006-11-30 | Fuji Electric Holdings Co Ltd | 複合型半導体装置 |
JP2011166673A (ja) * | 2010-02-15 | 2011-08-25 | Denso Corp | ハイブリッドパワーデバイス |
JP2012222360A (ja) * | 2011-04-11 | 2012-11-12 | Internatl Rectifier Corp | Iii−v族トランジスタとiv族横型トランジスタを含む積層複合デバイス |
JP2014187726A (ja) * | 2013-03-21 | 2014-10-02 | Toshiba Corp | 半導体装置 |
WO2014192348A1 (ja) * | 2013-05-28 | 2014-12-04 | シャープ株式会社 | 半導体装置 |
WO2015033631A1 (ja) * | 2013-09-06 | 2015-03-12 | シャープ株式会社 | トランジスタ回路 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19902519C2 (de) * | 1999-01-22 | 2002-04-18 | Siemens Ag | Hybrid-Leistungs-MOSFET für hohe Stromtragfähigkeit |
DE19902520B4 (de) * | 1999-01-22 | 2005-10-06 | Siemens Ag | Hybrid-Leistungs-MOSFET |
JP2006158185A (ja) | 2004-10-25 | 2006-06-15 | Toshiba Corp | 電力用半導体装置 |
US7501670B2 (en) * | 2007-03-20 | 2009-03-10 | Velox Semiconductor Corporation | Cascode circuit employing a depletion-mode, GaN-based FET |
CN102725840B (zh) * | 2010-01-25 | 2014-12-10 | 夏普株式会社 | 复合型半导体装置 |
US20140225163A1 (en) * | 2013-02-11 | 2014-08-14 | International Rectifier Corporation | Inverter Circuit Including Short Circuit Protected Composite Switch |
CN203826387U (zh) * | 2014-03-28 | 2014-09-10 | 长安大学 | 一种GaN基超薄势垒增强/耗尽模式反相器及环振 |
-
2016
- 2016-02-22 WO PCT/JP2016/055085 patent/WO2016185745A1/ja active Application Filing
- 2016-02-22 JP JP2017519031A patent/JP6408146B2/ja not_active Expired - Fee Related
- 2016-02-22 US US15/564,138 patent/US10128829B2/en not_active Expired - Fee Related
- 2016-02-22 CN CN201680027806.7A patent/CN107667422A/zh active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006324839A (ja) * | 2005-05-18 | 2006-11-30 | Fuji Electric Holdings Co Ltd | 複合型半導体装置 |
JP2011166673A (ja) * | 2010-02-15 | 2011-08-25 | Denso Corp | ハイブリッドパワーデバイス |
JP2012222360A (ja) * | 2011-04-11 | 2012-11-12 | Internatl Rectifier Corp | Iii−v族トランジスタとiv族横型トランジスタを含む積層複合デバイス |
JP2014187726A (ja) * | 2013-03-21 | 2014-10-02 | Toshiba Corp | 半導体装置 |
WO2014192348A1 (ja) * | 2013-05-28 | 2014-12-04 | シャープ株式会社 | 半導体装置 |
WO2015033631A1 (ja) * | 2013-09-06 | 2015-03-12 | シャープ株式会社 | トランジスタ回路 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019102596A (ja) * | 2017-11-30 | 2019-06-24 | 株式会社東芝 | 半導体装置 |
US10651161B2 (en) | 2017-11-30 | 2020-05-12 | Kabushiki Kaisha Toshiba | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JPWO2016185745A1 (ja) | 2018-01-11 |
CN107667422A (zh) | 2018-02-06 |
JP6408146B2 (ja) | 2018-10-17 |
US20180083613A1 (en) | 2018-03-22 |
US10128829B2 (en) | 2018-11-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9041456B2 (en) | Power semiconductor device | |
US9653449B2 (en) | Cascoded semiconductor device | |
JP5433214B2 (ja) | モータ駆動回路 | |
JP6223918B2 (ja) | 半導体装置 | |
US9116533B2 (en) | Cascoded semiconductor devices with gate bias circuit | |
JP6211829B2 (ja) | 半導体装置 | |
US9123536B2 (en) | Semiconductor device | |
JP5829700B2 (ja) | 短絡保護された複合スイッチを含むインバータ回路 | |
JP5653326B2 (ja) | 窒化物半導体装置 | |
EP3696980A2 (en) | Configurations of composite devices comprising of a normally-on fet and a normally-off fet | |
JP5600875B2 (ja) | 双方向スイッチ及びスイッチング素子 | |
JP7016973B2 (ja) | 基板電圧制御回路 | |
JP6408146B2 (ja) | 複合型半導体装置 | |
JP2012199549A (ja) | パッシブ発振防止用のiii族窒化物トランジスタ | |
WO2011067903A1 (ja) | スイッチ装置 | |
US10854718B2 (en) | Method of forming a semiconductor device | |
JP6562359B2 (ja) | 半導体装置 | |
US20160248422A1 (en) | Switching circuit, semiconductor switching arrangement and method | |
US9705488B2 (en) | Semiconductor device | |
US20220385196A1 (en) | Substrate electric potential stabilization circuit and bidirectional switch system | |
TWI584562B (zh) | 半導體裝置 | |
JP6265849B2 (ja) | 制御回路 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 16796140 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2017519031 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 15564138 Country of ref document: US |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 16796140 Country of ref document: EP Kind code of ref document: A1 |