CN102664192A - 一种自适应复合机制隧穿场效应晶体管及其制备方法 - Google Patents

一种自适应复合机制隧穿场效应晶体管及其制备方法 Download PDF

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CN102664192A
CN102664192A CN2012101395606A CN201210139560A CN102664192A CN 102664192 A CN102664192 A CN 102664192A CN 2012101395606 A CN2012101395606 A CN 2012101395606A CN 201210139560 A CN201210139560 A CN 201210139560A CN 102664192 A CN102664192 A CN 102664192A
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doping
source region
effect transistor
control gate
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CN102664192B (zh
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黄如
黄芊芊
詹瞻
邱颖鑫
王阳元
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Peking University
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Abstract

本发明提供了一种隧穿场效应晶体管及其制备方法，属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域。本发明的核心是：对于N型晶体管，掺杂源区在N-掺杂的基础上，在靠近控制栅边缘的一侧又注入P+，使得该注入部分原有的N-掺杂完全被补偿为P+；对于P型晶体管，掺杂源区在P-掺杂的基础上，在靠近控制栅边缘的一侧又注入N+，使得该注入部分原有的P-掺杂完全被补偿为N+。本发明器件结构采用源区两次不同浓度的掺杂注入，有效地结合了MOSFET导通电流大的特征，提高了器件的开态电流，且自适应地实现了该器件MOSFET和TFET部分的阈值调节。

Description

一种自适应复合机制隧穿场效应晶体管及其制备方法
技术领域
本发明属于CMOS超大集成电路（ULSI）中的场效应晶体管逻辑器件与电路领域，具体涉及一种利用自适应方法有效结合金属-氧化层-硅场效晶体管（MOSFET）电流的隧穿场效应晶体管（TFET）及其制备方法。
背景技术
随着MOSFET的尺寸不断缩小，当进入纳米尺度以后，器件的短沟道效应等负面影响也愈加严重，使得器件关态漏泄电流不断增大。同时，由于传统MOSFET的亚阈值斜率受到热电势的限制无法随着器件尺寸的缩小而同步减小，存在60mV/dec的理论极限，使得泄漏电流随着电源电压的缩小而进一步增大，由此增加了器件功耗。功耗问题如今已经成为限制器件等比例缩小的最严峻的问题之一。
在超低压低功耗领域中，采用新型导通机制而获得超陡亚阈值斜率的器件结构和工艺制备方法成为了近些年大家关注的热点。这些器件由于不受热电势的限制能突破传统MOSFET亚阈值斜率的极限，从而在低功耗器件领域里大放异彩。其中，隧穿场效应晶体管（TFET）因其有很低的泄漏电流，超陡的亚阈值斜率而受到广泛关注。TFET不同于传统MOSFET，其源漏掺杂类型相反，利用栅极控制反向偏置的P-I-N结的带带隧穿实现导通，它能工作在较低电压下，因此适用于低压低功耗领域的应用。但TFET由于受源结隧穿几率和隧穿面积的限制，面临着开态电流小的问题，远远比不上传统MOSFET器件，且TFET存在双极导通效应，极大限制了TFET器件的应用。
发明内容
本发明的目的在于提出一种利用自适应的方法结合MOSFET电流的复合机制隧穿场效应晶体管及其制备方法。该结构能在与现有的CMOS工艺完全兼容的条件下，显著地提高TFET器件的导通电流，同时抑制双极效应，并获得更陡直的亚阈特性。
本发明的技术方案如下：
本发明隧穿场效应晶体管包括一个控制栅，一个栅介质层，一个半导体衬底，一个掺杂源区和一个掺杂漏区，掺杂源区和掺杂漏区分别位于控制栅的两侧，其特征在于，对于N型（或P型）器件，所述掺杂源区由P+（或P-）掺杂区和N-（或N+）掺杂区两部分组成。具体为：对于N型晶体管，漏区由N-（浓度约1×1019~1×1020cm-3）掺杂区构成，源区在N-掺杂的基础上，在靠近控制栅边缘的一侧又注入P+（浓度约1×1020~1×1021cm-3），使得该注入部分原有的N-掺杂完全被补偿为P+，且该部分的两侧和有源区边缘要有一定的间距Lud（间距Lud小于耗尽层宽度，视掺杂浓度而定，小于2μm）。对于P型晶体管，漏区由P-（浓度约1×1019~1×1020cm-3）掺杂区构成，源区在P-掺杂的基础上，在靠近控制栅边缘的一侧又注入N+（浓度约1×1020~1×1021cm-3），使得该注入部分原有的P-掺杂完全被补偿为N+，且该部分的两侧和有源区边缘有一定的间距Lud（间距Lud小于耗尽层宽度，视掺杂浓度而定，小于2μm），如图6所示。
上述隧穿场效应晶体管的制备方法，包括以下步骤：
（1）在半导体衬底上通过浅槽隔离定义有源区；
（2）生长栅介质层；
（3）淀积栅材料，接着光刻和刻蚀，形成控制栅图形；
（4）以控制栅为掩膜，自对准离子注入，形成相同掺杂类型且浓度约1×1019~1×1020cm-3的掺杂漏区和掺杂源区；
（5）光刻暴露出部分与控制栅相连的源掺杂区，以光刻胶及栅为掩膜，离子注入形成另一种掺杂类型的高掺杂源区，浓度约1×1020~1×1021cm-3，然后快速高温热退火激活掺杂杂质；
（6）最后进入常规CMOS后道工序，包括淀积钝化层、开接触孔以及金属化等，即可制得所述的隧穿场效应晶体管，注意源区接触孔的位置需覆盖住源区的两种掺杂杂质。
上述的制备方法中，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅（SOI）或绝缘体上的锗（GOI）。
上述的制备方法中，所述步骤（2）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
上述的制备方法中，所述步骤（2）中的生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
上述的制备方法中，所述步骤（3）中的栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。
本发明的技术效果如下：
一、源区的第二次高掺杂注入区、相对较低掺杂的漏区以及控制栅形成了具有较好性能的非对称TFET结构：一方面，由于源区的第二次是高掺杂注入，能有效地将第一次注入的杂质补偿并形成相反类型杂质，构成了TFET结构，且由于两次注入的杂质类型相反，使得TFET的隧穿结处的浓度梯度由于耗尽作用更加陡直，有利于发生带带隧穿，相比传统TFET能获得更陡直的亚阈值斜率和更高的开态电流；另一方面，漏区的掺杂由第一次自对准注入时形成，使得漏区掺杂浓度相对较低，能有效抑制传统TFET器件的双极效应，抑制双极导通电流。因此，两次不同浓度和不同位置的注入掺杂的设计使得该器件能获得更加陡直的亚阈特性，同时抑制TFET的双极效应。
二、第二次掺杂注入的区域和有源区宽度边缘有一定间距的设计有效地将MOSFET的特点引入到该晶体管中：一方面，在该结构中，未被第二次掺杂注入的源区部分、控制栅和漏区构成了MOSFET结构，因此，在相同的有源区面积下，该器件能得到远高于传统TFET的导通电流；另一方面，由于间距小于耗尽层宽度，使得MOSFET部分源结处的能带被抬高，不利于MOSFET部分的开启，因此在不增加工艺步骤的前提下，通过简单的版图设计能自动调节两者的阈值电压，实现TFET部分比MOSFET先导通，从而保证该器件的亚阈部分受TFET决定，突破传统MOSFET亚阈值斜率的极限。因此，该器件能很好结合传统TFET和MOSFET的优点，具有较好的亚阈特性和较高的开态电流，自适应地实现复合机制的结合。
三、该器件制备工艺简单，制备方法与传统的MOSFET工艺完全兼容，在不增加有源区的面积和工艺复杂度的情况下能大大提高性能。
简而言之，该器件结构采用源区两次不同浓度的掺杂注入且位置上有一定间距的设计，有效地结合了MOSFET导通电流大的特征，提高了器件的开态电流，且自适应地实现了该器件MOSFET和TFET部分的阈值调节。与现有的TFET相比，在同样的工艺条件、同样的有源区尺寸下该器件可以得到更高的导通电流和更低的亚阈值斜率，有望在低功耗领域得到采用，有较高的实用价值。
附图说明
图1是半导体衬底上生长栅介质层并淀积栅材料的工艺步骤示意图；
图2a是光刻并刻蚀后形成的控制栅的器件沿图2b虚线方向的剖面图，图2b是相应的器件俯视图；
图3是自对准离子注入形成相对较低掺杂浓度的源漏区后的器件剖面图；
图4a是光刻暴露出与控制栅相连的部分源区并离子注入形成相反类型的高掺杂源区后的器件沿图4b虚线方向的剖面图，图4b是相应的器件俯视图；
图5是经过后道工序（接触孔，金属化）后的器件沿图4b虚线方向的剖面图；
图6是本发明的自适应复合机制隧穿场效应晶体管的器件俯视图；
图7a是本发明晶体管沿图6中AA’方向的剖面图；
图7b是本发明晶体管沿图6中BB’方向的剖面图，红色虚线标注的部分是被耗尽的掺杂部分；
图中：
1——半导体衬底            2——栅介质层
3——栅                    4——较低掺杂浓度的漏区和源区
5——光刻胶                6——相反类型的高掺杂源区
7——后道工序的钝化层      8——后道工序的金属
具体实施方式
下面通过实例对本发明做进一步说明。需要注意的是，公布实施例的目的在于帮助进一步理解本发明，但是本领域的技术人员可以理解：在不脱离本发明及所附权利要求的精神和范围内，各种替换和修改都是可能的。因此，本发明不应局限于实施例所公开的内容，本发明要求保护的范围以权利要求书界定的范围为准。
本发明制备方法的一具体实例包括图1至图4b所示的工艺步骤：
1、在晶向为（100）的体硅硅片硅衬底1上采用浅槽隔离技术制作有源区隔离层，衬底掺杂浓度为轻掺杂；然后热生长一层栅介质层2，栅介质层为SiO2，厚度为1~5nm；淀积栅材料3，栅材料为掺杂多晶硅层，厚度为150~300nm，如图1所示。
2、光刻出控制栅图形，刻蚀栅材料3直到栅介质层2，如图2a、2b所示。
3、以控制栅3为掩膜进行自对准P-离子注入，形成相对较低掺杂浓度的源漏区4，离子注入的能量为40keV，剂量为1e14，注入杂质为BF2 +，如图3所示。
4、光刻暴露出与控制栅相连的部分源区图形，图形两侧和有源区边缘有一定间距，约为1μm，以光刻胶5和控制栅3为掩膜进行N+离子注入，形成高掺杂N+源区6，离子注入的能量为50keV，剂量为1e15，注入杂质为As+，如图4a、4b所示；进行一次快速高温退火，激活源漏掺杂的杂质。
5、最后进入常规CMOS后道工序，包括淀积钝化层7、开接触孔以及金属化8等，如图5所示，即可制得所述的自适应复合机制隧穿场效应晶体管。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (9)

1.一种隧穿场效应晶体管，包括一个控制栅，一个栅介质层，一个半导体衬底，一个掺杂源区和一个掺杂漏区，掺杂源区和掺杂漏区分别位于控制栅的两侧，其特征在于，对于N型晶体管，掺杂源区在N-掺杂的基础上，在靠近控制栅边缘的一侧又注入P+，使得该注入部分原有的N-掺杂完全被补偿为P+，且P+掺杂区和有源区宽度方向的边缘有间距；对于P型晶体管，掺杂源区在P-掺杂的基础上，在靠近控制栅边缘的一侧又注入N+，使得该注入部分原有的P-掺杂完全被补偿为N+，且N+掺杂区和有源区宽度方向的边缘有间距。
2.如权利要求1所述的隧穿场效应晶体管，其特征在于，对于N型晶体管，掺杂漏区N-的掺杂浓度为1×1019~1×1020cm-3；P+掺杂浓度为1×1020~1×1021cm-3。
3.如权利要求1所述的隧穿场效应晶体管，其特征在于，对于P型晶体管，掺杂漏区P-的掺杂浓度约1×1019~1×1020cm-3；N+的掺杂浓度约1×1020～1×1021cm-3。
4.如权利要求1所述的隧穿场效应晶体管，其特征在于，P+掺杂区或N+掺杂区和有源区宽度方向边缘的间距小于2μm。
5.一种制备如权利要求1所述隧穿场效应晶体管的方法，包括以下步骤：
（1）在半导体衬底上通过浅槽隔离定义有源区；
（2）生长栅介质层；
（3）淀积栅材料，接着光刻和刻蚀，形成控制栅图形；
（4）以控制栅为掩膜，自对准离子注入，形成相同掺杂类型的掺杂漏区和掺杂源区；
（5）光刻暴露出部分与控制栅相连的源掺杂区，以光刻胶及栅为掩膜，在靠近控制栅边缘的一侧离子注入形成另一种掺杂类型的高掺杂源区，然后快速高温热退火激活掺杂杂质；
（6）最后进入常规CMOS后道工序。
6.如权利要求5所述的方法，其特征在于，所述步骤（1）中的半导体衬底材料选自Si、Ge、SiGe、GaAs或其他II-VI，III-V和IV-IV族的二元或三元化合物半导体、绝缘体上的硅或绝缘体上的锗。
7.如权利要求5所述的方法，其特征在于，所述步骤（2）中的栅介质层材料选自SiO2、Si3N4和高K栅介质材料。
8.如权利要求5所述的方法，其特征在于，生长栅介质层的方法选自下列方法之一：常规热氧化、掺氮热氧化、化学气相淀积和物理气相淀积。
9.如权利要求5所述的方法，其特征在于，所述步骤（3）中的栅材料选自掺杂多晶硅、金属钴，镍以及其他金属或金属硅化物。 
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