CN102549741B - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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- CN102549741B CN102549741B CN201180003759.XA CN201180003759A CN102549741B CN 102549741 B CN102549741 B CN 102549741B CN 201180003759 A CN201180003759 A CN 201180003759A CN 102549741 B CN102549741 B CN 102549741B
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- metal column
- semiconductor device
- plate member
- semiconductor element
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- 238000000034 method Methods 0.000 title claims description 41
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- 229910052751 metal Inorganic materials 0.000 claims abstract description 131
- 239000002184 metal Substances 0.000 claims abstract description 131
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- 238000010438 heat treatment Methods 0.000 description 19
- 239000010949 copper Substances 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 14
- 229920005989 resin Polymers 0.000 description 12
- 239000011347 resin Substances 0.000 description 12
- 230000000994 depressogenic effect Effects 0.000 description 11
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- 229910052782 aluminium Inorganic materials 0.000 description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000035882 stress Effects 0.000 description 9
- 230000008646 thermal stress Effects 0.000 description 9
- 239000004411 aluminium Substances 0.000 description 7
- LQBJWKCYZGMFEV-UHFFFAOYSA-N lead tin Chemical compound [Sn].[Pb] LQBJWKCYZGMFEV-UHFFFAOYSA-N 0.000 description 6
- 229910000679 solder Inorganic materials 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
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- 230000007423 decrease Effects 0.000 description 4
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- 239000010959 steel Substances 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000000280 densification Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
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- 238000012858 packaging process Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910052797 bismuth Inorganic materials 0.000 description 1
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- ZUOUZKKEUPVFJK-UHFFFAOYSA-N diphenyl Chemical class C1=CC=CC=C1C1=CC=CC=C1 ZUOUZKKEUPVFJK-UHFFFAOYSA-N 0.000 description 1
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
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Abstract
本发明公开了一种半导体装置及其制造方法。该半导体装置包括:具有通孔(15)的板部件(13)、隔着绝缘性部件(17)固定在通孔上且包括从板部件的上表面突出的突出部的金属柱(16)、固定在突出部上的半导体元件(12)、与半导体元件电连接的引线架(11)、以及覆盖半导体元件(12)且覆盖板部件、金属柱以及引线架的至少一部分的外包装体(14)。板部件的下表面(13b)从外包装体露出。
Description
技术领域
本发明涉及一种半导体元件被封装在外包装体内的半导体装置及其制造方法。
背景技术
近年来,对放置在变频器控制设备等上的半导体元件提出了进一步高密度化和高速化的要求。然而却有可能出现以下不良现象。半导体元件的发热量伴随着半导体元件的高密度化和高速化而增加,半导体元件的工作可靠性下降。因此,封装半导体元件的封装体的散热构造就变得很重要了。具有散热构造的半导体装置例如在专利文献1中有过公开。如图13所示,专利文献1所公开的半导体装置具有放置于其上的半导体元件101的芯片垫子102的背面从封装树脂103露出的散热构造。
具有其他散热构造的半导体装置例如在专利文献2中有过公开。如图14所示,专利文献2所公开的半导体装置所具有的散热构造的具体情况如下:其上放置有发热量较大的半导体元件201的芯片垫202与散热部件203连接,散热部件203的一部分自封装半导体元件201的封装树脂204露出。
除此以外,还有例如专利文献3中所公开的半导体装置。在专利文献3所公开的半导体装置中,半导体元件放置在由第一金属部件和贯通第一金属部件且由铜制成的第二金属部件构成的散热部件上,其中第一金属部件由铁制成。该半导体装置具有半导体元件被封装树脂封装而让散热部件的一部分露出的构造。
然而,若使这些现有的半导体装置工作,半导体元件就会因发热而温度上升,由于热膨胀系数的不同而在芯片垫或散热部件与半导体元件之间产生热应力。这是由于芯片垫的热变形量比半导体元件的热变形量大而引起的。半导体装置还会由于该热应力而产生翘曲。其结果是,不仅半导体元件的特性会发生变化,半导体元件等上还会产生龟裂,半导体装置的可靠性会下降。
具有用来降低半导体元件上所产生的热应力之结构的半导体装置例如在专利文献4中有过公开。专利文献4中所公开的半导体装置的具体情况如下:通过用柱状部件支撑半导体元件的一表面的一部分,则与由基板等支撑半导体元件的一个面的全部之情形相比,在半导体元件上产生的热应力就会减小。
利用这样的结构降低在半导体元件上产生的热应力且能够将从半导体元件发出的热释放到外部的半导体装置例如在专利文献5中有过公开。如图15所示,专利文献5中所公开的半导体装置,在由铝(Al)制成的金属基板301上隔着绝缘层302和锡铅合金焊料303具有由铜(Cu)制成的多个柱部305以及板部304构成的散热部件306。在多个柱部305上隔着锡铅合金焊料307安装有半导体元件308。从半导体元件308发出的热经锡铅合金焊料307从柱部305传递给板部304,再经绝缘层302从金属基板301向外部散去。这里,构成散热部件306的铜和构成金属基板301的铝的热膨胀系数比构成半导体元件308的二氧化硅(SiO2)的大。因此,如果三者的温度上升,则热应力就会由于热变形量的不同而加在了连接半导体元件308和柱部305的锡铅合金焊料307上,而有可能引起龟裂和断裂。在专利文献5中,因为用铜线制成柱部305而使柱部305的强度比锡铅合金焊料307小,所以柱部305以它已弯曲的状态支撑着半导体元件308。其结果是,几乎不会产生热应力,从而能够防止半导体元件308因热应力而翘曲。
专利文献1:日本公开特许公报特开平11-251494号公报
专利文献2:日本公开特许公报特开平4-168753号公报
专利文献3:日本公开特许公报特开平7-211818号公报
专利文献4:日本公开特许公报特开平5-218133号公报
专利文献5:日本公开特许公报特开2004-87612号公报
发明内容
-发明要解决的技术问题-
然而,专利文献5中所公开的半导体装置的具体情况是这样的,从半导体元件发出的热经散热部件和形成在金属基板的几乎整个上表面上的绝缘层散向半导体装置外部。因此,专利文献5中所公开的半导体装置有散热效果下降的可能性。其结果是,会出现半导体装置的可靠性下降的情况。也就是说,就专利文献5中公开的半导体装置而言,当想要降低在半导体元件周围产生的热应力时,则也会使散热效果下降。
本发明的目的在于:获得一种能够降低由于从半导体元件发出的热而产生的应力、散热效果高且可靠性高的半导体装置。
-用以解决技术问题的技术方案-
为达成上述目的,本发明所涉及的第一半导体装置包括:具有通孔的板部件、隔着绝缘性部件固定在所述通孔上并包括从所述板部件的一表面突出的突出部的金属柱、固定在所述突出部上的半导体元件、与所述半导体元件电连接的引线架、以及覆盖所述半导体元件且覆盖所述板部件、所述金属柱以及所述引线架的至少一部分的外包装体。所述板部件的另一表面从所述外包装体露出。
为达成上述目的,本发明所涉及的第二半导体装置包括:具有通孔的板部件、隔着绝缘性部件固定在所述通孔上并包括从所述板部件的一表面突出的突出部的金属柱、固定在所述突出部上的半导体元件、与所述半导体元件电连接的引线架、固定在所述板部件的另一表面上的散热部件、以及覆盖所述半导体元件且覆盖所述板部件、所述金属柱、所述散热部件以及所述引线架的至少一部分的外包装体;所述散热部件的一部分从所述外包装体露出。
为达成上述目的,本发明所涉及的第一半导体装置的制造方法包括以下工序:使所述金属柱的一部分作为突出部从所述板部件的一表面突出地隔着绝缘性部件将金属柱插入形成在板部件上的通孔内的工序、将半导体元件固定在所述突出部上的工序、使所述半导体元件与引线架电连接的工序、以及形成覆盖所述半导体元件且使所述板部件的另一表面露出地覆盖所述板部件和所述引线架的至少一部分的外包装体的工序。
为达成上述目的,本发明所涉及的第二半导体装置的制造方法包括以下工序:使所述金属柱的一部分作为突出部从所述板部件的一表面突出地隔着绝缘性部件将金属柱插入形成在板部件上的通孔内的工序、将半导体元件固定在所述突出部上的工序、将散热部件固定在所述板部件的另一表面上的工序、使所述半导体元件与引线架电连接的工序、以及形成覆盖所述半导体元件且使所述散热部件的一部分露出地覆盖所述板部件、所述散热部件以及所述引线架的至少一部分的外包装体的工序。
-发明的效果-
根据本发明所涉及的半导体装置及其制造方法,能够获得一种能够降低由于从半导体元件发出的热而产生的应力、散热效果高且可靠性高的半导体装置。
附图说明
图1是示出本发明第一实施方式所涉及的半导体装置的剖视图。
图2是示出本发明第一实施方式所涉及的半导体装置、放大示出图1中的A部的剖视图。
图3是示出本发明第一实施方式所涉及的半导体装置、放大示出图1中的A部的俯视图。
图4是示出本发明第一实施方式所涉及的半导体装置的制造方法中的一工序的剖视图。
图5是示出本发明第一实施方式所涉及的半导体装置的制造方法中的一工序的剖视图。
图6是示出本发明第一实施方式所涉及的半导体装置的制造方法中的一工序的剖视图。
图7是示出本发明第一实施方式的一变形例所涉及的半导体装置的制造方法中的一工序的剖视图。
图8是示出本发明第一实施方式的一变形例所涉及的半导体装置的制造方法中的一工序的剖视图。
图9示出本发明第一实施方式的一变形例所涉及的半导体装置的制造方法中的一工序的剖视图。
图10是示出本发明第二实施方式所涉及的半导体装置的剖视图。
图11是示出本发明第三实施方式所涉及的半导体装置的剖视图。
图12是示出本发明第三实施方式所涉及的半导体装置的制造方法中的一工序的剖视图。
图13是示出第一现有例中的半导体装置的剖视图。
图14是示出第二现有例中的半导体装置的剖视图。
图15是示出第三现有例中的半导体装置的剖视图。
-符号说明-
11、51-引线架;12-半导体元件;13-芯片垫;13a、16a、26a、70a-上表面;13b、16b、26b、53b、70b-下表面;14-外包装体;15、55-通孔;16、26-金属柱;17-绝缘性部件;19-焊料;20-金属部件;21、22-平缘;30-插入杆;31-凸部;31a-顶面;31b-侧面;32-凹部;53-散热板;61-绝缘性薄板;70-散热部件。
具体实施方式
(第一实施方式)
参照图1~图3对本发明第一实施方式所涉及的半导体装置进行说明。
如图1和图2所示,本实施方式所涉及的半导体装置至少包括:半导体元件12、具有芯片垫13且芯片垫13又具有通孔15的引线架11、隔着绝缘性部件17嵌合在通孔15内的圆柱状金属柱16以及外包装体14。芯片垫13是由例如铜和铜合金制成、厚度为400μm~500μm左右的板部件。芯片垫13上形成有从芯片垫13的上表面13a通到其下表面13b的圆柱状通孔15。通孔15上隔着绝缘性部件17固定有由铜和铜合金等制成的圆柱状金属柱16。金属柱16的固定,是例如隔着绝缘性部件17将金属柱16嵌合在通孔15中而实现的。此外,金属柱16具有从芯片垫13的上表面13a突出的突出部。在金属柱16的突出部的上表面(突出面)16a隔着焊料19固定有半导体元件12。半导体元件12的固定,是例如用焊料19将半导体元件12焊合在金属柱16的突出部的上表面16a上而实现的。下面,作为固定方法之一例使用焊合。焊料例如是锡(Sn)银(Ag)铋(Bi)系锡铅合金焊料。金属柱16的突出部的上表面(突出面)是与半导体元件12相对的面。
此外,板部件之一例即芯片垫13的上表面13a是板部件的一表面之一例;芯片垫13的下表面13b是板部件的另一表面之一例。
这里,如图2和图3所示,一个半导体元件12在其中央部位由一个金属柱16支撑着。此外,为简化附图,图3中省略了焊料19和外包装体14。半导体元件12的厚度例如为200μm,金属柱16的直径例如为3mm。半导体元件12上形成有焊垫(未图示),该焊垫和由例如铜制成的引线架11利用金属细线即金属部件20而电连接。半导体元件12和包括芯片垫13的引线架11的一部分被例如封装树脂即外包装体14封装起来,芯片垫13的下表面13b从外包装体14露出。
此外,绝缘性部件17由例如低融点玻璃和氧化铝(Al2O3)粉末的混合物制成。因为绝缘性部件17含有氧化铝,所以与普通的低融点玻璃相比,绝缘性部件17的导热性高。
金属部件20例如是铝线。而且,不仅可以使用铝线,还可以使用铝带状件或铜板状件。因为与铝线相比,铝带状件和铜板状件的横截面积大,布线电阻值小,所以用铝带状件和铜板状件能够降低功耗。
外包装体14由例如联苯类或甲酚酚醛类环氧树脂等热固性树脂制成的封装树脂制成。通过用外包装体14封装半导体元件12、金属部件20以及引线架11的一部分,便能够使引线架11和半导体元件12一体化。而且还能够用外包装体14保护半导体元件12。
半导体元件12,能够使用例如绝缘栅极型双极晶体管(insulated gatebipolar transistor:IGBT)或功率金属氧化膜型场效应晶体管(power metaloxide semiconductor field effect transistor:功率MOSFET)。在本实施方式中,半导体元件12是内置有二极管的横向导电结构功率MOSFET。半导体元件12由于在大电流下进行高速开关动作而发热,该热传递给芯片垫13,芯片垫13的温度上升。与构成半导体元件12的硅(Si)等半导体材料相比,构成芯片垫13的铜等金属材料的热膨胀系数大,所以芯片垫13的热变形量比半导体元件12的热变形量大。其结果是,会在半导体元件12和芯片垫13的连接部产生很大的应力。在本实施方式所涉及的半导体装置中,支撑半导体元件12的金属柱16的上表面16a的表面积比半导体元件12的背面的表面积小。也就是说,因为半导体元件12和芯片垫13经金属柱16仅与半导体元件12的一部分相连接,所以能够使在半导体元件12和芯片垫13的连接部产生的应力减小。
在本实施方式所涉及的半导体装置中,在半导体元件12和芯片垫13之间的间隙内填充有是外包装体14的封装树脂。通过这样填充封装树脂,就能够使半导体元件12和芯片垫13的紧密接触性更加牢固,从而能够防止来自外部的水分等浸入。
因为封装树脂形成为将半导体元件12上下夹住,所以在填充封装树脂之际能够确保在半导体元件12上产生的压力的均匀性。其结果是,在本实施方式所涉及的半导体装置中,能够使在半导体元件12上产生的残余变形减小。在本实施方式中,因为仅使用了一根金属柱16,所以很容易地就能够将封装树脂填充在半导体元件12和芯片垫13之间的间隙里。
因为金属柱16支撑半导体元件12的中央部位,所以封装树脂即外包装体14就是以金属柱16为中心填充在半导体元件12和芯片垫13之间的间隙里。其结果是,能够使在半导体元件12上产生的压力更加均匀。
本实施方式所涉及的半导体装置,能够经金属柱16和含氧化铝的绝缘性部件17以及是封装树脂的外包装体14将从半导体元件12发出的热从芯片垫13的下表面一侧放出。因此,与现有技术中的半导体装置那样在基板的整个上表面形成绝缘层的结构相比,本实施方式的半导体装置具有较高的散热性。
下面,对第一实施方式所涉及的半导体装置中的半导体元件12和金属柱16的连接部的构造进行详细的说明。
如图2所示,金属柱6隔着绝缘性部件17嵌合在芯片垫13的通孔15内,其一部分(突出部)从芯片垫13的上表面13a突出。这里,金属柱16的突出部的高度例如为70μm~100μm。金属柱16的与上表面16a相反一侧的下表面16b位于比芯片垫13的下表面13b更靠上的位置。
绝缘性部件17设置为使至少金属柱16的上表面16a露出。也就是说,通过使绝缘性部件17形成在金属柱16的底面、通孔15的壁面以及金属柱16的侧面之间,将金属柱16和芯片垫13电绝缘。因此,在本实施方式中,即使让半导体元件12以大电流工作,在芯片垫13中也不会有电流流动,从而能够防止半导体元件12的误操作。
在金属柱16的下表面16b一侧的绝缘性部件17和通孔15的壁面的连接部形成有绝缘性部件17的平缘22。同样,在芯片垫13的上表面13a上通孔15的周缘部也形成有绝缘性部件17的平缘21。利用这些平缘21、22能够使金属柱16和芯片垫13的连接强度更大,连接更牢固。
这里,如果平缘22向通孔15的外部流出,则会在芯片垫13的下表面13b产生台阶。在芯片垫13的下表面13b产生台阶以后,则在将本实施方式所涉及的半导体装置安装在其他装置等上之际会产生摇晃等问题。因此,如上所述,优选将金属柱16的下表面16b布置在比芯片垫13的下表面13b更靠上的上侧位置(图2中纸面上侧),且将从芯片垫13的下表面13b到覆盖金属柱16的下表面16b的绝缘性部件17的下表面的距离设定在约10μm以上。
优选,在金属柱16的上表面16a形成凹状的凹陷部(凹部)。该上表面16a上的凹陷部的曲率半径例如为10mm,凹陷部的深度例如为10μm~20μm。有了这样的凹陷部以后,在使焊料19熔化之际,就能够防止焊料19从金属柱16的上表面16a流出到芯片垫13上。而且,即使焊料19已从金属柱16的上表面16a流出,也能够利用形成在金属柱16和芯片垫13的上表面13a之间的绝缘性部件17的平缘21防止半导体元件12和芯片垫13之间的短路。这里,绝缘性部件17形成为覆盖通孔15的周缘部。
此外,在本实施方式的半导体装置中,在芯片垫13上设置有通孔15,但除此以外,还可以不在芯片垫13上形成通孔15,而是在芯片垫13上形成凹部。不过,如果将金属柱嵌合在凹部内,就有可能因为凹部内存在空气而在绝缘性部件17内形成气泡,所以优选在芯片垫13上设置通孔15。
根据本实施方式所涉及的半导体装置,能够获得一种能够降低由于从半导体元件12发出的热而产生的应力、散热效果高且可靠性高的半导体装置。
接下来,参照图4~图6对本实施方式所涉及的半导体装置的制造方法进行说明。
本实施方式所涉及的半导体装置的制造方法包括引线架形成工序、芯片垫加工工序、芯片焊接(die bond)工序、线焊工序、注塑工序以及引线加工工序。这里,因为引线架形成工序、芯片焊接工序、线焊工序、注塑工序以及引线加工工序都是公知的,所以省略对这些工序的说明,仅对芯片垫加工工序做详细的说明。
首先,如图4所示,将覆盖通孔15的绝缘性部件17放置在已形成有圆柱状通孔15的板部件即芯片垫13的上表面13a。这里,绝缘性部件17是一个直径比通孔15的开口直径(例如3mm)大的圆板状部件。也就是说,绝缘性部件17的面积比通孔15的开口面积大。此外,优选绝缘性部件17的直径大小为通孔15的开口直径和通孔15的深度(芯片垫13的厚度)之和那么大。通过使用这样的大直径绝缘性部件17,则在后工序中就能够使绝缘性部件17可靠地位于金属柱16和芯片垫13之间。
接着,相对于通孔15将例如直径3mm的圆柱状金属柱16的下表面16b定好位。这里,因为金属柱16是利用例如冲孔加工形成的,所以会在金属柱16的上表面16a一侧产生毛刺。在上表面16a上形成有中央部位比外周部位凹陷的凹陷部(凹部)。该上表面16a上的凹陷部(凹部)的曲率半径例如为10mm,深度例如为10μm~20μm。
接着,如图5所示,使金属柱16的下表面16b紧紧地顶在绝缘性部件17上,对绝缘性部件17加热且将金属柱16插入通孔15中。此时,将绝缘性部件17的温度保持在其软化温度(约300℃)以上且熔融温度(约350℃)以下。在将金属柱16插入通孔15内之际,绝缘性部件17是一边弯曲一边与金属柱16一起被插入通孔15内。能够想到的加热绝缘性部件17而使其软化的方法例如有:激光照射绝缘性性部件17的方法或加热芯片垫13的方法。此时,为使绝缘性部件17稳定地变形,优选通过加热金属柱16来间接地加热绝缘性部件17。
这里,在将金属柱16插入通孔15之际,优选保持一种金属柱16的上部位于比芯片垫13上的绝缘性部件17还在上的(图5中纸面上侧)位置之状态。也就是说,优选不将金属柱16的上部插入到比芯片垫13的上表面13a上的绝缘性部件17更靠下的(图5中纸面下侧)位置。通过这样插入金属柱16,则在后工序中使绝缘性部件17熔化之际能够防止绝缘性部件17进入金属柱16的上表面(突出面)16a的凹陷部内。
接下来,如图6所示,将绝缘性部件17加热到其熔融温度(约350℃)以上而使其熔化。由此在芯片垫13的上表面13a上通孔15的周缘部形成平缘(fillet)21,在金属柱16的下表面16b一侧的绝缘性部件17和通孔15的壁面的连接部形成平缘22,而让金属柱16嵌合在通孔15中。
利用以上工序加工本实施方式所涉及的半导体装置的芯片垫13。
之后,再进行芯片焊接工序、线焊工序、注塑工序以及引线加工工序后,即能够制造出本实施方式所涉及的半导体装置。
此外,在需要其他装置等和半导体元件12背面导通的导通部位的情况下,让金属柱16的一部分从中央部位设置有穴部的绝缘性部件17露出后,再进一步从外包装体14露出(突出)来形成导通部位即可。不过,在该情况下,因为绝缘性部件17固定在已使之露出的金属柱16上的可能性很高,所以优选另外进行去掉金属柱16的露出部上的绝缘性部件17的工序。
根据本发明第一实施方式所涉及的半导体装置的制造方法,即能够制造出能够降低由于从半导体元件发出的热而产生的应力、散热效果高且可靠性高的半导体装置。
(第一实施方式的一变形例)
在第一实施方式中,是将事先在上表面16a上形成有凹陷部(凹部)的金属柱16插入通孔15内。但除此以外,还可以在将金属柱16插入通孔15的同时,在金属柱16的上表面上形成凹陷部。下面,参照图7~图9对采用了在插入的同时形成凹陷部之方法的本发明第一实施方式的一变形例所涉及的半导体装置的制造方法进行说明。在本变形例中,简化或者省略说明与第一实施方式相同的工序,对不同之处做详细的说明。
如图7所示,本变形例的芯片垫加工工序中,用在端部的中央部位具有凸部31的插入杆30将金属柱26插入芯片垫13的通孔15内。此外,凸部31的在突出方向(图7中纸面上下方向)上的长度例如为10μm~20μm,凸部31的顶面31a的直径(图7中纸面左右方向上的长度)例如为1mm。凸部31的侧面31b相对于与顶面31a垂直的方向倾斜,该倾斜角例如为45°。还有,在本变形例中,与第一实施方式不同,不需要在金属柱26的上表面26a形成凹状的凹陷部,上表面26a可以是平的。
首先,如图7所示,覆盖芯片垫13的通孔15地将绝缘性部件17放置在芯片垫13的上表面13a。接下来,相对于通孔15将金属柱26的下表面26b定好位。
接下来,如图8所示,使设置在插入杆30上的凸部31紧紧地顶在金属柱26的上表面26a上,加热绝缘性部件17且将金属柱26插入通孔15内。此时,将绝缘性部件17的温度保持在其软化温度(约300℃)以上且熔融温度(约350℃)以下。在将金属柱26插入通孔15之际,绝缘性部件17是一边弯曲一边与金属柱26一起被插入通孔15内。
接下来,如图9所示,将绝缘性部件17加热到熔融温度(约350℃)以上使其熔化,由此而在芯片垫13的上表面13a上通孔15的周缘部形成平缘21,在金属柱26的下表面26b一侧绝缘性部件17和通孔15壁面的连接部形成平缘22,使金属柱26嵌合在通孔15内。接着,从金属柱26中取出插入杆30,来在金属柱26的上表面26a上形成中央部位比其周围部位凹陷的凹部32。这里,凹部32的深度例如为10μm~20μm,凹部32的底面的直径例如为1mm。凹部32的侧面即倾斜面的倾斜角例如为45度。
在本变形例中,即使金属柱26的上表面26a是平的,也能够用具有凸部31的插入杆30在上表面26a上形成凹部32。因此,在使用上表面很平的金属柱的情况下,在使焊料19熔化之际也能够防止焊料19从金属柱26的上表面26a流出到芯片垫13上。
在本变形例中,使插入杆30上的凸部31的侧面的倾斜角例如为45度。但除此以外,角度既可以比该角度大,又可以比该角度小。只要是能够防止焊料19从凹部32流出的角度即可。
根据本发明第一实施方式的一变形例所涉及的半导体装置的制造方法,在使用上表面很平的金属柱的情况下,也能够制造出能够降低由于从半导体元件发出的热而产生的应力、散热效果高且可靠性高的半导体装置。
(第二实施方式)
下面,参照图10对本发明第二实施方式所涉及的半导体装置进行说明。在本实施方式中,用同一符号表示与第一实施方式相同的部件,说明省略。
如图10所示,第二实施方式所涉及的半导体装置,不是在芯片垫上设置通孔55,而是在散热板53上设置通孔55,且金属柱16嵌合在该通孔55内,这几点与第一实施方式所涉及的半导体装置不同。有了该结构,本实施方式所涉及的半导体装置上就能够放置发热量更大的半导体元件。
具体而言,本实施方式的半导体装置至少包括引线架51、半导体元件12、具有通孔55的板部件即散热板53、隔着绝缘性部件17与通孔55嵌合的金属柱16以及外包装体14。引线架51由导热性较高的材料制成,包括多条引线。由导热性较高的材料制成的引线架51由例如铜(Cu)制成。被外包装体14封装的引线架51上的多条引线的端部从外包装体14内向外突出。散热板53由导热性较高的金属制成。由导热性较高的金属制成的散热板53是由例如铜(Cu)和铝(Al)制成。在散热板53上形成有绝缘性薄板61,引线架51隔着绝缘性薄板61固定在散热板53上。
在本实施方式中,设置有隔着绝缘性部件17与散热板53上的通孔55嵌合的金属柱16,在金属柱16的上表面16a上固定有半导体元件12。半导体元件12、散热板53以及引线架51的一部分被外包装体14封装,散热板53的下表面53b从外包装体14露出。也就是说,散热板53的一部分从外包装体14露出。
在本实施方式中,和第一实施方式一样,支撑半导体元件12的金属柱16的上表面16a的表面积比半导体元件12的背面的表面积小。也就是说,因为半导体元件12和散热板53通过金属柱16与半导体元件12的一部分相连接,所以能够降低在半导体元件12和散热板53的连接部产生的应力。
在本发明第二实施方式中使用了由导热性较高的材料制成的散热板53,因此能够获得具有较高的散热性的半导体装置。
此外,本实施方式所涉及的半导体装置的制造方法特别是将金属柱嵌合在散热板上的通孔里的方法,与第一实施方式中的将金属柱嵌合在芯片垫上的通孔里的方法是同一个方法,说明省略。
(第三实施方式)
下面,参照图11对本发明第三实施方式所涉及的半导体装置进行说明。在本实施方式中,用同一符号表示与第一实施方式相同的部件,说明省略。
如图11所示,与第一实施方式所涉及的半导体装置相比,本实施方式所涉及的半导体装置,在板部件即芯片垫13的下表面13b上固定有由例如铜或铝制成、导热性较高的散热部件70。而且,在本实施方式所涉及的半导体装置中,散热部件70的下表面(图11中纸面下侧的面)70b从外包装体14露出。这里,散热部件的下表面70b是一个位于与固定在芯片垫13上的散热部件70的上表面(图11中纸面上侧的面)70a相反一侧的面。在本实施方式中使用了导热性较高的散热部件70,所以根据本实施方式能够收到比第一实施方式更高的散热效果。
接下来,参照图12对本实施方式所涉及的半导体装置的制造方法进行说明。
与第一实施方式所涉及的半导体装置的制造方法相比,如图12所示,在本实施方式所涉及的半导体装置的制造方法中增加了将散热部件70固定在芯片垫13的下表面13b上的工序。该固定工序只要在利用外包装体14对半导体元件12等进行封装以前进行即可。例如,该固定工序可以在图4~图6所示的将金属柱16嵌合在通孔15中的工序之前进行,还可以在已将金属柱16嵌合在通孔15中以后且利用外包装体14进行封装的封装工序以前进行。
在利用外包装体14进行封装的封装工序中,形成使散热部件70的下表面70b露出的外包装体14。
-产业实用性-
本发明所涉及的半导体装置及其制造方法能够降低由于从半导体元件发出的热而产生的应力、散热效果高。所以本发明特别是对半导体元件被外包装体封装的半导体装置及其制造方法很有用。
Claims (16)
1.一种半导体装置,其特征在于:
该半导体装置包括:
具有通孔的板部件、
隔着绝缘性部件固定在所述通孔上并包括从所述板部件的一表面突出的突出部的金属柱、
固定在所述突出部上的半导体元件、
与所述半导体元件电连接的引线架、以及
覆盖所述半导体元件且覆盖所述板部件、所述金属柱以及所述引线架的至少一部分的外包装体;
所述板部件的另一表面从所述外包装体露出,
所述金属柱在所述突出部的与所述半导体元件相向的面上具有凹部。
2.一种半导体装置,其特征在于:
该半导体装置包括:
具有通孔的板部件、
隔着绝缘性部件固定在所述通孔上并包括从所述板部件的一表面突出的突出部的金属柱、
固定在所述突出部上的半导体元件、
与所述半导体元件电连接的引线架、
固定在所述板部件的另一表面上的散热部件、以及
覆盖所述半导体元件且覆盖所述板部件、所述金属柱、所述散热部件以及所述引线架的至少一部分的外包装体;
所述散热部件的一部分从所述外包装体露出,
所述金属柱在所述突出部的与所述半导体元件相向的面上具有凹部。
3.根据权利要求1或2所述的半导体装置,其特征在于:
所述凹部由底面和与所述底面倾斜的倾斜面构成。
4.根据权利要求1或2所述的半导体装置,其特征在于:
在所述板部件的一表面上所述通孔的周缘部形成有所述绝缘性部件的平缘。
5.根据权利要求1或2所述的半导体装置,其特征在于:
在所述通孔的壁面和所述金属柱的连接部形成有所述绝缘性部件的平缘。
6.根据权利要求1或2所述的半导体装置,其特征在于:
所述引线架隔着绝缘性薄板固定在所述板部件上。
7.根据权利要求1或2所述的半导体装置,其特征在于:
所述板部件是芯片垫。
8.根据权利要求1或2所述的半导体装置,其特征在于:
所述金属柱为1根,
在所述1根金属柱上固定有一个所述半导体元件。
9.一种半导体装置的制造方法,其特征在于:
该半导体装置的制造方法包括以下工序:
使金属柱的一部分作为突出部从板部件的一表面突出地隔着绝缘性部件将所述金属柱插入形成在所述板部件上的通孔内的工序、
将半导体元件固定在所述突出部上的工序、
使所述半导体元件与引线架电连接的工序、以及
形成覆盖所述半导体元件且使所述板部件的另一表面露出地覆盖所述板部件和所述引线架的至少一部分的外包装体的工序。
10.一种半导体装置的制造方法,其特征在于:
该半导体装置的制造方法包括以下工序:
使金属柱的一部分作为突出部从板部件的一表面突出地隔着绝缘性部件将所述金属柱插入形成在所述板部件上的通孔内的工序、
将半导体元件固定在所述突出部上的工序、
将散热部件固定在所述板部件的另一表面上的工序、
使所述半导体元件与引线架电连接的工序、以及
形成覆盖所述半导体元件且使所述散热部件的一部分露出地覆盖所述板部件、所述散热部件以及所述引线架的至少一部分的外包装体的工序。
11.根据权利要求9或10所述的半导体装置的制造方法,其特征在于:
在隔着所述绝缘性部件将所述金属柱插入所述通孔内的工序中,使用在顶端具有凸部的插入杆使所述凸部紧紧地顶在所述金属柱上而将所述金属柱插入所述通孔内。
12.根据权利要求11所述的半导体装置的制造方法,其特征在于:
所述插入杆上的所述凸部的侧面是倾斜面。
13.根据权利要求9或10所述的半导体装置的制造方法,其特征在于:
在隔着所述绝缘性部件将所述金属柱插入所述通孔内的工序中,和所述金属柱一起插入面积比所述通孔的开口面积大的所述绝缘性部件。
14.根据权利要求9或10所述的半导体装置的制造方法,其特征在于:
在隔着所述绝缘性部件将所述金属柱插入所述通孔内的工序中,使所述金属柱的一部分位于比所述板部件的一表面上的所述绝缘性部件更靠上的位置地将所述金属柱插入所述通孔内。
15.根据权利要求9或10所述的半导体装置的制造方法,其特征在于:
在隔着所述绝缘性部件将所述金属柱插入所述通孔内的工序中,在所述板部件的一表面上所述通孔的周缘部形成所述绝缘性部件的平缘。
16.根据权利要求9或10所述的半导体装置的制造方法,其特征在于:
在隔着所述绝缘性部件将所述金属柱插入所述通孔内的工序中,在所述通孔的壁面和所述金属柱的连接部形成所述绝缘性部件的平缘。
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PCT/JP2011/004126 WO2012023236A1 (ja) | 2010-08-20 | 2011-07-21 | 半導体装置及びその製造方法 |
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EP (1) | EP2608257B1 (zh) |
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US10083899B2 (en) * | 2017-01-23 | 2018-09-25 | Infineon Technologies Ag | Semiconductor package with heat slug and rivet free die attach area |
US10269678B1 (en) * | 2017-12-05 | 2019-04-23 | Nxp Usa, Inc. | Microelectronic components having integrated heat dissipation posts, systems including the same, and methods for the fabrication thereof |
US11133241B2 (en) * | 2019-06-28 | 2021-09-28 | Stmicroelectronics, Inc. | Semiconductor package with a cavity in a die pad for reducing voids in the solder |
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Publication number | Publication date |
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EP2608257B1 (en) | 2017-08-30 |
CN102549741A (zh) | 2012-07-04 |
EP2608257A1 (en) | 2013-06-26 |
US20120161302A1 (en) | 2012-06-28 |
EP2608257A4 (en) | 2014-10-01 |
JPWO2012023236A1 (ja) | 2013-10-28 |
WO2012023236A1 (ja) | 2012-02-23 |
JP5412532B2 (ja) | 2014-02-12 |
US8686545B2 (en) | 2014-04-01 |
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