CN102446547B - 交点自对准的可编程存储装置 - Google Patents
交点自对准的可编程存储装置 Download PDFInfo
- Publication number
- CN102446547B CN102446547B CN201110043837.0A CN201110043837A CN102446547B CN 102446547 B CN102446547 B CN 102446547B CN 201110043837 A CN201110043837 A CN 201110043837A CN 102446547 B CN102446547 B CN 102446547B
- Authority
- CN
- China
- Prior art keywords
- storage
- storage array
- word
- programmable
- access device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000008859 change Effects 0.000 title abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 56
- 238000003860 storage Methods 0.000 claims description 197
- 239000000463 material Substances 0.000 claims description 77
- 239000000758 substrate Substances 0.000 claims description 56
- 238000009413 insulation Methods 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 23
- 238000000926 separation method Methods 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 14
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 6
- 229920005591 polysilicon Polymers 0.000 abstract description 6
- 229910021332 silicide Inorganic materials 0.000 description 33
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 32
- 239000012782 phase change material Substances 0.000 description 23
- 239000012071 phase Substances 0.000 description 21
- 229910052581 Si3N4 Inorganic materials 0.000 description 20
- 238000005516 engineering process Methods 0.000 description 20
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 20
- 238000005530 etching Methods 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 238000000059 patterning Methods 0.000 description 15
- 239000007772 electrode material Substances 0.000 description 14
- 229910045601 alloy Inorganic materials 0.000 description 13
- 239000000956 alloy Substances 0.000 description 13
- 238000005240 physical vapour deposition Methods 0.000 description 13
- 230000007704 transition Effects 0.000 description 13
- 229910052798 chalcogen Inorganic materials 0.000 description 12
- 150000001787 chalcogens Chemical class 0.000 description 12
- 238000000151 deposition Methods 0.000 description 12
- 230000008021 deposition Effects 0.000 description 12
- 238000002347 injection Methods 0.000 description 12
- 239000007924 injection Substances 0.000 description 12
- 239000003989 dielectric material Substances 0.000 description 11
- 230000002093 peripheral effect Effects 0.000 description 10
- 238000011049 filling Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 238000002955 isolation Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 239000005380 borophosphosilicate glass Substances 0.000 description 7
- 150000004770 chalcogenides Chemical class 0.000 description 7
- 230000006698 induction Effects 0.000 description 7
- 230000003647 oxidation Effects 0.000 description 7
- 238000007254 oxidation reaction Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 5
- 229910052738 indium Inorganic materials 0.000 description 5
- 150000004767 nitrides Chemical class 0.000 description 5
- 230000009467 reduction Effects 0.000 description 5
- 229910052714 tellurium Inorganic materials 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 4
- 229910052787 antimony Inorganic materials 0.000 description 4
- 230000005055 memory storage Effects 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 239000011232 storage material Substances 0.000 description 4
- -1 sulphur compound Chemical class 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 238000000137 annealing Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000008025 crystallization Effects 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- XZWYZXLIPXDOLR-UHFFFAOYSA-N metformin Chemical compound CN(C)C(=N)NC(N)=N XZWYZXLIPXDOLR-UHFFFAOYSA-N 0.000 description 3
- 239000010955 niobium Substances 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910005872 GeSb Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 2
- 239000005864 Sulphur Substances 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- GDKWXCWTFCPDFQ-UHFFFAOYSA-N [Si].OP(O)(O)=O Chemical compound [Si].OP(O)(O)=O GDKWXCWTFCPDFQ-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 238000013459 approach Methods 0.000 description 2
- 238000003491 array Methods 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 239000003792 electrolyte Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 230000000149 penetrating effect Effects 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- VDNSGQQAZRMTCI-UHFFFAOYSA-N sulfanylidenegermanium Chemical compound [Ge]=S VDNSGQQAZRMTCI-UHFFFAOYSA-N 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 229960005196 titanium dioxide Drugs 0.000 description 2
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 2
- 229910015802 BaSr Inorganic materials 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910003321 CoFe Inorganic materials 0.000 description 1
- 229910019236 CoFeB Inorganic materials 0.000 description 1
- 229910052692 Dysprosium Inorganic materials 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 description 1
- 229910018279 LaSrMnO Inorganic materials 0.000 description 1
- 241000877463 Lanio Species 0.000 description 1
- 229910016629 MnBi Inorganic materials 0.000 description 1
- 229910016964 MnSb Inorganic materials 0.000 description 1
- 229910001245 Sb alloy Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- 229910001215 Te alloy Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- YMVZSICZWDQCMV-UHFFFAOYSA-N [O-2].[Mn+2].[Sr+2].[La+3] Chemical compound [O-2].[Mn+2].[Sr+2].[La+3] YMVZSICZWDQCMV-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910000424 chromium(II) oxide Inorganic materials 0.000 description 1
- 230000001149 cognitive effect Effects 0.000 description 1
- 238000004590 computer program Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 229910002075 lanthanum strontium manganite Inorganic materials 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002105 nanoparticle Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011946 reduction process Methods 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000013049 sediment Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000007784 solid electrolyte Substances 0.000 description 1
- 238000001228 spectrum Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Memories (AREA)
Abstract
本发明公开了一种可编程存储装置。该可编程存储阵列中,相变存储单元是在存取装置处与在位线与字线的交点处自对准。该制作可编程存储阵列的方法中,使用线掩模以定义位线和另一线掩模以定义字线,前段工艺(FEOL)存储单元是在同一层如同多晶硅栅,位线与字线在该装置上相交,且该存储阵列存储单元形成在位线与字线的相交处。本发明可以增加在存储单元阵列内的存储单元的密度,减少存储装置的制造的工艺成本。
Description
技术领域
本发明关于以相变存储材料,包括硫属基材料,与其它可编程阻抗材料为基础的高密度可编程存储装置。
背景技术
基于相变化的存储材料,例如硫属基材料与类似材料,能因为适合在集成电路中实施的电位电流的施加而在一非晶态与一结晶态之间改变。普通非晶态特征在于比普通结晶态更高的电阻,其可以容易地感应以指出数据,这些特质已经引起使用可编程阻抗材料以形成非挥发性存储器电路的兴趣,其能以随机存取来读取与写入。
从非晶态到结晶态的改变通常地是一较低电流操作,从非晶态到结晶态的改变,在此被称为复位(reset),是通常地一较高电流操作,其包括一短高电流密度脉冲以融化或者破坏结晶结构,此后相变材料迅速冷却,抑制相变过程并使相变材料的至少一部分在非晶态中稳定。通过缩减存储单元和/或电极与相变材料之间的接触面积内的相变材料元件的尺寸可以缩减用于复位所需要的电流大小,这样以至于可以由穿过相变材料元件的少量绝对电流值来达成较高电流密度。
增加在存储单元阵列内的存储单元的密度是值得向往的,随着特征尺寸缩减,存储单元与对应的存取装置以及字线和位线的适当排列呈现出挑战。
此外,减少存储装置的制造的工艺成本也是值得向往的。
发明内容
针对现有技术中的上述需求,本发明提出一种交点自对准缩减存储单元尺寸的可编程存储装置及其制作方法,以增加在存储单元阵列内的存储单元的密度,减少其工艺成本。
通常,交点可编程存储器阵列是以该可编程存储单元是排列在存取装置与在位线与字线交点的方式公开,一层周边逻辑装置形成在半导体衬底本体的表面处,且可编程存储元件是形成在半导体衬底本体表面上,这样以至于由该周边逻辑栅所定义的平面与可编程存储元件相交,一种制作存储阵列的方法使用镶嵌工艺(damascene process)形成一或者两条位线与字线,且位线是(或者位线与字线两者是)与存取装置和可编程存储元件自对准。
位线是被定义在衬底上的多个形成在平行于位线方向沟道内的第一绝缘结构之间,多个第二绝缘结构是形成在平行于字线方向的沟道内,其比第一绝缘沟道浅,第一和第二绝缘结构在半导体表面上延伸,存储单元存取装置是形成在半导体衬底,且他们被局限在多个第一绝缘结构之间的方向与多个第二绝缘结构之间的垂直方向。
字线与可编程存储元件是形成在覆盖存储单元存取装置的字线沟道,且被局限在半导体衬底表面上的多个第一绝缘结构之间,结果,可编程存储元件与存取装置与位线都被“自对准”。
在某些实施例,硬式掩模用来定义第二(字线)绝缘沟道,且可以将这个硬式掩模留在原处直到可编程存储元件与字线形成。在这些实施例中,可以在第二绝缘沟道上形成一填充,且覆盖存储单元存取装置的硬式掩模的部分可以被选择性地移除以形成字线沟道,结果,在这些实施例中字线、可编程存储元件与存取装置都被“自对准”。
在其它实施例中没有硬式掩模会留在原处,且额外的掩模会用来定义覆盖存储单元存取装置的字线沟道。在这些实施例中,字线与可编程存储元件被“自对准”(它们经由镶嵌工艺而形成在字线沟道内),但字线与可编程存储元件并没有与存储单元存取装置自对准。
一种制作存储阵列的方法使用镶嵌工艺形成一或者两条位线与字线,且位线是(或者位线与字线两者是)与存取装置和可编程存储元件自对准。
一方面,本发明以包含具有包含周边区域与存储阵列区域的表面的半导体衬底本体的可编程存储装置为特征,该装置包含在该存储阵列区域的一可编程存储阵列以及在该周边区域的该衬底表面的一逻辑装置层,该存储阵列包括形成在该衬底本体的多个存取装置以及形成在该衬底表面的多个可编程存储元件,其中这些存取装置与这些存储元件是在多个字线与多个字线的多个交点处对准,以及这些位线是与这些可编程存储元件与这些存取装置自对准。在某些这样的装置,该字线是与可编程存储元件和存取装置自对准。
另一方面,本发明以包含具有包含周边区域与存储阵列区域的表面的半导体衬底本体的可编程存储装置为特征,该装置包含在该存储阵列区域的一可编程存储阵列以及在该周边区域的该衬底表面的一逻辑装置层,该存储阵列包括形成在该衬底本体的多个存取装置以及形成在该衬底表面的多个可编程存储元件,其中经由多个周边逻辑栅所定义的一平面相交该可编程存储元件。在某些这样的实施例,该存取装置与存储元件是在位线与字线的交点处对准,且该位线是与可编程存储元件和该存取装置自对准。在某些这样的装置,该字线是与可编程存储元件和存取装置自对准。
另一方面,本发明以制作可编程存储阵列的方法为特征,其包括:提供具有覆盖一存储阵列区域与一周边区域的一表面的一半导体衬底;沉积在该衬底表面上的一栅氧化层和一栅层;使用一共同掩模在该存储阵列区域与该周边区域两者上形成平行于一第一方向的多个第一沟道绝缘结构;移除该共同掩模并形成在该栅层与该第一沟道绝缘结构上的一氮化硅层;形成平行于垂直该第一方向的一第二方向的多个第二沟道;形成在该存储阵列区域上的一介电填充;在该周边区域使用一逻辑掩模图案化(patterning)该周边栅氧化层与栅层,以形成多个逻辑栅;在该周边区域执行一装置注入以形成源极与漏极区域;形成在该存储阵列区域与该周边区域上的一介电填充并平坦化该介电填充;移除该氮化硅层与该栅层与在该存储阵列上的该栅氧化层以形成多个字线沟道;形成在该存储阵列区域内的该第一与第二沟道绝缘结构上的多个间隙物以形成孔隙;以及在该字线沟道内形成至少一存储单元或者字线。
另一方面,本发明以制作可编程存储阵列的方法为特征,其经由:提供具有覆盖一存储阵列区域与一周边区域的一表面的一半导体衬底;沉积在该衬底表面上的一栅氧化层和一栅层;使用一共同掩模在该存储阵列区域与该周边区域两者上形成平行于一第一方向的多个第一沟道绝缘结构;移除该共同掩模并形成平行于垂直于该第一方向的一第二方向的多个第二沟道;形成在该存储阵列区域上的一介电填充;在该周边区域使用一逻辑掩模图案化该周边栅氧化层与栅层以形成多个逻辑栅;在该周边区域执行一装置注入以形成源极与漏极区域;形成在该存储阵列区域与该周边区域上的一介电填充并平坦化该介电填充;移除在该存储阵列上的该栅层与栅氧化层以形成多个字线沟道;形成在该存储阵列区域内的该第一与第二沟道绝缘结构上的多个间隙物以形成孔隙;以及形成在该字线沟道内的至少一存储单元或者字线。
在某些实施例,该方法还包括在下列一或者更多阶段形成存储存取装置注入:先在沉积于该衬底表面上的该栅氧化层前,在形成该第二沟道后,或者先于形成在该存储阵列区域内的这些间隙物前。在某些实施例,该方法还包括在下列一或者更多阶段形成覆盖该周边区域的该衬底的周边装置注入:先于沉积在该衬底表面上的该栅氧化层前,或者在形成该逻辑栅后。
在某些实施例,形成这些第二沟道包括:形成在该氮化硅层上的一掩模以及,使用该掩模,刻蚀以形成该第二沟道。
在某些实施例,形成这些存储单元包括:沉积在该字线沟道内的一可编程存储材料以及形成在该可编程存储材料上的一顶部电极。在某些实施例,形成这些存储单元包括:沉积在该字线沟道内的一底部电极材料,沉积在该底部电极材料上的一可编程存储材料,以及形成在该可编程存储材料上的一顶部电极。
在某些实施例,形成在该第二存储阵列硅化物上的这些存储单元包括:形成在该存储阵列区域与该周边区域上的一掩模,该掩模经图案化以形成覆盖该第二存储阵列硅化物的字线沟道;以及沉积在该字线沟道内的一可编程存储材料与一顶部电极。
在某些实施例,形成这些存储单元包括:沉积在该第二存储阵列硅化物上的一可编程存储材料并形成在该可编程存储材料上的一顶部电极。在某些实施例形成这些存储单元包括沉积在该第二存储阵列硅化物上的一底部电极,沉积在该底部电极材料上的一可编程存储材料,以及形成在该可编程存储材料上的一顶部电极。
在某些实施例,该方法还包含:在形成存储单元后,形成在该存储阵列区域与该周边区域上的一钝化层;以及形成穿过该钝化层至该存储阵列区域内的顶部电极与至该周边区域内的源极/漏极区域的多个接触。
在某些实施例,在该存储阵列内的多个存储单元具有等于4D2的一面积,D是关于字线宽度与字线之间的分隔距离的总和的二分之一,典型地关于使用于制造这些存储单元的一光刻工艺的名义特征尺寸。
该结构可以使用自对准工艺形成,其中多条字线与多个存储阵列与垂直晶体管对准而无需额外的图案化步骤,此外,在工艺过程中存储材料并不暴露于刻蚀化学成分,留下无害的存储元件。
所公开的方法提供具有缩减存储单元尺寸存储单元的存储阵列,以及该方法具有低处理成本,如缩减掩模的数目。
附图说明
图1为流程图其根据实施例概述制作相变存储器工艺的多个阶段;
图2A、图2B与图2C为示意描绘其根据实施例显示相变存储器,图2A是平面视图,图2B是如图2A在B-B所指出的侧剖视图,图2C是如图2A在C-C所指出的侧剖视图;
图3、图4、图5A、图5B、图6A、图6B、图6C、图7A、图7B、图7C、图7D、图7E、图8A、图8B、图8C、图8D、图8E、图9A、图9B、图10A、图10B、图11A、图11B、图11C、图11D、图12A、图12B、图12C、图12D、图13A、图13B、图13C、图13D、图14A、图14B、图14C、图14D、图15A、图15B、图16A、图16B与图17为示意描绘其根据实施例显示制作相变存储器工艺的多个阶段;
(根据前述所概述的方案可以认出多种视图:在每个实例标注A的附图(例如,图7A)为平面视图,标注为B的附图为在对应的平面视图在B-B所指出的侧剖视图,以及标注为C、D或E的附图为在对应的视图在C-C、D-D或者E-E所指出的侧剖视图,例如,图7B是如图7A在B-B所指出的侧剖视图,图7C是如图7A在C-C所指出的侧剖视图,第7D图是如图7A与图7B在D-D所指出的侧剖视图,图7E是如图A与图7C图在E-E所指出的侧剖视图);
图18为流程图其根据另一实施例概述制作相变存储器工艺的多个阶段;
图19A、图19B、图19C、图20A、图20B、图21A、图21B、图22A、图22B、图23A、图23B、图24A、图24B、图25A、图25B、图26A、图26B、图26C、图27A、图27B、图28A、与图28B为示意描绘其根据实施例显示制作相变存储器工艺的多个阶段;(根据前述所概述的方案可以识别多种视图)
图29与图30为剖视示意描绘其说明实施例的实施例;
图31为对于如在此所描述使用存储单元来实施的存储阵列示意图;以及
图32为如在此所描述包含具有存取装置与存储元件的存储单元阵列的集成电路的简化区块图。
【主要元件符号说明】
310:存储阵列 317:存储单元
318:二极管 312、312a、312b与312c:字线
314、314a、314b与314c:位线 316:可编程阻抗存储元件
3201:集成电路
3214:字线(列)译码器 3216:多条字线
3218:位线(栏)译码器 3220:多条位线
3222、3226:总线 3228:数据输入线
3224:感应放大器与数据输入结构
3230:其它电路 3232:数据输出线
3234:控制器 3236:偏压配置供应电压
20:存储器 202:衬底
2100:存储区域 2200:周边区域
2217、2117’、2117”与2117’”:沟道绝缘
2210:逻辑装置 2111:箭头
2213:栅介电层 2211:掺杂层
2212、2114:硅化物层 2214、2215:掺杂区域
206:介电质 2216:接触
2110:括号 2113:水平部分
2112:垂直部分 204:介电层
2115:顶部电极、位线
101:提供半导体衬底
103:注入装置
104:沉积氧化栅层并光刻栅层
105:在存储阵列内形成第一沟道绝缘并光刻
106:沉积SiN
107:形成第二存储阵列沟道绝缘
108:存储阵列装置注入
108’:形成存储阵列硅化物;并填充
109:形成逻辑栅
110:光刻注入;形成间隙物;形成光刻硅化物
111:填充并平坦化
112:从存储阵列移除栅氧化层与SiN
113:存储阵列注入与硅化物
114:在存储阵列上形成间隙物
115:沉积PCM与顶部电极;平坦化
116:形成BPSG与通透连接(contacts through the BPSG)402:栅氧化层 404:栅层
602:氮化硅层 504:栅材料
502:栅氧化材 820:硅化物
840:介电填充 920:条状SiN层
910与910’:逻辑栅 913:栅氧化物
911:栅结构 2010、2010’:栅叠层
1002:沟道绝缘结构 1010:硅化物
112:介电质 1302:硅化物
1401:间隙物 1402:接触面积
1502:相变材料 1504:电极材料
2616:接触 2615:掺杂区域
1615:顶部电极 1725:电极材料
1801:提供半导体衬底
1803:注入装置
1804:沉积氧化栅层并光刻栅层
1805:在存储阵列内形成第一沟道绝缘并光刻
1807:形成第二存储阵列沟道绝缘*
1808:存储阵列装置注入
1808’:形成存储阵列硅化物;并填充
1809:形成逻辑栅
1810:光刻注入;形成间隙物;形成光刻硅化物
1812:从存储阵列移除栅氧化层与SiN
1813:存储阵列注入;硅化物光刻与存储阵列
1814:掩模光刻
1815:阵列间隙物微缩与形成底部电极
1816:沉积字线介电质
1817:形成存储阵列字线沟道
1818:沉积PCM与顶部电极;平坦化
1819:形成BPSG与通透接触
1920:硅化物 1940:介电填充
2013:栅氧化物 2011:栅结构
2012:绝缘结构 2310:硅化物
2320:硅化物 2402:掩模
2706:电极材料 2602:介电层
2702:相变材料 2704:电极材料
2802:电极涂覆 2816:接触
2815:掺杂区域 2802:介电质
2910:插塞 2902:条状相变材料
2904:电极 2916:接触
2922:介电质 3010:相变材料
3004:电极 3016:接触
3022:介电质
具体实施方式
本发明现将通过参照附图,其说明替代具体实施例与方法,而被更详细地描述,附图是概略的,展示实施例的特征和它们与其它特征与结构的关系,且不是按比例制作。为了增进展示的明晰度,在图中,说明各种实施例,对应于其它附图的元件没有全部特别地重新编号,虽然在图中它们全部都可以无困难地识别,也为了没有展示在附图中的某些特征,其对本发明的了解并非必须,的展示的清晰度。没有意图将该发明限制在具体公开的实施例与方法以及使用其它特征,元件,方法与实施例可能可以实行该发明是可以了解的。描述特定的实施例是用以说明本发明,并非用以限制其范围,该范围通过权利要求定义。本领域的普通技术人员将可以认知对下列描述的各种等同变化。
图31是存储阵列310的示意图,使用在此所描述的存储单元可以实施存储阵列310。在这个实施例,每个存储单元317包括二极管存取装置318与沿着对应字线312与对应位线314间的一电流路径串联排列的可编程阻抗存储元件316(表现为可变电阻),如以下更详细地描述,在给定的存储单元存储器储元件针对包括第一与第二阻抗状态的多个阻抗状态是可编程的。
阵列包括:包含在第一方向平行延伸的字线312a、312b与312c的多条字线312,以及包含在垂直于第一方向的第二方向平行延伸的位线314a、314b与314c的多条位线314。阵列310被称为交点阵列是因为字线312与位线314互相横跨(cross),但并未实体地相交(intersect),且存储单元317是位于字线312与位线314的这些交点位置。
存储单元317是代表阵列310的存储单元并排列在字线312b与位线314b的交点位置,存储单元317包含(在这个实施例中)二极管318与串联排列的存储元件316,二极管318是电耦接于字线312b且存储元件316是电耦接于位线314b。
阵列310的存储器存储单元317的读取(reading)或写入(writing)可以通过施加适当电压脉冲至对应的字线312b及位线314b以感应穿过所选择的存储单元317的电流来达到,取决于所执行的操作,例如:读取操作或编程操作,施加电压的电位和延时。
在存储于存储单元317中的数据值的读取(或感应)操作,偏压电路(参见图32的偏压配置供应电压、电流源3236)耦接至对应的字线312b及位线314b以横跨存储单元317施加适合振幅与延时的偏压配置以感应电流流动,其不会导致存储元件316经历在阻性状态(resistive state)中的改变。穿过存储器存储单元317的电流取决于存储元件316的阻抗,以及取决于存储在存储单元317中的数据值。数据值的决定,举例来说,可以通过比较位线314b上的电流与感应放大器(sense amplifier)的适合参考电流(参见,例如:图32中的感应放大器/数据输入结构3224)。
在存储于该存储器存储单元317中的数据值的编程操作中,偏压电路(参见图32的偏压配置供应电压、电流源3236)耦接至对应的字线312b及位线314b以横跨存储单元317施加适当振幅与延时的偏压配置以感应存储元件316的可编程改变,以将数据值存储于存储单元317内,存储元件316的电阻对应于存储在存储单元317中的数据值。
该偏压配置包含足够顺偏(forward bias)二极管318并将存储器元件317的阻抗状态从对应于第一编程状态的电阻改变至对应于第二编程状态的电阻的第一偏压配置,该偏压配置也包含足够顺偏(forward bias)二极管318并将存储器元件317的阻抗状态从对应于第二编程状态的电阻改变至对应于第一编程状态的电阻的第二偏压配置,在各实施例中,用于存储器元件317的单极操作(unipolar operation)的每个偏压配置可以包括一或多个电压脉冲,以及可以对每个实施例经验地决定电压电位与脉冲时间。
图32是包含存储单元的交点存储阵列310的集成电路3201的简化区块图,在这个实施例中,每个存储单元包含二极管存取装置与可编程阻抗存储元件,字线(列)译码器3214被耦接到并与多条字线3216电通信,一位线(栏)译码器3218与多条位线3220电通信以对阵列310中的存储单元(未示于图中)读取并写入数据。地址在总线3222上提供至字线译码器与装置3214以及位线译码器3218。区块3224中的感应放大器与数据输入结构透过数据总线3226耦接至位线译码器3218,数据透过数据输入线(data-in line)3228从集成电路3201上的输入/输出端口,或从集成电路3201的内部或外部的其它数据源,提供至区块3224中的数据输入结构。在集成电路3201中可包含其它电路3230,例如:通用处理器或特殊目的应用电路,或者提供受阵列310支持的单芯片系统功能性(system-on-a-chipfunctionality)的多个模块的组合。数据透过数据输出线3232从区块3224中的感应放大器供应至集成电路3201上的输入/输出端口或至集成电路3201的内部或外部的其它数据目的地。
在这个实施例中实施的控制器3234,使用偏压配置状态机,控制偏压配置供应电压3236的应用,例如:读取、编程及编程验证电压。控制器3234可以使用本领域所知的特殊目的逻辑电路来实施,在另一实施例中,控制器3234包括通用处理器,其可以在相同集成电路上实施以执行用以控制装置的操作的计算机程序,又在其它实施例中,特殊目的逻辑电路与通用处理器的组合可以被利用于控制器3234的实施。
存储材料元件的可编程阻抗材料的实施例包含相变存储材料,包含硫属基材料(chalcogenide based materials)与其它材料,硫属包含,形成周期表VIA族的一部分的,四元素氧(O)、硫(S)、硅(S)与锑(Se)当中的任一,硫属包括具有更多阳性元素或者基的硫化合物,硫属合金包括具有其它材料例如过渡材料的硫属组合,硫属合金通常含有一或者更多的来自元素周期表VIA族的元素,例如:锗(Ge)与锡(Sn),往往,硫属合金包含一或者更多的锑(Sb)、镓(Ga)、铟(In)与银(Ag)。许多相变存储材料已经在技术文献中描述,包含Ga/Sb、In/Sb、In/Se、Sb/Te、Ge/Te、Ge/Sb/Te、In/Sb/Te、Ga/Se/Te、Sn/Sb/Te、In/Sb/Ge、Ag/In/Sb/Te、Ge/Sn/Sb/Te、Ge/Sb/Se/Te与Te/Ge/Sb/S的合金,在Ge/Sb/Te合金的家族,大范围的合金合成物是可行的,此合成物的特征在于TeaGebSb100-(a+b)。某研究者已经描述最有用的合金如具有在沉积材料中Te的平均浓度将低于70%,典型地低于约60%以及通常在介于从低到如约23%升到约58%之间的Te且最佳地约48%到58%的Te,Ge的浓度大于约5%以及平均在材料中介于从低约8%到约30%之间,剩余者通常低于50%。最佳地,Ge的浓度介于从约8%到约40%之间,在此合成物中的剩余主要组成元素为Sb,这些百分比是组成元素的原子总计100%的原子百分比(Ovshinsky美国专利号码5,687,112第10-11栏),由另一研究者所评估的特殊合金包含Ge2Sb2Te5、GeSb2Te4与GeSb4Te7(Noboru Yamada,“Ge-Sb-Te相变光盘用于高数据率纪录的潜力”,SPIE v.3109,第28-37页(1997))。更通常地,过渡金属例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、铅(Pd)、铂(Pt)与混合物或者其合金可以与Ge/Sb/Te组合以形成具有可编程阻抗特质的相变合金,在Ovshinsky‘112第10-13栏中提供了有用的存储材料的具体实施例,在此并入本发明以供参考。
其它材料,可以被称为“杂质”,在某些实施例中可以添加到硫属与其它相变材料以使用添加来修改硫属来修改导电性,过渡温度,融化温度,与存储元件的其它特质,作为硫属添加物的代表性杂质包含氮、硅、氧、氧化硅、氮化硅、铜、银、金、铝、氧化铝、钽、氧化钽、氮化钽、钛与氧化钛,参见,例如:美国专利号码6,800,504与美国专利申请公开号U.S.2005/0029502。
相变合金能够在第一结构状态与第二结构状态之间切换,在第一结构状态中材料是在普通非晶固态,在第二结构状态中材料是在存储单元活化信道区域中的局部有秩序的普通结晶固态,这些合金至少是双稳态的,术语非晶是惯指一相对较少的秩序结构,比单晶更无秩序,其具有可检测的特性例如比结晶相高的电阻,术语结晶是惯指一相对比较有秩序的结构,比非晶结构更有秩序,其具有可检测的特性例如比非晶相低的电阻,典型地,相变材料可以在跨越完全非晶与完全结晶态间频谱的局部秩序的不同可检测状态之间电性切换,其它受包含原子秩序、自由电子密度与活化能的非晶与结晶相间改变影响的材料特性,材料可以被切换进入不同固相或者进入二或者更多的固相混合物,其在完全非晶与完全结晶态之间提供过渡,材料的电特质可以据此改变。
相变合金可以通过电脉冲的施加而从某相态改变到另一相态,据观察一较短、较高振幅脉冲倾向于改变相变材料至普通非晶态,一较长、较低振幅脉冲倾向于改变相变材料至普通结晶态,一较短、较高振幅脉冲的能量其高到足够使结晶结构的键结被打断且短到足够预防原子重新排列为结晶态,脉冲的适当曲线,无须大量实验即可以被决定,具体地适应于一个特殊相变合金,在以下公开的小节,相变材料是指GST,且其将被理解为也可以使用其它类型的相变材料,在此描述适用于PCRAM的实施的材料为Ge2Sb2Te5。
其它可编程阻抗存储材料可以使用在本发明的其它实施例,包含使用不同晶相改变以决定阻抗的其它材料,或者使用电脉冲以改变阻抗状态的其它存储材料,实施例包含使用在随机存取存储器(RRAM)的材料例如包含氧化钨(WOX)、NiO、Nb2O5、CuO2、Ta2O5、Al2O3、CoO、Fe2O3、HfO2、TiO2、SrTiO3、SrZrO3、(BaSr)TiO3的金属氧化物,其他实施例包含使用在磁电阻式随机存取存储器(MRAM)的材料例如自旋矩转移(STT)MRAM,例如CoFeB、Fe、Co、Ni、Gd、Dy、CoFe、NiFe、MnAs、MnBi、MnSb、CrO2、MnOFe2O3、FeOFe2O5、NiOFe2O3、MgOFe2、EuO与Y3Fe5O12的至少其一,参见,例如:美国专利申请公开号2007/0176251,名称“Magnetic Memory Device and Method of Fabricating the Same”,在此并入本发明以供参考,额外实施例包含用于可编程金属化存储单元(PMC)存储器,或者纳米离子存储器的固态电解质材料,例如银掺杂锗硫化物电解质与铜掺杂锗硫化物电解质,参见,例如:N.E.Gilbert et al.,“A macromodel of programmable metallization cell devices”,固态电子49(2005)1813-1819,在此并入本发明以供参考。
图2A、图2B与图2C显示以平面视图(图2A)与剖视图(图2B与图2C)包含一个存储单元阵列与一个周边逻辑电路的存储器20的一部分。
存储器20包含在单结晶半导体衬底202上的存储区域2100与周边区域2200,衬底202具有实质平面的顶部表面,如在此使用的,术语“实质平面”是有意容纳衬底202形成过程中的制造公差(tolerances),术语“实质平面”也有意容纳衬底202形成后所执行的工艺其可能导致在顶部表面的平面的变异。
周边区域2200包含逻辑装置,其经由沟道绝缘所绝缘,例如沟道绝缘2217,每个逻辑装置,例如逻辑装置2210,例如,具有在栅介电层2213上的栅结构,栅介电层2213是在衬底202的顶部表面,栅结构包含在栅介电层2213上的多晶硅掺杂层2211,与在多晶硅掺杂上的硅化物层2212。
逻辑装置2210包含在衬底202内作为源极和漏极区域的掺杂区域2214与2215,包括覆盖逻辑装置2210的一或者更多介电材料的介电质206(图2A中的结构表现出如同介电质206是透明的,这样以便于可看见在其下方的特征)。
接触2216是耦接到掺杂区域2215并延伸到可以接近所覆盖的电路的介电质206的顶部表面。
存储区域2100包含,形成在单晶硅衬底202上且经由沟道绝缘,例如沟道绝缘2117、2117’、2117”以及2117’”,所绝缘的,存取装置阵列(未显示于这些图中,箭头2111是建议这样装置的位置),硅化物层2114覆盖在覆盖存取装置的衬底202表面的存取装置,相变存储单元是构造在衬底202表面的硅化物层,即,相变存储单元是在同一层(经由括号2110所建议)如同周边逻辑的栅结构,各种相变存储单元结构(configurations)被仔细考虑(以及如后所描述的某些实施例),在这些附图显示的实施例中,存储材料是“孔隙结构”,包含水平部分2113与垂直部分2112,垂直部分是形成在围绕介电层204中的孔隙中,在此显示的实施例中,相变存储材料的水平部分2113是由顶部电极2115所覆盖,接触2116耦接到顶部电极2115并延伸到可以接近所覆盖的电路的介电质206的顶部表面。
位线2115经设计以具有特定位线宽度且以经由一特定第一分隔距离而分离,字线经设计以具有特定字线宽度且以经由一特定第二分隔距离而分离,在某些实施例中特定位线宽度与特定第一分离距离的总和约等于两倍的特征尺寸D,其中D是用于建立字线与位线的光刻工艺的名义特征尺寸,以及特定字线宽度与特定第二分离距离的总和约等于两倍的特征尺寸D,这些尺寸的限制下存储单元具有约等于4D2的面积2500。
图1为流程图其概述制作相变存储器工艺的多个阶段,以及图3-图17,以各种视图,根据本发明的实施例说明相变存储器建造的多个阶段。
参照图1,在阶段101提供半导体衬底202;典型地衬底是一个单晶硅衬底,但可以仔细考虑其它半导体。在阶段103在存储阵列区域2100与半导体衬底(在图3的30处)的周边区域2200实行装置注入,第一装置注入可以在这个阶段执行:以形成用于存储阵列区域存储器取装置的P或者N阱,与用于周边区域内周边逻辑装置的P或者N阱,一或者更多额外注入可以在这个阶段执行包含:用以形成在存储阵列区域内位线的注入(经由,例如,在阱为P的地方的N+注入),以及用以形成二极管存取装置或者晶体管存取装置元件的注入(经由,例如,在N+注入上的P注入,以形成N-P二极管;或者在N+注入上的P注入,跟随在额外浅N+注入后),或者,一或者更多装置注入可以在一或者更多继续的阶段执行,在存储阵列区域2100的存取装置并未显示在这些附图,适当的存取装置包含,例如,垂直建造装置,如垂直二极管,垂直场效应晶体管(FET),垂直双极结晶体管(BJT),垂直金属氧化物半导体(MOS)。
继续地,在阶段104栅氧化层402形成在存储阵列区域2100与周边区域2200两者内的衬底表面上,以及在继续阶段栅层404形成在栅氧化层402上,结果显示在图4的40处,在较后的阶段(概述如下),将图案化栅氧化层与栅层以形成在周边逻辑的栅结构,适合用于栅层的材料包含多晶硅,例如,以及可以经由低压化学气相沉积形成栅层,例如。
在继续阶段105第一沟道绝缘(平行于位线方向)形成在存储阵列区域(沟道绝缘2117)与周边区域(沟道绝缘2217)内,适合用于形成沟道的技术导致实质平面,近似垂直的边墙,且可以在二或者更多的步骤中执行,适合用于形成沟道的技术包含,例如,方向性刻蚀如,例如,RIE,经由工艺参数的选择可以控制RIE,使用较低压力与较高衬底偏差可以对沟道形状与大小提供优选的控制,在使用RIE之处,在其后可以接着清洁工艺,可以使用双重曝光(double patterning)或者多重曝光(manifoldpatterning)光刻技术,这样技术的实施例概述于Ping Xie et al.(2009)“Analysis of higher-order pitch division for sub-32m,lithography”,SPIE会议,Vol.7274,第72741Y-1到72741Y-8页,可以使用共同(共享)掩模图案化在周边区域与存储阵列区域两者内的绝缘沟道。
适合用于填充沟道的材料为介电质,以及适合的介电材料包含,例如,优选可以是氧化物(举例,氧化硅,如SiO2)以及氮化物(举例,氮化硅,如SiN),低K介电材料(如掺杂SiO2,例如),以及优选可以是具有低热导系数的材料,介电质可以经由,例如,物理气相沉积(PVD)工艺,或者化学气相沉积(CVD)工艺形成,在沟道填充后可以实行平坦化步骤(经由,例如,化学机械研磨,CMP),结果显示于图5A与图5B的50处。
在继续阶段106在沟道绝缘的结构上形成氮化硅层602,适合用于形成氮化硅层的技术包含低压化学气相沉积,例如。在继续的步骤图案化氮化硅,以及经图案化的氮化硅作为用于沟道形成的硬式掩模,除了氮化硅材料,适合作为硬式掩模的材料,可以用来形成这层,结果显示于图6A、图6B与图6C的60处。
在继续阶段107,第二沟道(平行于字线方向)在存储阵列区域内形成,使用掩模与刻蚀程序以形成穿过SiN与穿过所选择的底层的图案化沟道,在这个步骤中用于图案化硬式掩模层(氮化硅)的掩模并未显示在附图中,这构成了用于阵列的一个(第一)关键掩模步骤,即,这个掩模的大小建立了阵列密度与位置,适合用于形成第二沟道的技术包含选择性地移除未受掩模遮蔽的SiN602,未受掩模遮蔽的栅材料504,未受掩模遮蔽的栅氧化材料502,以及未受掩模遮蔽的半导体衬底202材料,但不要移除第一沟道绝缘内的介电填充,在多于一个步骤中实行刻蚀,使用适合各种将被刻蚀材料的刻蚀技术以和/或者刻蚀参数,适合用于形成沟道的技术包含,例如,方向性刻蚀如,例如RIE,经由工艺参数的选择可以控制RIE,使用较低压力与较高衬底偏差可以对沟道形状与大小提供优选的控制,可使用双重曝光或者多重曝光光刻技术,这样技术的实施例概述于Ping Xieet al.,如前所引述,可以定时刻蚀的最后阶段,以建立在沟道底部处的刻蚀停止,结果显示于图7A、图7B与图7C的70处。
在继续阶段108可以实行存储阵列装置注入,存储阵列注入必须在氮化硅掩模形成前实行。
在继续阶段108’选择性地在存储阵列上形成硅化物820,以及形成介电填充840,适合用于填充沟道的材料为介电质,以及适合的介电材料包含,例如,优选可以是氧化物(举例,氧化硅,如SiO2)以及氮化物(举例,氮化硅,如SiN),低K介电材料(如掺杂SiO2,例如),以及优选可以是具有低热导系数的材料,介电质可以经由,例如,物理气相沉积(PVD)工艺,或者化学气相沉积(CVD)工艺形成,可以在沟道填充后实行平坦化步骤(经由,例如,化学机械研磨,CMP),结果显示于图8A、图8B与图8C的80处。
移除覆盖在周边区域的SiN层602的部分,留下覆盖存取装置的条状SiN层920在原处。在继续的阶段109图案化(经掩模与刻蚀)周边区域内的逻辑栅(举例,910与910’),每个经图案化的逻辑栅(举例,栅910)包含叠层在栅氧化物913上的栅结构911,结果显示于图9A与图9B的90处,适合用作为逻辑栅掩模的材料与适合的刻蚀技术,其移除未受掩模遮蔽的栅材料但是并不移除绝缘结构,为已知,剩余在存储阵列上的条状SiN层920保护覆盖存储单元装置的栅以与门氧化物。
在继续的阶段110实行周边装置注入以形成源极与漏极区域,且此后在周边区域中邻近栅叠层(2010)处与在介电沟道绝缘结构(1002)的暴露表面处形成介电间隙物,此后在邻近间隙物的衬底的暴露面积与栅的暴露表面上形成硅化物1010,结果显示于图10A与图10B的110处。
在继续的阶段111以介电质112填充周边区域并平坦化所导致的结构,例如经由CMP,适合用作介电质的材料包含,例如,优选可以是氧化物(举例,氧化硅,如SiO2)以及氮化物(举例,氮化硅,如SiN),低K介电材料(如掺杂SiO2,例如),以及优选可以是具有低热导系数的材料,可以经由,例如,物理气相沉积(PVD)工艺,或者化学气相沉积(CVD)工艺形成介电支撑层,结果显示于图11A与图11B图的110处。
在继续的阶段112经由,例如选择性刻蚀,从存储阵列区域移除栅氧化层与氧化硅层,结果显示于图12A与图12B图。在继续的阶段113可以在硅化物之后,举例,硅化物1302,实行选择性地额外存储阵列注入,结果显示于图13A与图13B的130处。
在继续的阶段114在存储阵列区域内的氧化物边墙上形成氧化间隙物,其结果例如显示于图14A、图14B、图14C与图14D的140处。氧化间隙物(举例,间隙物1401)遮蔽存储阵列区域内覆盖存取装置的多数硅化物,这样以至于只留下小接触面积1402被暴露,这个小接触面积是,作为工艺的结果,与所覆盖存取装置对准(“自对准”),并也将与字线和位线的相交对准,如下所描述。
在继续的阶段115在存储阵列区域上沉积相变材料1502,填充在所暴露硅化物的小接触面积上的开口。
在所显示的实施例,是使用硫属材料,经由气相沉积,如物理气相沉积(PVD)或者化学气相沉积(CVD),例如,可以形成硫属材料薄膜。
一种形成硫属材料薄膜的方法的实施例在范围1mTorr~100mTorr的压力使用并同Ar、N2以和/或者He等的气体源的PVD溅射或者磁控溅射方法,沉积通常是在室温下进行,具有1~5深宽比的准直仪可以用来改进填充表现,为了改进表面的一致性,也可以使用数种几十伏特至数种几千伏特的DC偏压,另一方面,DC偏压与准直仪的组合可以同时地使用。
一种形成硫属材料薄膜的方法的另一实施例使用CVD如公开在美国专利申请公开号2006/0172067,名称“Chemical Vapor Deposition ofChalcogenide Material”,在此并入本发明以供参考。
此后沉积顶部电极材料1504与相变材料接触,且平坦化该结构,例如经由CMP,结果显示于图15A与图15B的150处。适合顶部电极的材料包含导电材料如金属或者金属基材料或者非金属材料,如,举例:铜、铝;钛(Ti)与钛基材料如氮化钛(TiN)、氮氧化钛(TON);钽(Ta)与钽基材料如氮化钽(TaN);多晶硅,钨基材料如硅化钨(WSiX);以及,对于低热导系数电极,如镍酸镧(LNO,LaNiO3)与锰酸锶镧(LSMO,LaSrMnO3)材料等,经由各种适合这些特殊材料的技术当中的任一可以形成顶部电极层,这些技术包含,经过这样的实施例,溅射与电镀与CVD。顶部电极可以具有厚度,例如,在约至约的范围,通常约
在真空或者在N2环境中选择性地执行沉积后退火处理以改进硫属材料的结晶态,退火温度典型地介于从100℃至400℃之间并具有少于30分钟的退火时间。
在继续的阶段116电极涂覆,例如在该结构上形成硅磷酸玻璃(BPSG),并平坦化BPSG,然后形成接触以将在存储阵列内与周边内的结构耦接到结构的顶部表面,接触2616是耦接到掺杂区域2615并延伸到介电质206的顶部表面,在此其可以存取覆盖电路,接触1616是耦接到顶部电极1615并延伸到介电质206的顶部表面,在此其可以存取覆盖电路。
如上所述,其它相变存储阵列构造被仔细考虑,例如,较低的电极材料可以沉积在经由在控制层上的介电间隙物所形成的狭窄的开口内,以及相变材料可以沉积在较低电极材料上,这些结构说明在图17,例如,较低电极材料1725接触硅化物1302的狭窄表面。
图18为流程图其根据本发明的另一实施例说明制作相变存储器工艺的多个阶段,以及图19A-图28B,以各种视图,根据本发明的另一实施例说明相变存储器建造的多个阶段。在此说明的实施例,相变存储元件只自对准于位线。
参照图18,其阶段相似于关于图1所概述的工艺的初期阶段,并参照初期的附图,在以下的讨论,在这个实施例,如同图1所说明的实施例,可以使用共同掩模在存储阵列区域与周边区域两者上形成第一沟道绝缘(平行于位线方向),但是不像图1所说明的实施例,在这个实施例没有使用氮化硅硬式掩模,且使用两个不同掩模以在存储阵列区域内形成第二沟道绝缘与平行于字线方向的结构,据此,在这个实施例,位线是与至少存取装置与底部电极自对准,但字线并未自对准。
尤其是,在阶段1801提供半导体衬底202;典型地衬底是一个单晶硅衬底,但可以仔细考虑其它半导体。在阶段1803在存储阵列区域2100与半导体衬底(在图3的30处)的周边区域2200实行装置注入,第一装置注入可以在这个阶段执行:以形成用于存储阵列区域存储器取装置的P或者N阱,与用于周边区域内周边逻辑装置的P或者N阱,一或者更多额外注入可以在这个阶段执行包含:用以形成在存储阵列区域内位线的注入(经由,例如,在阱为P的地方的N+注入),以及用以形成二极管存取装置或者晶体管存取装置元件的注入(经由,例如,在N+注入上的P注入,以形成N-P二极管;或者在N+注入上的P注入,跟随在额外浅N+注入后),或者,一或者更多装置注入可以在一或者更多继续的阶段执行,在存储阵列区域2100的存取装置并未显示在这些附图,适合的存取装置包含,例如,垂直建造装置,如垂直二极管,垂直场效应晶体管(FET),垂直双极结晶体管(BJT),垂直金属氧化物半导体(MOS)。
继续地,在阶段1804栅氧化层402形成在存储阵列区域2100与周边区域2200两者内的衬底表面上,以及在继续阶段栅层404形成在栅氧化层402上,结果显示在图4的40处,在较后的阶段(概述如下),将图案化栅氧化层与栅层以形成在周边逻辑的栅结构,适合用于栅层的材料包含多晶硅,例如,以及可以经由低压化学气相沉积形成栅层,例如。
在继续阶段1805第一沟道绝缘(平行于位线方向)形成在存储阵列区域(沟道绝缘2117)与周边区域(沟道绝缘2217)内,适合用于形成沟道的技术导致实质平面,近似垂直的边墙,且可以在二或者更多的步骤中执行,适合用于形成沟道的技术包含,例如,方向性刻蚀如,例如,RIE,经由工艺参数的选择可以控制RIE,使用较低压力与较高衬底偏差可以对沟道形状与大小提供优选的控制,在使用RIE之处,在其后可以接着清洁工艺,可使用双重曝光或者多重曝光光刻技术,这些技术的实施例概述于Ping Xie et al.(2009),如前所引述,可以使用共同(共享)掩模图案化在周边区域与存储阵列区域两者内的绝缘沟道。
适合用于填充沟道的材料为介电质,以及适合的介电材料包含,例如,优选可以是氧化物(举例,氧化硅,如SiO2)以及氮化物(举例,氮化硅,如SiN),低K介电材料(如掺杂SiO2,例如),以及优选可以是具有低热导系数的材料,介电质可以经由,例如,物理气相沉积(PVD)工艺,或者化学气相沉积(CVD)工艺形成,在沟道填充后可以实行平坦化步骤(经由,例如,化学机械研磨,CMP),结果显示于图5A与图5B的50处。
在继续阶段1807,第二沟道(平行于字线方向)在存储阵列区域内形成,使用掩模与刻蚀程序以形成穿过SiN与穿过所选择的底层的图案化沟道,优选的第一关键掩模材料包含光阻,在这个步骤中用于图案化硬式掩模层(氮化硅)的掩模并未显示在附图中,这构成了用于阵列的一个(第一)关键掩模步骤,即,这个掩模的大小建立了阵列密度与位置,适合用于形成第二沟道的技术包含选择性地移除未受掩模遮蔽的SiN602,未受掩模遮蔽的栅材料504,未受掩模遮蔽的栅氧化材料502,以及未受掩模遮蔽的半导体衬底202材料,但不要移除第一沟道绝缘内的介电填充,在多于一个步骤中实行刻蚀,使用适合各种将被刻蚀材料的刻蚀技术以和/或者刻蚀参数,适合用于形成沟道的技术包含,例如,方向性刻蚀如,例如RIE,经由工艺参数的选择可以控制RIE,使用较低压力与较高衬底偏差可以对沟道形状与大小提供优选的控制,可以使用双重曝光或者多重曝光光刻技术,这些技术的实施例概述于Ping Xie et al.(2009),如前所引述,可以定时刻蚀的最后阶段,以建立在沟道底部处的刻蚀停止。
此后可以实行存储阵列装置注入1808。选择性地此后在程序1808’在存储阵列上形成硅化物1920,以及形成介电填充1940,适合用于填充沟道的材料为介电质,以及适合的介电材料包含,例如,优选可以是氧化物(举例,氧化硅,如SiO2)以及氮化物(举例,氮化硅,如SiN),低K介电材料(如掺杂SiO2,例如),以及优选可以是具有低热导系数的材料,介电质可以经由,例如,物理气相沉积(PVD)工艺,或者化学气相沉积(CVD)工艺形成,可以在沟道填充后实行平坦化步骤(经由,例如,化学机械研磨,CMP),结果显示于图19A、图19B与图19C的190处。
在继续的阶段1809图案化(经掩模与刻蚀)周边区域内的逻辑栅(举例,2010与2010’),每个经图案化的逻辑栅(举例,栅2010)包含叠层在栅氧化物2013上的栅结构2011,结果显示于图20A与图20B的200处,适合用作为逻辑栅掩模的材料包含光阻,适合的刻蚀技术其移除未受掩模遮蔽的栅材料但是并不移除绝缘结构。
在继续的阶段1810实行周边装置注入以形成源极与漏极区域,且此后在周边区域中邻近栅叠层(2010)处与在介电沟道绝缘结构(2012)的暴露表面处形成介电间隙物,结果显示于图21A与图21B的210处。
在继续的阶段1812从存储阵列区域移除栅氧化层与氮化硅层,结果显示于图22A与图22B。
在继续的阶段1813可以在硅化物2310与2320形成之后实行选择性地额外阵列装置注入,结果显示于图23A与图23B的230处。
在继续的阶段1814周边区域由掩模2402所保护,其结果例如显示于图24A与图24B的240处。
在继续的阶段1815在存储阵列区域内形成多个间隙物,以缩减覆盖存取装置的硅化物2310的暴露面积的尺寸,这样以至于只留下小接触面积被暴露,其结果显示于图25A与图25B。间隙物可以经由,例如,沉积一层介电材料在表面上且然后使用非等向性刻蚀以形成孔隙以暴露小面积的用来接触的下层硅化物,这个小接触面积是,作为工艺的结果,与所覆盖存取装置对准(“自对准”),并也将与字线和位线的相交对准,如下所描述。
在经由以底部电极材料2706如,例如,TiN填充孔隙或者开口并平坦化之后,其结果显示于图25A与图25B的250处。
在继续的阶段1816字线介电层2602形成在由阶段1815所导致的经平坦化表面上,且在阶段1817在第二关键掩模步骤中字线沟道穿过字线介电层而形成,其结果显示于图26A与图25B的260处。
此后相变材料2702沉积进入字线沟道,接触底部电极,以及顶部电极材料2704沉积在其上并接触相变材料2702,平坦化结果结构,其结果显示于图27A与图27B的270处。
在继续的阶段1819电极涂覆2802,例如在该结构上形成硅磷酸玻璃(BPSG),并平坦化BPSG,然后形成接触以将在存储阵列内与周边内的结构耦接到结构的顶部表面,接触2816是耦接到掺杂区域2815并延伸到介电质2802的顶部表面,在此其可以存取覆盖电路,接触2616是耦接到顶部电极2704并延伸到介电质206的顶部表面,在此其可以存取覆盖电路。
如上所述,其它相变存储阵列构造被仔细考虑,例如,图29显示具有孔隙结构的构造,其中在孔隙中的相变材料2910插塞接触其下的硅化物并接触覆盖条状相变材料2902,其受到电极2904的覆盖所转变,接触2916耦接到顶部电极2904并延伸到介电质2922的顶部表面,在此其可以存取覆盖电路,以及,例如,图30显示具有孔隙结构的构造,其中在孔隙中的相变材料3010插塞接触其下的硅化物并接触覆盖电极3004,接触3016耦接到顶部电极3004并延伸到介电质3022的顶部表面,在此其可以存取覆盖电路。
其它实施例在权利要求之中。
以上所述的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步详细说明,所应理解的是,以上所述仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (4)
1.一种可编程存储装置,其特征在于,包括:
具有包括一周边区域与一存储阵列区域的一表面的一半导体衬底本体;
在该存储阵列区域的一可编程存储阵列以及在该周边区域的该衬底表面的一逻辑装置层;
该存储阵列包括:形成在该衬底本体的多个存取装置以及形成在该衬底表面的多个可编程存储元件,其中这些存取装置与这些存储元件是在多个位线与多个字线的多个交点处对准,以及这些位线是与这些可编程存储元件与这些存取装置自对准;
其中,位线是被定义在衬底上的多个形成在平行于位线方向沟道内的第一绝缘结构之间,多个第二绝缘结构是形成在平行于字线方向的沟道内,其比第一绝缘沟道浅,第一和第二绝缘结构在半导体表面上延伸,存取装置是形成在半导体衬底,且他们被局限在多个第一绝缘结构之间的方向与多个第二绝缘结构之间的垂直方向;字线与可编程存储元件是形成在覆盖存取装置的字线沟道,且被局限在半导体衬底表面上的多个第一绝缘结构之间,可编程存储元件与存取装置与位线都被“自对准”;形成在该存储阵列区域内的该第一与第二绝缘结构上的多个间隙物以形成孔隙;以及在该字线沟道内形成至少一存储单元或者字线。
2.根据权利要求1所述的可编程存储装置,其特征在于,这些字线是与这些可编程存储元件与这些存取装置自对准。
3.根据权利要求1所述的可编程存储装置,其特征在于,在该存储阵列内的多个存储单元具有等于4D2的一面积,D是关于字线宽度与字线之间的分隔距离的总和的二分之一。
4.根据权利要求1所述的可编程存储装置,其特征在于,在该存储阵列内的多个存储单元具有等于4D2的一面积,D是关于使用于制造这些存储单元的一光刻工艺的名义特征尺寸。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/899,232 US8395935B2 (en) | 2010-10-06 | 2010-10-06 | Cross-point self-aligned reduced cell size phase change memory |
US12/899,232 | 2010-10-06 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102446547A CN102446547A (zh) | 2012-05-09 |
CN102446547B true CN102446547B (zh) | 2014-06-25 |
Family
ID=45925028
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201110043837.0A Active CN102446547B (zh) | 2010-10-06 | 2011-02-22 | 交点自对准的可编程存储装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US8395935B2 (zh) |
CN (1) | CN102446547B (zh) |
TW (1) | TWI426632B (zh) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9454997B2 (en) | 2010-12-02 | 2016-09-27 | Micron Technology, Inc. | Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells |
US9673102B2 (en) * | 2011-04-01 | 2017-06-06 | Micron Technology, Inc. | Methods of forming vertical field-effect transistor with self-aligned contacts for memory devices with planar periphery/array and intermediate structures formed thereby |
US8603891B2 (en) * | 2012-01-20 | 2013-12-10 | Micron Technology, Inc. | Methods for forming vertical memory devices and apparatuses |
US8946018B2 (en) * | 2012-08-21 | 2015-02-03 | Micron Technology, Inc. | Methods of forming memory arrays and semiconductor constructions |
US8921195B2 (en) | 2012-10-26 | 2014-12-30 | International Business Machines Corporation | Isolation scheme for bipolar transistors in BiCMOS technology |
US9627611B2 (en) | 2012-11-21 | 2017-04-18 | Micron Technology, Inc. | Methods for forming narrow vertical pillars and integrated circuit devices having the same |
US9082966B2 (en) | 2013-09-26 | 2015-07-14 | Micron Technology, Inc. | Methods of forming semiconductor devices and structures with improved planarization, uniformity |
US9306165B2 (en) | 2014-03-27 | 2016-04-05 | Micron Technology, Inc. | Replacement materials processes for forming cross point memory |
US9601577B1 (en) * | 2015-10-08 | 2017-03-21 | Samsung Electronics Co., Ltd. | Three-dimensionally integrated circuit devices including oxidation suppression layers |
CN109687864A (zh) * | 2017-10-19 | 2019-04-26 | 成都海存艾匹科技有限公司 | 含有可编程计算单元的可编程门阵列 |
KR102465967B1 (ko) | 2016-02-22 | 2022-11-10 | 삼성전자주식회사 | 메모리 소자 및 그 제조방법 |
KR101825318B1 (ko) | 2017-01-03 | 2018-02-05 | 고려대학교 산학협력단 | 스핀필터 구조체를 포함하는 자기 터널 접합 소자 |
WO2019066898A1 (en) * | 2017-09-29 | 2019-04-04 | Intel Corporation | SELF-ALIGNED INTEGRATED PHASE CHANGE MEMORY CELL |
US10741560B2 (en) | 2017-10-26 | 2020-08-11 | International Business Machines Corporation | High resistance readout FET for cognitive device |
US10297750B1 (en) | 2017-11-16 | 2019-05-21 | International Business Machines Corporation | Wraparound top electrode line for crossbar array resistive switching device |
US10937832B2 (en) | 2018-06-21 | 2021-03-02 | Macronix International Co., Ltd. | 3D memory with confined cell |
US10803933B2 (en) | 2018-08-21 | 2020-10-13 | International Business Machines Corporation | Self-aligned high density and size adjustable phase change memory |
TWI735031B (zh) | 2019-08-26 | 2021-08-01 | 華邦電子股份有限公司 | 電阻式隨機存取記憶體結構及其製造方法 |
CN112041997B (zh) * | 2020-07-27 | 2024-01-12 | 长江先进存储产业创新中心有限责任公司 | 用于3D X-Point存储器的具有减小的编程电流和热串扰的新单元结构 |
CN112449726A (zh) * | 2020-10-12 | 2021-03-05 | 长江先进存储产业创新中心有限责任公司 | 用于3d交叉点存储器的具有减小的编程电流和热串扰的新型缩小单元结构和制造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101685826A (zh) * | 2008-03-31 | 2010-03-31 | 旺宏电子股份有限公司 | 一种具有二极管驱动器的存储阵列及其制造方法 |
Family Cites Families (336)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3271591A (en) | 1963-09-20 | 1966-09-06 | Energy Conversion Devices Inc | Symmetrical current controlling device |
US3530441A (en) | 1969-01-15 | 1970-09-22 | Energy Conversion Devices Inc | Method and apparatus for storing and retrieving information |
US3846767A (en) | 1973-10-24 | 1974-11-05 | Energy Conversion Devices Inc | Method and means for resetting filament-forming memory semiconductor device |
IL61678A (en) | 1979-12-13 | 1984-04-30 | Energy Conversion Devices Inc | Programmable cell and programmable electronic arrays comprising such cells |
US4452592A (en) | 1982-06-01 | 1984-06-05 | General Motors Corporation | Cyclic phase change coupling |
US4676220A (en) | 1985-02-19 | 1987-06-30 | Pietraszek Mitchell E | Arrow rest |
US4876220A (en) | 1986-05-16 | 1989-10-24 | Actel Corporation | Method of making programmable low impedance interconnect diode element |
JP2685770B2 (ja) | 1987-12-28 | 1997-12-03 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JP2606857B2 (ja) | 1987-12-10 | 1997-05-07 | 株式会社日立製作所 | 半導体記憶装置の製造方法 |
US5534712A (en) | 1991-01-18 | 1996-07-09 | Energy Conversion Devices, Inc. | Electrically erasable memory elements characterized by reduced current and improved thermal stability |
US5166758A (en) | 1991-01-18 | 1992-11-24 | Energy Conversion Devices, Inc. | Electrically erasable phase change memory |
US5177567A (en) | 1991-07-19 | 1993-01-05 | Energy Conversion Devices, Inc. | Thin-film structure for chalcogenide electrical switching devices and process therefor |
JP2825031B2 (ja) | 1991-08-06 | 1998-11-18 | 日本電気株式会社 | 半導体メモリ装置 |
US5166096A (en) | 1991-10-29 | 1992-11-24 | International Business Machines Corporation | Process for fabricating self-aligned contact studs for semiconductor structures |
JPH05206394A (ja) | 1992-01-24 | 1993-08-13 | Mitsubishi Electric Corp | 電界効果トランジスタおよびその製造方法 |
US5958358A (en) | 1992-07-08 | 1999-09-28 | Yeda Research And Development Co., Ltd. | Oriented polycrystalline thin films of transition metal chalcogenides |
JP2884962B2 (ja) | 1992-10-30 | 1999-04-19 | 日本電気株式会社 | 半導体メモリ |
US5515488A (en) | 1994-08-30 | 1996-05-07 | Xerox Corporation | Method and apparatus for concurrent graphical visualization of a database search and its search history |
US5785828A (en) | 1994-12-13 | 1998-07-28 | Ricoh Company, Ltd. | Sputtering target for producing optical recording medium |
US5789758A (en) | 1995-06-07 | 1998-08-04 | Micron Technology, Inc. | Chalcogenide memory cell with a plurality of chalcogenide electrodes |
US5869843A (en) | 1995-06-07 | 1999-02-09 | Micron Technology, Inc. | Memory array having a multi-state element and method for forming such array or cells thereof |
US5879955A (en) | 1995-06-07 | 1999-03-09 | Micron Technology, Inc. | Method for fabricating an array of ultra-small pores for chalcogenide memory cells |
US5831276A (en) | 1995-06-07 | 1998-11-03 | Micron Technology, Inc. | Three-dimensional container diode for use with multi-state material in a non-volatile memory cell |
US6420725B1 (en) | 1995-06-07 | 2002-07-16 | Micron Technology, Inc. | Method and apparatus for forming an integrated circuit electrode having a reduced contact area |
US5837564A (en) | 1995-11-01 | 1998-11-17 | Micron Technology, Inc. | Method for optimal crystallization to obtain high electrical performance from chalcogenides |
KR0182866B1 (ko) | 1995-12-27 | 1999-04-15 | 김주용 | 플래쉬 메모리 장치 |
US5687112A (en) | 1996-04-19 | 1997-11-11 | Energy Conversion Devices, Inc. | Multibit single cell memory element having tapered contact |
US5866928A (en) | 1996-07-16 | 1999-02-02 | Micron Technology, Inc. | Single digit line with cell contact interconnect |
US5814527A (en) | 1996-07-22 | 1998-09-29 | Micron Technology, Inc. | Method of making small pores defined by a disposable internal spacer for use in chalcogenide memories |
US6337266B1 (en) | 1996-07-22 | 2002-01-08 | Micron Technology, Inc. | Small electrode for chalcogenide memories |
US5985698A (en) | 1996-07-22 | 1999-11-16 | Micron Technology, Inc. | Fabrication of three dimensional container diode for use with multi-state material in a non-volatile memory cell |
US5789277A (en) | 1996-07-22 | 1998-08-04 | Micron Technology, Inc. | Method of making chalogenide memory device |
US5998244A (en) | 1996-08-22 | 1999-12-07 | Micron Technology, Inc. | Memory cell incorporating a chalcogenide element and method of making same |
US5688713A (en) | 1996-08-26 | 1997-11-18 | Vanguard International Semiconductor Corporation | Method of manufacturing a DRAM cell having a double-crown capacitor using polysilicon and nitride spacers |
US6147395A (en) | 1996-10-02 | 2000-11-14 | Micron Technology, Inc. | Method for fabricating a small area of contact between electrodes |
US6087674A (en) | 1996-10-28 | 2000-07-11 | Energy Conversion Devices, Inc. | Memory element with memory material comprising phase-change material and dielectric material |
US5716883A (en) | 1996-11-06 | 1998-02-10 | Vanguard International Semiconductor Corporation | Method of making increased surface area, storage node electrode, with narrow spaces between polysilicon columns |
US6015977A (en) | 1997-01-28 | 2000-01-18 | Micron Technology, Inc. | Integrated circuit memory cell having a small active area and method of forming same |
US5804477A (en) | 1997-02-24 | 1998-09-08 | Integrated Device Technology, Inc. | Method of making a 6-transistor compact static ram cell |
US5952671A (en) | 1997-05-09 | 1999-09-14 | Micron Technology, Inc. | Small electrode for a chalcogenide switching device and method for fabricating same |
US6031287A (en) | 1997-06-18 | 2000-02-29 | Micron Technology, Inc. | Contact structure and memory element incorporating the same |
US5933365A (en) | 1997-06-19 | 1999-08-03 | Energy Conversion Devices, Inc. | Memory element with energy control mechanism |
US5902704A (en) | 1997-07-02 | 1999-05-11 | Lsi Logic Corporation | Process for forming photoresist mask over integrated circuit structures with critical dimension control |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6617192B1 (en) | 1997-10-01 | 2003-09-09 | Ovonyx, Inc. | Electrically programmable memory element with multi-regioned contact |
US6969866B1 (en) | 1997-10-01 | 2005-11-29 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
US7023009B2 (en) | 1997-10-01 | 2006-04-04 | Ovonyx, Inc. | Electrically programmable memory element with improved contacts |
FR2774209B1 (fr) | 1998-01-23 | 2001-09-14 | St Microelectronics Sa | Procede de controle du circuit de lecture d'un plan memoire et dispositif de memoire correspondant |
US6087269A (en) | 1998-04-20 | 2000-07-11 | Advanced Micro Devices, Inc. | Method of making an interconnect using a tungsten hard mask |
US6372651B1 (en) | 1998-07-17 | 2002-04-16 | Advanced Micro Devices, Inc. | Method for trimming a photoresist pattern line for memory gate etching |
US6141260A (en) | 1998-08-27 | 2000-10-31 | Micron Technology, Inc. | Single electron resistor memory device and method for use thereof |
US6034882A (en) | 1998-11-16 | 2000-03-07 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6351406B1 (en) | 1998-11-16 | 2002-02-26 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
US6483736B2 (en) | 1998-11-16 | 2002-11-19 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
JP2000164830A (ja) | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | 半導体記憶装置の製造方法 |
US6487106B1 (en) | 1999-01-12 | 2002-11-26 | Arizona Board Of Regents | Programmable microelectronic devices and method of forming and programming same |
US6291137B1 (en) | 1999-01-20 | 2001-09-18 | Advanced Micro Devices, Inc. | Sidewall formation for sidewall patterning of sub 100 nm structures |
US6245669B1 (en) | 1999-02-05 | 2001-06-12 | Taiwan Semiconductor Manufacturing Company | High selectivity Si-rich SiON etch-stop layer |
US6750079B2 (en) | 1999-03-25 | 2004-06-15 | Ovonyx, Inc. | Method for making programmable resistance memory element |
US6943365B2 (en) | 1999-03-25 | 2005-09-13 | Ovonyx, Inc. | Electrically programmable memory element with reduced area of contact and method for making same |
BR0009308A (pt) | 1999-03-25 | 2001-12-18 | Energy Conversion Devices Inc | Elemento de memória |
US6177317B1 (en) | 1999-04-14 | 2001-01-23 | Macronix International Co., Ltd. | Method of making nonvolatile memory devices having reduced resistance diffusion regions |
US6075719A (en) | 1999-06-22 | 2000-06-13 | Energy Conversion Devices, Inc. | Method of programming phase-change memory element |
US6214958B1 (en) | 1999-07-21 | 2001-04-10 | Arco Chemical Technology, L.P. | Process for preparing comb-branched polymers |
US6077674A (en) | 1999-10-27 | 2000-06-20 | Agilent Technologies Inc. | Method of producing oligonucleotide arrays with features of high purity |
US6326307B1 (en) | 1999-11-15 | 2001-12-04 | Appllied Materials, Inc. | Plasma pretreatment of photoresist in an oxide etch process |
US6314014B1 (en) | 1999-12-16 | 2001-11-06 | Ovonyx, Inc. | Programmable resistance memory arrays with reference cells |
US6576546B2 (en) | 1999-12-22 | 2003-06-10 | Texas Instruments Incorporated | Method of enhancing adhesion of a conductive barrier layer to an underlying conductive plug and contact for ferroelectric applications |
TW586154B (en) | 2001-01-05 | 2004-05-01 | Macronix Int Co Ltd | Planarization method for semiconductor device |
US6687307B1 (en) | 2000-02-24 | 2004-02-03 | Cisco Technology, Inc | Low memory and low latency cyclic prefix addition |
US6420216B1 (en) | 2000-03-14 | 2002-07-16 | International Business Machines Corporation | Fuse processing using dielectric planarization pillars |
US6444557B1 (en) | 2000-03-14 | 2002-09-03 | International Business Machines Corporation | Method of forming a damascene structure using a sacrificial conductive layer |
US6888750B2 (en) | 2000-04-28 | 2005-05-03 | Matrix Semiconductor, Inc. | Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication |
US6420215B1 (en) | 2000-04-28 | 2002-07-16 | Matrix Semiconductor, Inc. | Three-dimensional memory array and method of fabrication |
ATE347299T1 (de) | 2000-06-02 | 2006-12-15 | A Robert A Spitzer | Anti-tropf-becken |
US6501111B1 (en) | 2000-06-30 | 2002-12-31 | Intel Corporation | Three-dimensional (3D) programmable device |
US6563156B2 (en) | 2001-03-15 | 2003-05-13 | Micron Technology, Inc. | Memory elements and methods for making same |
US6440837B1 (en) | 2000-07-14 | 2002-08-27 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
US6512263B1 (en) | 2000-09-22 | 2003-01-28 | Sandisk Corporation | Non-volatile memory cell array having discontinuous source and drain diffusions contacted by continuous bit line conductors and methods of forming |
US6339544B1 (en) | 2000-09-29 | 2002-01-15 | Intel Corporation | Method to enhance performance of thermal resistor device |
US6567293B1 (en) | 2000-09-29 | 2003-05-20 | Ovonyx, Inc. | Single level metal memory cell using chalcogenide cladding |
US6429064B1 (en) | 2000-09-29 | 2002-08-06 | Intel Corporation | Reduced contact area of sidewall conductor |
US6555860B2 (en) | 2000-09-29 | 2003-04-29 | Intel Corporation | Compositionally modified resistive electrode |
KR100382729B1 (ko) | 2000-12-09 | 2003-05-09 | 삼성전자주식회사 | 반도체 소자의 금속 컨택 구조체 및 그 형성방법 |
US6569705B2 (en) | 2000-12-21 | 2003-05-27 | Intel Corporation | Metal structure for a phase-change memory device |
TW490675B (en) | 2000-12-22 | 2002-06-11 | Macronix Int Co Ltd | Control method of multi-stated NROM |
US6271090B1 (en) | 2000-12-22 | 2001-08-07 | Macronix International Co., Ltd. | Method for manufacturing flash memory device with dual floating gates and two bits per cell |
US6627530B2 (en) | 2000-12-22 | 2003-09-30 | Matrix Semiconductor, Inc. | Patterning three dimensional structures |
US6534781B2 (en) | 2000-12-26 | 2003-03-18 | Ovonyx, Inc. | Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact |
CN101174633A (zh) | 2001-01-30 | 2008-05-07 | 株式会社日立制作所 | 半导体集成电路器件及其制造方法 |
KR100400037B1 (ko) | 2001-02-22 | 2003-09-29 | 삼성전자주식회사 | 콘택 플러그를 구비하는 반도체 소자 및 그의 제조 방법 |
US6487114B2 (en) | 2001-02-28 | 2002-11-26 | Macronix International Co., Ltd. | Method of reading two-bit memories of NROM cell |
US6596589B2 (en) | 2001-04-30 | 2003-07-22 | Vanguard International Semiconductor Corporation | Method of manufacturing a high coupling ratio stacked gate flash memory with an HSG-SI layer |
US6730928B2 (en) | 2001-05-09 | 2004-05-04 | Science Applications International Corporation | Phase change switches and circuits coupling to electromagnetic waves containing phase change switches |
US7102150B2 (en) | 2001-05-11 | 2006-09-05 | Harshfield Steven T | PCRAM memory cell and method of making same |
US6514788B2 (en) | 2001-05-29 | 2003-02-04 | Bae Systems Information And Electronic Systems Integration Inc. | Method for manufacturing contacts for a Chalcogenide memory device |
DE10128482A1 (de) | 2001-06-12 | 2003-01-02 | Infineon Technologies Ag | Halbleiterspeichereinrichtung sowie Verfahren zu deren Herstellung |
US6774387B2 (en) | 2001-06-26 | 2004-08-10 | Ovonyx, Inc. | Programmable resistance memory element |
US6613604B2 (en) | 2001-08-02 | 2003-09-02 | Ovonyx, Inc. | Method for making small pore for use in programmable resistance memory element |
US6589714B2 (en) | 2001-06-26 | 2003-07-08 | Ovonyx, Inc. | Method for making programmable resistance memory element using silylated photoresist |
US6511867B2 (en) | 2001-06-30 | 2003-01-28 | Ovonyx, Inc. | Utilizing atomic layer deposition for programmable device |
US6673700B2 (en) | 2001-06-30 | 2004-01-06 | Ovonyx, Inc. | Reduced area intersection between electrode and programming element |
US6605527B2 (en) | 2001-06-30 | 2003-08-12 | Intel Corporation | Reduced area intersection between electrode and programming element |
US6643165B2 (en) | 2001-07-25 | 2003-11-04 | Nantero, Inc. | Electromechanical memory having cell selection circuitry constructed with nanotube technology |
US6737312B2 (en) | 2001-08-27 | 2004-05-18 | Micron Technology, Inc. | Method of fabricating dual PCRAM cells sharing a common electrode |
US6709958B2 (en) | 2001-08-30 | 2004-03-23 | Micron Technology, Inc. | Integrated circuit device and fabrication using metal-doped chalcogenide materials |
US6507061B1 (en) | 2001-08-31 | 2003-01-14 | Intel Corporation | Multiple layer phase-change memory |
US6764894B2 (en) | 2001-08-31 | 2004-07-20 | Ovonyx, Inc. | Elevated pore phase-change memory |
US6586761B2 (en) | 2001-09-07 | 2003-07-01 | Intel Corporation | Phase change material memory device |
US6861267B2 (en) | 2001-09-17 | 2005-03-01 | Intel Corporation | Reducing shunts in memories with phase-change material |
US7045383B2 (en) | 2001-09-19 | 2006-05-16 | BAE Systems Information and Ovonyx, Inc | Method for making tapered opening for programmable resistance memory element |
US6800563B2 (en) | 2001-10-11 | 2004-10-05 | Ovonyx, Inc. | Forming tapered lower electrode phase-change memories |
US6566700B2 (en) | 2001-10-11 | 2003-05-20 | Ovonyx, Inc. | Carbon-containing interfacial layer for phase-change memory |
US6791859B2 (en) | 2001-11-20 | 2004-09-14 | Micron Technology, Inc. | Complementary bit PCRAM sense amplifier and method of operation |
US6545903B1 (en) | 2001-12-17 | 2003-04-08 | Texas Instruments Incorporated | Self-aligned resistive plugs for forming memory cell with phase change material |
US6512241B1 (en) | 2001-12-31 | 2003-01-28 | Intel Corporation | Phase change material memory device |
US6867638B2 (en) | 2002-01-10 | 2005-03-15 | Silicon Storage Technology, Inc. | High voltage generation and regulation system for digital multilevel nonvolatile memory |
JP3948292B2 (ja) | 2002-02-01 | 2007-07-25 | 株式会社日立製作所 | 半導体記憶装置及びその製造方法 |
US6972430B2 (en) | 2002-02-20 | 2005-12-06 | Stmicroelectronics S.R.L. | Sublithographic contact structure, phase change memory cell with optimized heater shape, and manufacturing method thereof |
US7151273B2 (en) | 2002-02-20 | 2006-12-19 | Micron Technology, Inc. | Silver-selenide/chalcogenide glass stack for resistance variable memory |
US7122281B2 (en) | 2002-02-26 | 2006-10-17 | Synopsys, Inc. | Critical dimension control using full phase and trim masks |
JP3796457B2 (ja) | 2002-02-28 | 2006-07-12 | 富士通株式会社 | 不揮発性半導体記憶装置 |
WO2003079463A2 (en) | 2002-03-15 | 2003-09-25 | Axon Technologies Corporation | Programmable structure, an array including the structure, and methods of forming the same |
US6579760B1 (en) | 2002-03-28 | 2003-06-17 | Macronix International Co., Ltd. | Self-aligned, programmable phase change memory |
US6620715B1 (en) | 2002-03-29 | 2003-09-16 | Cypress Semiconductor Corp. | Method for forming sub-critical dimension structures in an integrated circuit |
US6670628B2 (en) | 2002-04-04 | 2003-12-30 | Hewlett-Packard Company, L.P. | Low heat loss and small contact area composite electrode for a phase change media memory device |
JP3624291B2 (ja) | 2002-04-09 | 2005-03-02 | 松下電器産業株式会社 | 不揮発性メモリおよびその製造方法 |
US6864500B2 (en) | 2002-04-10 | 2005-03-08 | Micron Technology, Inc. | Programmable conductor memory cell structure |
US6605821B1 (en) | 2002-05-10 | 2003-08-12 | Hewlett-Packard Development Company, L.P. | Phase change material electronic memory structure and method for forming |
US6864503B2 (en) | 2002-08-09 | 2005-03-08 | Macronix International Co., Ltd. | Spacer chalcogenide memory method and device |
US6850432B2 (en) | 2002-08-20 | 2005-02-01 | Macronix International Co., Ltd. | Laser programmable electrically readable phase-change memory method and device |
JP4133141B2 (ja) | 2002-09-10 | 2008-08-13 | 株式会社エンプラス | 電気部品用ソケット |
EP1537584B1 (en) | 2002-09-11 | 2017-10-25 | Ovonyx Memory Technology, LLC | Programming a phase-change material memory |
JP4190238B2 (ja) | 2002-09-13 | 2008-12-03 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置 |
JP2006502578A (ja) | 2002-10-11 | 2006-01-19 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | 相変化材料を備えた電子装置 |
US6992932B2 (en) | 2002-10-29 | 2006-01-31 | Saifun Semiconductors Ltd | Method circuit and system for read error detection in a non-volatile memory array |
JP4928045B2 (ja) | 2002-10-31 | 2012-05-09 | 大日本印刷株式会社 | 相変化型メモリ素子およびその製造方法 |
US6940744B2 (en) | 2002-10-31 | 2005-09-06 | Unity Semiconductor Corporation | Adaptive programming technique for a re-writable conductive memory device |
US7589343B2 (en) | 2002-12-13 | 2009-09-15 | Intel Corporation | Memory and access device and method therefor |
US6869883B2 (en) | 2002-12-13 | 2005-03-22 | Ovonyx, Inc. | Forming phase change memories |
US6744088B1 (en) | 2002-12-13 | 2004-06-01 | Intel Corporation | Phase change memory device on a planar composite layer |
US7314776B2 (en) | 2002-12-13 | 2008-01-01 | Ovonyx, Inc. | Method to manufacture a phase change memory |
US6791102B2 (en) | 2002-12-13 | 2004-09-14 | Intel Corporation | Phase change memory |
US6815266B2 (en) | 2002-12-30 | 2004-11-09 | Bae Systems Information And Electronic Systems Integration, Inc. | Method for manufacturing sidewall contacts for a chalcogenide memory device |
EP1439583B1 (en) | 2003-01-15 | 2013-04-10 | STMicroelectronics Srl | Sublithographic contact structure, in particular for a phase change memory cell, and fabrication process thereof |
KR100476690B1 (ko) | 2003-01-17 | 2005-03-18 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
EP1593126B1 (en) | 2003-01-31 | 2009-03-25 | Nxp B.V. | Mram architecture for low power consumption and high selectivity |
KR100486306B1 (ko) | 2003-02-24 | 2005-04-29 | 삼성전자주식회사 | 셀프 히터 구조를 가지는 상변화 메모리 소자 |
US7115927B2 (en) | 2003-02-24 | 2006-10-03 | Samsung Electronics Co., Ltd. | Phase changeable memory devices |
US7323734B2 (en) | 2003-02-25 | 2008-01-29 | Samsung Electronics Co., Ltd. | Phase changeable memory cells |
US6936544B2 (en) | 2003-03-11 | 2005-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of removing metal etching residues following a metal etchback process to improve a CMP process |
US7400522B2 (en) | 2003-03-18 | 2008-07-15 | Kabushiki Kaisha Toshiba | Resistance change memory device having a variable resistance element formed of a first and second composite compound for storing a cation |
KR100504698B1 (ko) | 2003-04-02 | 2005-08-02 | 삼성전자주식회사 | 상변화 기억 소자 및 그 형성 방법 |
JP4634014B2 (ja) | 2003-05-22 | 2011-02-16 | 株式会社日立製作所 | 半導体記憶装置 |
KR100979710B1 (ko) | 2003-05-23 | 2010-09-02 | 삼성전자주식회사 | 반도체 메모리 소자 및 제조방법 |
US20060006472A1 (en) | 2003-06-03 | 2006-01-12 | Hai Jiang | Phase change memory with extra-small resistors |
US7067865B2 (en) | 2003-06-06 | 2006-06-27 | Macronix International Co., Ltd. | High density chalcogenide memory cells |
US6838692B1 (en) | 2003-06-23 | 2005-01-04 | Macronix International Co., Ltd. | Chalcogenide memory device with multiple bits per cell |
US20050018526A1 (en) | 2003-07-21 | 2005-01-27 | Heon Lee | Phase-change memory device and manufacturing method thereof |
US7132350B2 (en) | 2003-07-21 | 2006-11-07 | Macronix International Co., Ltd. | Method for manufacturing a programmable eraseless memory |
KR100615586B1 (ko) | 2003-07-23 | 2006-08-25 | 삼성전자주식회사 | 다공성 유전막 내에 국부적인 상전이 영역을 구비하는상전이 메모리 소자 및 그 제조 방법 |
US7893419B2 (en) | 2003-08-04 | 2011-02-22 | Intel Corporation | Processing phase change material to improve programming speed |
US20050029267A1 (en) | 2003-08-05 | 2005-02-10 | Sonoco Development, Inc. | Container having a cut panel lid with a pull feature |
DE102004039977B4 (de) | 2003-08-13 | 2008-09-11 | Samsung Electronics Co., Ltd., Suwon | Programmierverfahren und Treiberschaltung für eine Phasenwechselspeicherzelle |
US6815704B1 (en) | 2003-09-04 | 2004-11-09 | Silicon Storage Technology, Inc. | Phase change memory device employing thermally insulating voids |
US6927410B2 (en) | 2003-09-04 | 2005-08-09 | Silicon Storage Technology, Inc. | Memory device with discrete layers of phase change memory material |
KR100505709B1 (ko) | 2003-09-08 | 2005-08-03 | 삼성전자주식회사 | 상 변화 메모리 장치의 파이어링 방법 및 효율적인파이어링을 수행할 수 있는 상 변화 메모리 장치 |
US20050062087A1 (en) | 2003-09-19 | 2005-03-24 | Yi-Chou Chen | Chalcogenide phase-change non-volatile memory, memory device and method for fabricating the same |
DE10345455A1 (de) | 2003-09-30 | 2005-05-04 | Infineon Technologies Ag | Verfahren zum Erzeugen einer Hartmaske und Hartmasken-Anordnung |
US6910907B2 (en) | 2003-11-18 | 2005-06-28 | Agere Systems Inc. | Contact for use in an integrated circuit and a method of manufacture therefor |
US6808991B1 (en) | 2003-11-19 | 2004-10-26 | Macronix International Co., Ltd. | Method for forming twin bit cell flash memory |
US7485891B2 (en) | 2003-11-20 | 2009-02-03 | International Business Machines Corporation | Multi-bit phase change memory cell and multi-bit phase change memory including the same, method of forming a multi-bit phase change memory, and method of programming a multi-bit phase change memory |
KR100558548B1 (ko) | 2003-11-27 | 2006-03-10 | 삼성전자주식회사 | 상변화 메모리 소자에서의 라이트 드라이버 회로 및라이트 전류 인가방법 |
US6937507B2 (en) | 2003-12-05 | 2005-08-30 | Silicon Storage Technology, Inc. | Memory device and method of operating same |
US7928420B2 (en) | 2003-12-10 | 2011-04-19 | International Business Machines Corporation | Phase change tip storage cell |
US7291556B2 (en) | 2003-12-12 | 2007-11-06 | Samsung Electronics Co., Ltd. | Method for forming small features in microelectronic devices using sacrificial layers |
US7265050B2 (en) | 2003-12-12 | 2007-09-04 | Samsung Electronics Co., Ltd. | Methods for fabricating memory devices using sacrificial layers |
KR100569549B1 (ko) | 2003-12-13 | 2006-04-10 | 주식회사 하이닉스반도체 | 상 변화 저항 셀 및 이를 이용한 불휘발성 메모리 장치 |
KR100564602B1 (ko) | 2003-12-30 | 2006-03-29 | 삼성전자주식회사 | 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로 |
US7038230B2 (en) | 2004-01-06 | 2006-05-02 | Macronix Internation Co., Ltd. | Horizontal chalcogenide element defined by a pad for use in solid-state memories |
JP4124743B2 (ja) | 2004-01-21 | 2008-07-23 | 株式会社ルネサステクノロジ | 相変化メモリ |
KR100564608B1 (ko) | 2004-01-29 | 2006-03-28 | 삼성전자주식회사 | 상변화 메모리 소자 |
US6936840B2 (en) | 2004-01-30 | 2005-08-30 | International Business Machines Corporation | Phase-change memory cell and method of fabricating the phase-change memory cell |
US7858980B2 (en) | 2004-03-01 | 2010-12-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Reduced active area in a phase change memory structure |
KR100574975B1 (ko) | 2004-03-05 | 2006-05-02 | 삼성전자주식회사 | 상 변화 메모리 어레이의 셋 프로그래밍 방법 및 기입드라이버 회로 |
JP4529493B2 (ja) | 2004-03-12 | 2010-08-25 | 株式会社日立製作所 | 半導体装置 |
KR100598100B1 (ko) | 2004-03-19 | 2006-07-07 | 삼성전자주식회사 | 상변환 기억 소자의 제조방법 |
DE102004014487A1 (de) | 2004-03-24 | 2005-11-17 | Infineon Technologies Ag | Speicherbauelement mit in isolierendes Material eingebettetem, aktiven Material |
KR100532509B1 (ko) | 2004-03-26 | 2005-11-30 | 삼성전자주식회사 | SiGe를 이용한 트렌치 커패시터 및 그 형성방법 |
US7158411B2 (en) | 2004-04-01 | 2007-01-02 | Macronix International Co., Ltd. | Integrated code and data flash memory |
US7482616B2 (en) | 2004-05-27 | 2009-01-27 | Samsung Electronics Co., Ltd. | Semiconductor devices having phase change memory cells, electronic systems employing the same and methods of fabricating the same |
US6977181B1 (en) | 2004-06-17 | 2005-12-20 | Infincon Technologies Ag | MTJ stack with crystallization inhibiting layer |
KR100668825B1 (ko) | 2004-06-30 | 2007-01-16 | 주식회사 하이닉스반도체 | 상변화 기억 소자 및 그 제조방법 |
US7359231B2 (en) | 2004-06-30 | 2008-04-15 | Intel Corporation | Providing current for phase change memories |
DE102004035830A1 (de) | 2004-07-23 | 2006-02-16 | Infineon Technologies Ag | Speicherbauelement mit thermischen Isolationsschichten |
KR100657897B1 (ko) | 2004-08-21 | 2006-12-14 | 삼성전자주식회사 | 전압 제어층을 포함하는 메모리 소자 |
US7365385B2 (en) | 2004-08-30 | 2008-04-29 | Micron Technology, Inc. | DRAM layout with vertical FETs and method of formation |
KR100610014B1 (ko) | 2004-09-06 | 2006-08-09 | 삼성전자주식회사 | 리키지 전류 보상 가능한 반도체 메모리 장치 |
US7443062B2 (en) | 2004-09-30 | 2008-10-28 | Reliance Electric Technologies Llc | Motor rotor cooling with rotation heat pipes |
US7023008B1 (en) | 2004-09-30 | 2006-04-04 | Infineon Technologies Ag | Resistive memory element |
TWI277207B (en) | 2004-10-08 | 2007-03-21 | Ind Tech Res Inst | Multilevel phase-change memory, operating method and manufacture method thereof |
KR100626388B1 (ko) | 2004-10-19 | 2006-09-20 | 삼성전자주식회사 | 상변환 메모리 소자 및 그 형성 방법 |
JP2006127583A (ja) | 2004-10-26 | 2006-05-18 | Elpida Memory Inc | 不揮発性半導体記憶装置及び相変化メモリ |
DE102004052611A1 (de) | 2004-10-29 | 2006-05-04 | Infineon Technologies Ag | Verfahren zur Herstellung einer mit einem Füllmaterial mindestens teilweise gefüllten Öffnung, Verfahren zur Herstellung einer Speicherzelle und Speicherzelle |
US7364935B2 (en) | 2004-10-29 | 2008-04-29 | Macronix International Co., Ltd. | Common word line edge contact phase-change memory |
US7238959B2 (en) | 2004-11-01 | 2007-07-03 | Silicon Storage Technology, Inc. | Phase change memory device employing thermally insulating voids and sloped trench, and a method of making same |
US20060108667A1 (en) | 2004-11-22 | 2006-05-25 | Macronix International Co., Ltd. | Method for manufacturing a small pin on integrated circuits or other devices |
US7202493B2 (en) | 2004-11-30 | 2007-04-10 | Macronix International Co., Inc. | Chalcogenide memory having a small active region |
JP2006156886A (ja) | 2004-12-01 | 2006-06-15 | Renesas Technology Corp | 半導体集積回路装置およびその製造方法 |
KR100827653B1 (ko) | 2004-12-06 | 2008-05-07 | 삼성전자주식회사 | 상변화 기억 셀들 및 그 제조방법들 |
DE102004059428A1 (de) | 2004-12-09 | 2006-06-22 | Infineon Technologies Ag | Herstellungsverfahren für eine mikroelektronische Elektrodenstruktur, insbesondere für ein PCM-Speicherelement, und entsprechende mikroelektronische Elektrodenstruktur |
US7220983B2 (en) | 2004-12-09 | 2007-05-22 | Macronix International Co., Ltd. | Self-aligned small contact phase-change memory method and device |
TWI260764B (en) | 2004-12-10 | 2006-08-21 | Macronix Int Co Ltd | Non-volatile memory cell and operating method thereof |
US20060131555A1 (en) | 2004-12-22 | 2006-06-22 | Micron Technology, Inc. | Resistance variable devices with controllable channels |
US20060138467A1 (en) | 2004-12-29 | 2006-06-29 | Hsiang-Lan Lung | Method of forming a small contact in phase-change memory and a memory cell produced by the method |
JP4646634B2 (ja) | 2005-01-05 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US7419771B2 (en) | 2005-01-11 | 2008-09-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming a finely patterned resist |
EP1684352B1 (en) | 2005-01-21 | 2008-09-17 | STMicroelectronics S.r.l. | Phase-change memory device and manufacturing process thereof |
US20060172067A1 (en) | 2005-01-28 | 2006-08-03 | Energy Conversion Devices, Inc | Chemical vapor deposition of chalcogenide materials |
US20060169968A1 (en) | 2005-02-01 | 2006-08-03 | Thomas Happ | Pillar phase change memory cell |
US7214958B2 (en) | 2005-02-10 | 2007-05-08 | Infineon Technologies Ag | Phase change memory cell with high read margin at low power operation |
US7099180B1 (en) | 2005-02-15 | 2006-08-29 | Intel Corporation | Phase change memory bits reset through a series of pulses of increasing amplitude |
US7229883B2 (en) | 2005-02-23 | 2007-06-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase change memory device and method of manufacture thereof |
KR100668333B1 (ko) | 2005-02-25 | 2007-01-12 | 삼성전자주식회사 | Pram 소자 및 그 제조방법 |
JP2006244561A (ja) | 2005-03-01 | 2006-09-14 | Renesas Technology Corp | 半導体装置 |
US7154774B2 (en) | 2005-03-30 | 2006-12-26 | Ovonyx, Inc. | Detecting switching of access elements of phase change memory cells |
US7488967B2 (en) | 2005-04-06 | 2009-02-10 | International Business Machines Corporation | Structure for confining the switching current in phase memory (PCM) cells |
DE602005011249D1 (de) | 2005-04-08 | 2009-01-08 | St Microelectronics Srl | Phasenwechselspeicher mit rohrförmiger Heizstruktur sowie deren Herstellungsverfahren |
US7166533B2 (en) | 2005-04-08 | 2007-01-23 | Infineon Technologies, Ag | Phase change memory cell defined by a pattern shrink material process |
KR100675279B1 (ko) | 2005-04-20 | 2007-01-26 | 삼성전자주식회사 | 셀 다이오드들을 채택하는 상변이 기억소자들 및 그제조방법들 |
US7408240B2 (en) | 2005-05-02 | 2008-08-05 | Infineon Technologies Ag | Memory device |
US7488968B2 (en) | 2005-05-05 | 2009-02-10 | Ovonyx, Inc. | Multilevel phase change memory |
KR100682946B1 (ko) | 2005-05-31 | 2007-02-15 | 삼성전자주식회사 | 상전이 램 및 그 동작 방법 |
KR100668846B1 (ko) | 2005-06-10 | 2007-01-16 | 주식회사 하이닉스반도체 | 상변환 기억 소자의 제조방법 |
US7388273B2 (en) | 2005-06-14 | 2008-06-17 | International Business Machines Corporation | Reprogrammable fuse structure and method |
US7696503B2 (en) | 2005-06-17 | 2010-04-13 | Macronix International Co., Ltd. | Multi-level memory cell having phase change element and asymmetrical thermal boundary |
US7514367B2 (en) | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Method for manufacturing a narrow structure on an integrated circuit |
US7534647B2 (en) | 2005-06-17 | 2009-05-19 | Macronix International Co., Ltd. | Damascene phase change RAM and manufacturing method |
US8237140B2 (en) | 2005-06-17 | 2012-08-07 | Macronix International Co., Ltd. | Self-aligned, embedded phase change RAM |
US7238994B2 (en) | 2005-06-17 | 2007-07-03 | Macronix International Co., Ltd. | Thin film plate phase change ram circuit and manufacturing method |
US7321130B2 (en) | 2005-06-17 | 2008-01-22 | Macronix International Co., Ltd. | Thin film fuse phase change RAM and manufacturing method |
US7514288B2 (en) | 2005-06-17 | 2009-04-07 | Macronix International Co., Ltd. | Manufacturing methods for thin film fuse phase change ram |
US7598512B2 (en) | 2005-06-17 | 2009-10-06 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation layer and manufacturing method |
US20060289848A1 (en) | 2005-06-28 | 2006-12-28 | Dennison Charles H | Reducing oxidation of phase change memory electrodes |
US20060289847A1 (en) | 2005-06-28 | 2006-12-28 | Richard Dodge | Reducing the time to program a phase change memory to the set state |
US7309630B2 (en) | 2005-07-08 | 2007-12-18 | Nanochip, Inc. | Method for forming patterned media for a high density data storage device |
US7233520B2 (en) | 2005-07-08 | 2007-06-19 | Micron Technology, Inc. | Process for erasing chalcogenide variable resistance memory bits |
TWI290369B (en) | 2005-07-08 | 2007-11-21 | Ind Tech Res Inst | Phase change memory with adjustable resistance ratio and fabricating method thereof |
US7345907B2 (en) | 2005-07-11 | 2008-03-18 | Sandisk 3D Llc | Apparatus and method for reading an array of nonvolatile memory cells including switchable resistor memory elements |
US20070037101A1 (en) | 2005-08-15 | 2007-02-15 | Fujitsu Limited | Manufacture method for micro structure |
TWI273703B (en) | 2005-08-19 | 2007-02-11 | Ind Tech Res Inst | A manufacture method and structure for improving the characteristics of phase change memory |
US20070045606A1 (en) | 2005-08-30 | 2007-03-01 | Michele Magistretti | Shaping a phase change layer in a phase change memory cell |
KR100655443B1 (ko) | 2005-09-05 | 2006-12-08 | 삼성전자주식회사 | 상변화 메모리 장치 및 그 동작 방법 |
US7615770B2 (en) | 2005-10-27 | 2009-11-10 | Infineon Technologies Ag | Integrated circuit having an insulated memory |
US7417245B2 (en) | 2005-11-02 | 2008-08-26 | Infineon Technologies Ag | Phase change memory having multilayer thermal insulation |
US7397060B2 (en) | 2005-11-14 | 2008-07-08 | Macronix International Co., Ltd. | Pipe shaped phase change memory |
US20070111429A1 (en) | 2005-11-14 | 2007-05-17 | Macronix International Co., Ltd. | Method of manufacturing a pipe shaped phase change memory |
US7635855B2 (en) | 2005-11-15 | 2009-12-22 | Macronix International Co., Ltd. | I-shaped phase change memory cell |
US7786460B2 (en) | 2005-11-15 | 2010-08-31 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7450411B2 (en) | 2005-11-15 | 2008-11-11 | Macronix International Co., Ltd. | Phase change memory device and manufacturing method |
US7394088B2 (en) | 2005-11-15 | 2008-07-01 | Macronix International Co., Ltd. | Thermally contained/insulated phase change memory device and method (combined) |
US7414258B2 (en) | 2005-11-16 | 2008-08-19 | Macronix International Co., Ltd. | Spacer electrode small pin phase change memory RAM and manufacturing method |
US7507986B2 (en) | 2005-11-21 | 2009-03-24 | Macronix International Co., Ltd. | Thermal isolation for an active-sidewall phase change memory cell |
US7479649B2 (en) | 2005-11-21 | 2009-01-20 | Macronix International Co., Ltd. | Vacuum jacketed electrode for phase change memory element |
US7449710B2 (en) | 2005-11-21 | 2008-11-11 | Macronix International Co., Ltd. | Vacuum jacket for phase change memory element |
US7829876B2 (en) | 2005-11-21 | 2010-11-09 | Macronix International Co., Ltd. | Vacuum cell thermal isolation for a phase change memory device |
US7599217B2 (en) | 2005-11-22 | 2009-10-06 | Macronix International Co., Ltd. | Memory cell device and manufacturing method |
US7688619B2 (en) | 2005-11-28 | 2010-03-30 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7459717B2 (en) | 2005-11-28 | 2008-12-02 | Macronix International Co., Ltd. | Phase change memory cell and manufacturing method |
US7233054B1 (en) | 2005-11-29 | 2007-06-19 | Korea Institute Of Science And Technology | Phase change material and non-volatile memory device using the same |
US7605079B2 (en) | 2005-12-05 | 2009-10-20 | Macronix International Co., Ltd. | Manufacturing method for phase change RAM with electrode layer process |
US7642539B2 (en) | 2005-12-13 | 2010-01-05 | Macronix International Co., Ltd. | Thin film fuse phase change cell with thermal isolation pad and manufacturing method |
ATE480873T1 (de) | 2005-12-20 | 2010-09-15 | Nxp Bv | Vertikale phasenwechsel-speicherzelle und herstellungsverfahren dafür |
US7655536B2 (en) * | 2005-12-21 | 2010-02-02 | Sandisk Corporation | Methods of forming flash devices with shared word lines |
US7531825B2 (en) | 2005-12-27 | 2009-05-12 | Macronix International Co., Ltd. | Method for forming self-aligned thermal isolation cell for a variable resistance memory array |
US8062833B2 (en) | 2005-12-30 | 2011-11-22 | Macronix International Co., Ltd. | Chalcogenide layer etching method |
US20070156949A1 (en) | 2005-12-30 | 2007-07-05 | Rudelic John C | Method and apparatus for single chip system boot |
US7292466B2 (en) | 2006-01-03 | 2007-11-06 | Infineon Technologies Ag | Integrated circuit having a resistive memory |
KR100763908B1 (ko) | 2006-01-05 | 2007-10-05 | 삼성전자주식회사 | 상전이 물질, 이를 포함하는 상전이 메모리와 이의 동작방법 |
US7560337B2 (en) | 2006-01-09 | 2009-07-14 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7595218B2 (en) | 2006-01-09 | 2009-09-29 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US7741636B2 (en) | 2006-01-09 | 2010-06-22 | Macronix International Co., Ltd. | Programmable resistive RAM and manufacturing method |
US20070158632A1 (en) | 2006-01-09 | 2007-07-12 | Macronix International Co., Ltd. | Method for Fabricating a Pillar-Shaped Phase Change Memory Element |
US7825396B2 (en) | 2006-01-11 | 2010-11-02 | Macronix International Co., Ltd. | Self-align planerized bottom electrode phase change memory and manufacturing method |
US7351648B2 (en) | 2006-01-19 | 2008-04-01 | International Business Machines Corporation | Methods for forming uniform lithographic features |
US7432206B2 (en) | 2006-01-24 | 2008-10-07 | Macronix International Co., Ltd. | Self-aligned manufacturing method, and manufacturing method for thin film fuse phase change ram |
US7456421B2 (en) | 2006-01-30 | 2008-11-25 | Macronix International Co., Ltd. | Vertical side wall active pin structures in a phase change memory and manufacturing methods |
US7956358B2 (en) | 2006-02-07 | 2011-06-07 | Macronix International Co., Ltd. | I-shaped phase change memory cell with thermal isolation |
US7426134B2 (en) | 2006-02-24 | 2008-09-16 | Infineon Technologies North America | Sense circuit for resistive memory |
US7910907B2 (en) | 2006-03-15 | 2011-03-22 | Macronix International Co., Ltd. | Manufacturing method for pipe-shaped electrode phase change memory |
US20070252127A1 (en) | 2006-03-30 | 2007-11-01 | Arnold John C | Phase change memory element with a peripheral connection to a thin film electrode and method of manufacture thereof |
US20070235811A1 (en) | 2006-04-07 | 2007-10-11 | International Business Machines Corporation | Simultaneous conditioning of a plurality of memory cells through series resistors |
US7928421B2 (en) | 2006-04-21 | 2011-04-19 | Macronix International Co., Ltd. | Phase change memory cell with vacuum spacer |
US20070249090A1 (en) | 2006-04-24 | 2007-10-25 | Philipp Jan B | Phase-change memory cell adapted to prevent over-etching or under-etching |
US7514705B2 (en) | 2006-04-25 | 2009-04-07 | International Business Machines Corporation | Phase change memory cell with limited switchable volume |
US8129706B2 (en) | 2006-05-05 | 2012-03-06 | Macronix International Co., Ltd. | Structures and methods of a bistable resistive random access memory |
US7608848B2 (en) | 2006-05-09 | 2009-10-27 | Macronix International Co., Ltd. | Bridge resistance random access memory device with a singular contact structure |
US20070267618A1 (en) | 2006-05-17 | 2007-11-22 | Shoaib Zaidi | Memory device |
US7423300B2 (en) | 2006-05-24 | 2008-09-09 | Macronix International Co., Ltd. | Single-mask phase change memory element |
US7696506B2 (en) | 2006-06-27 | 2010-04-13 | Macronix International Co., Ltd. | Memory cell with memory material insulation and manufacturing method |
US7663909B2 (en) | 2006-07-10 | 2010-02-16 | Qimonda North America Corp. | Integrated circuit having a phase change memory cell including a narrow active region width |
US7785920B2 (en) | 2006-07-12 | 2010-08-31 | Macronix International Co., Ltd. | Method for making a pillar-type phase change memory element |
US7542338B2 (en) | 2006-07-31 | 2009-06-02 | Sandisk 3D Llc | Method for reading a multi-level passive element memory cell array |
US7394089B2 (en) | 2006-08-25 | 2008-07-01 | International Business Machines Corporation | Heat-shielded low power PCM-based reprogrammable EFUSE device |
KR100760634B1 (ko) | 2006-10-02 | 2007-09-20 | 삼성전자주식회사 | 낸드형 비휘발성 기억 소자 및 그 형성 방법 |
US7684225B2 (en) | 2006-10-13 | 2010-03-23 | Ovonyx, Inc. | Sequential and video access for non-volatile memory arrays |
US20080225489A1 (en) | 2006-10-23 | 2008-09-18 | Teledyne Licensing, Llc | Heat spreader with high heat flux and high thermal conductivity |
US7863655B2 (en) | 2006-10-24 | 2011-01-04 | Macronix International Co., Ltd. | Phase change memory cells with dual access devices |
US20080101110A1 (en) | 2006-10-25 | 2008-05-01 | Thomas Happ | Combined read/write circuit for memory |
US7682868B2 (en) | 2006-12-06 | 2010-03-23 | Macronix International Co., Ltd. | Method for making a keyhole opening during the manufacture of a memory cell |
US7476587B2 (en) | 2006-12-06 | 2009-01-13 | Macronix International Co., Ltd. | Method for making a self-converged memory material element for memory cell |
US7473576B2 (en) | 2006-12-06 | 2009-01-06 | Macronix International Co., Ltd. | Method for making a self-converged void and bottom electrode for memory cell |
US20080137400A1 (en) | 2006-12-06 | 2008-06-12 | Macronix International Co., Ltd. | Phase Change Memory Cell with Thermal Barrier and Method for Fabricating the Same |
US20080165569A1 (en) | 2007-01-04 | 2008-07-10 | Chieh-Fang Chen | Resistance Limited Phase Change Memory Material |
US7515461B2 (en) | 2007-01-05 | 2009-04-07 | Macronix International Co., Ltd. | Current compliant sensing architecture for multilevel phase change memory |
US20080164453A1 (en) | 2007-01-07 | 2008-07-10 | Breitwisch Matthew J | Uniform critical dimension size pore for pcram application |
US7440315B2 (en) | 2007-01-09 | 2008-10-21 | Macronix International Co., Ltd. | Method, apparatus and computer program product for stepped reset programming process on programmable resistive memory cell |
US7456460B2 (en) | 2007-01-29 | 2008-11-25 | International Business Machines Corporation | Phase change memory element and method of making the same |
US7535756B2 (en) | 2007-01-31 | 2009-05-19 | Macronix International Co., Ltd. | Method to tighten set distribution for PCRAM |
US7701759B2 (en) | 2007-02-05 | 2010-04-20 | Macronix International Co., Ltd. | Memory cell device and programming methods |
US7463512B2 (en) | 2007-02-08 | 2008-12-09 | Macronix International Co., Ltd. | Memory element with reduced-current phase change element |
US8138028B2 (en) | 2007-02-12 | 2012-03-20 | Macronix International Co., Ltd | Method for manufacturing a phase change memory device with pillar bottom electrode |
US8008643B2 (en) | 2007-02-21 | 2011-08-30 | Macronix International Co., Ltd. | Phase change memory cell with heater and method for fabricating the same |
US7755076B2 (en) | 2007-04-17 | 2010-07-13 | Macronix International Co., Ltd. | 4F2 self align side wall active phase change memory |
US7569844B2 (en) | 2007-04-17 | 2009-08-04 | Macronix International Co., Ltd. | Memory cell sidewall contacting side electrode |
US20080265234A1 (en) | 2007-04-30 | 2008-10-30 | Breitwisch Matthew J | Method of Forming Phase Change Memory Cell With Reduced Switchable Volume |
US7545668B2 (en) | 2007-06-22 | 2009-06-09 | Qimonda North America Corp. | Mushroom phase change memory having a multilayer electrode |
US7906368B2 (en) | 2007-06-29 | 2011-03-15 | International Business Machines Corporation | Phase change memory with tapered heater |
US7745807B2 (en) | 2007-07-11 | 2010-06-29 | International Business Machines Corporation | Current constricting phase change memory element structure |
DE102008032067A1 (de) | 2007-07-12 | 2009-01-15 | Samsung Electronics Co., Ltd., Suwon | Verfahren zum Bilden von Phasenänderungsspeichern mit unteren Elektroden |
US7755935B2 (en) | 2007-07-26 | 2010-07-13 | International Business Machines Corporation | Block erase for phase change memory |
US7642125B2 (en) | 2007-09-14 | 2010-01-05 | Macronix International Co., Ltd. | Phase change memory cell in via array with self-aligned, self-converged bottom electrode and method for manufacturing |
US7838341B2 (en) * | 2008-03-14 | 2010-11-23 | Ovonyx, Inc. | Self-aligned memory cells and method for forming |
US7868313B2 (en) | 2008-04-29 | 2011-01-11 | International Business Machines Corporation | Phase change memory device and method of manufacture |
US8324605B2 (en) | 2008-10-02 | 2012-12-04 | Macronix International Co., Ltd. | Dielectric mesh isolated phase change structure for phase change memory |
US8198124B2 (en) * | 2010-01-05 | 2012-06-12 | Micron Technology, Inc. | Methods of self-aligned growth of chalcogenide memory access device |
-
2010
- 2010-10-06 US US12/899,232 patent/US8395935B2/en active Active
- 2010-12-29 TW TW099146717A patent/TWI426632B/zh active
-
2011
- 2011-02-22 CN CN201110043837.0A patent/CN102446547B/zh active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101685826A (zh) * | 2008-03-31 | 2010-03-31 | 旺宏电子股份有限公司 | 一种具有二极管驱动器的存储阵列及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
CN102446547A (zh) | 2012-05-09 |
TW201216539A (en) | 2012-04-16 |
TWI426632B (zh) | 2014-02-11 |
US20120087181A1 (en) | 2012-04-12 |
US8395935B2 (en) | 2013-03-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102446547B (zh) | 交点自对准的可编程存储装置 | |
US8624236B2 (en) | Phase change memory cell having vertical channel access transistor | |
CN102244194B (zh) | 自动对准的鳍型可编程存储单元 | |
US8168538B2 (en) | Buried silicide structure and method for making | |
US7755076B2 (en) | 4F2 self align side wall active phase change memory | |
US8158963B2 (en) | Programmable resistive RAM and manufacturing method | |
TWI387103B (zh) | 具有二極體存取裝置之完全自我對準微孔型記憶胞 | |
US7903457B2 (en) | Multiple phase change materials in an integrated circuit for system on a chip application | |
US8084760B2 (en) | Ring-shaped electrode and manufacturing method for same | |
US8350316B2 (en) | Phase change memory cells having vertical channel access transistor and memory plane | |
US8513637B2 (en) | 4F2 self align fin bottom electrodes FET drive phase change memory | |
US8933536B2 (en) | Polysilicon pillar bipolar transistor with self-aligned memory element | |
US8415651B2 (en) | Phase change memory cell having top and bottom sidewall contacts | |
US8497182B2 (en) | Sidewall thin film electrode with self-aligned top electrode and programmable resistance memory | |
US8110822B2 (en) | Thermal protect PCRAM structure and methods for making | |
US7820997B2 (en) | Resistor random access memory cell with reduced active area and reduced contact areas | |
US8237144B2 (en) | Polysilicon plug bipolar transistor for phase change memory | |
CN102290428A (zh) | 一种存储装置及其制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |