CN102318051B - 具有加固层的半导体芯片 - Google Patents

具有加固层的半导体芯片 Download PDF

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CN102318051B
CN102318051B CN201080008014.8A CN201080008014A CN102318051B CN 102318051 B CN102318051 B CN 102318051B CN 201080008014 A CN201080008014 A CN 201080008014A CN 102318051 B CN102318051 B CN 102318051B
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semiconductor chip
layer
raceway groove
frame part
middle body
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CN102318051A (zh
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M·苏
F·屈兴迈斯特
J·布拉沃
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Abstract

本发明揭露各种半导体芯片加固结构及其制作方法。在一态样中，提供一种制造方法包括提供具有侧面(40)的半导体芯片(15)及在该侧面(40)上形成聚合物层(60)。该聚合物层(60)具有中央部分(65)和空间上与该中央部分(65)分离的第一框部分(70)以定义第一沟道(80)。

Description

具有加固层的半导体芯片
技术领域
本发明通常是有关半导体工艺，尤其是有关半导体芯片裂缝阻挡和其制作方法。
背景技术
裂缝可以对传统半导体芯片精细的电路结构造成严重破坏。许多来源可以产生这样的裂缝。常见的来源是在切单(singulation)所给予的应力。传统半导体芯片经常集体大量制造作为单一半导体晶圆的一部分。在形成个别芯片的最后的工艺步骤中，在晶圆上执行所谓的切割(dicing)或切锯(sawing)操作以切出个别裸晶。此后，裸晶可被封装或直接安装在一种或另一种形式的印刷电路板。传统的半导体裸晶经常从晶圆切割出长方形的形状。根据定义，传统的半导体裸晶有四个边和四个角。切割操作是以同类型的圆形锯或者激光执行机械切割操作。切割机(dicing saws)是以较类似砖石(comparable masonry)圆形切锯更小心和操作更精确制成。尽管有这些改进，切割锯仍在切割个别的裸晶时施加显着的应力。切割操作时所负载的这些应力和冲击可能导致裸晶的微断裂，特别是在裸晶的角。一旦切割的裸晶安装在一种或另一种类型的封装衬底或印刷电路板，由于可能施加在裸晶上的热应力和其它机械应力，在切割时引入的裂缝可能会扩展到裸晶中心。此外，特别是在靠近角而由于其几何形状产生所谓的应力冒口(stress risers)，可能形成新的裂缝。
为解决从裸晶的角的裂缝的扩展的传统技术是有关裂缝阻挡的使用。传统的裂缝阻挡由在半导体裸晶的边缘之中和附近形成框架式结构所组成。当从上面看，裂缝阻挡看起来像图框。传统的裂缝阻挡是不延伸出传统裸晶的边缘。由于这种几何形状，从裸晶的角扩展的裂缝在遇到裸晶裂缝阻挡之前可达到明显的长度。如果裂缝在遇到传统的裂缝挡并之前达到一定临界长度，裂缝可成为几乎无法控制。裂缝可击败传统的裂缝阻挡并入侵半导体裸晶的主动部分和耗损位在其中的精细的电路结构。
另外潜在造成损害的裂缝的来源是凸块下聚酰亚胺(polyimide)层和底部填充材料层之间的接口的不足。在通过控制的倒塌工艺而安装在封装衬底的典型半导体芯片内，焊料接合(solder joints)阵列电连接芯片至底层衬底。此种安装建立垂直结合封装衬底附近一侧和聚酰亚胺层附近另一侧的接口区域。传统的聚酰亚胺层是覆盖半导体芯片前侧的连续薄层，。中性点，尽管通常不一定位在芯片的中心，其代表了实质零热应变的区域。在该区域中或附近的焊料接合遭受低应变。然而，从中性点向外的工艺，芯片和底层衬底开始表现出依赖于温度、热膨胀系数(CTE)和与该中性点的距离的热应变。衬底通常有比芯片的CTE大6至7倍的CTE。为了解决不同热膨胀系数的问题，底部填充材料沉积在半导体芯片的聚酰亚胺层和封装衬底之间并通过固化工艺硬化。
裂缝扩展在聚酰亚胺对底部填充接口或其附近开始和增长。随着裂缝长度增长，其驱动力增加。一旦裂缝已经获得临界的驱动力或所谓的“临界能量释放率”，裂缝将获得足够的能量穿透主动凸块并永久损坏封装器件。
用来补偿聚酰亚胺对底部填充的接口裂缝的传统技术是有关聚酰亚胺薄片表面的粗糙。在接口强度的增加是直接正比在接口区域的增加。然而，即使具有粗糙，在区域的增加可能相当小。
本发明是针对克服或减少上述的一个或多个问题的影响。
发明内容
依据本发明的一实施态样，提供一种制造方法，包括提供具有一侧面的半导体芯片和在该侧面上形成聚合物层。该聚合物层具有中央部分和空间上与该中央部分分离的第一框部分以定义第一沟道。
依据本发明的另一实施态样，提供一种制造方法，包括提供具有一侧面的半导体芯片和在该侧面上形成聚合物层。该聚合物层具有中央部分和空间上与该中央部分分离的第一框部分以定义第一沟道。该半导体芯片与衬底耦合，该半导体芯片的侧面面对该衬底但与该衬底分离而造成接口区域。底部填充置于该接口区域。该底部填充的一部分侵入该沟道以在该聚合物层和该底部填充之间建立机械接合。
依据本发明的另一实施态样，提供一种设备，包括具有一侧面的半导体芯片和在该侧面上的聚合物层。该聚合物层具有中央部分和空间上与该中央部分分离的第一框部分以定义第一沟道。
附图说明
根据阅读以下详细说明及根据参阅其中附加的图式，本发明的上述及其它优点将成为明显，其中：
图1是包括安装在封装衬底上的半导体芯片的半导体芯片封装的示范实施例的部分分解视图；
图2是图1的半导体芯片封装的俯视图；
图3是翻转以显示其前侧面上的裂缝阻挡聚合物层的示范半导体芯片的视图；
图4是图2在截面4-4的剖视图；
图5是绘示替代示范裂缝阻挡聚合物层的半导体芯片的替代示范实施例的俯视图；
图6是绘示另一替代示范裂缝阻挡聚合物层的半导体芯片的另一示范实施例的俯视图；
图7是图6的选定部分以更大倍率显示的俯视图；
图8是图7在截面8-8的剖视图；
图9是绘示制造聚合物裂缝阻挡层的示范步骤的如图8的剖视图；
图10是绘示制造聚合物裂缝阻挡层的额外示范步骤的如图9的剖视图；
图11是绘示制造聚合物裂缝阻挡层的额外示范步骤的如图10的剖视图；
图12是绘示制造聚合物裂缝阻挡层的额外示范步骤的如图11的剖视图；
图13是绘示制造聚合物裂缝阻挡层的额外示范步骤的如图12的剖视图；
图14是绘示底部填充至聚合物裂缝阻挡层的示范啮合的剖视图。
具体实施方式
本文描述具有裂缝阻抗聚合物层的半导体芯片的各种实施方案。一示范例包括具有一侧面上涂布有聚合物层的半导体芯片。该聚合物层具有中央部分和空间上与中央部分分离的第一框部分以定义第一沟道。在随后的底部填充过程中，底部填充材料填充到沟道以建立裂缝阻抗接口。更多细节现在加以说明。
在下述图式，出现在多个图式的相同的元件重复相同的参考数字。图1是包括安装在封装衬底20上的半导体芯片15的半导体芯片封装10的示范实施例的部分分解视图。封装10可提供具有盖体25，其从封装衬底20所分解显示。在半导体芯片15的周边可见底部填充材料层30的小部分。图2是不具有可选的盖体25的封装10的俯视图。在两个图1和2中可见半导体芯片15的背面35。
半导体芯片15可以是如图所示的安装在衬底20的覆晶芯片(flip-chip)，并通过未见于图1但将显示在随后的图的互连电连接至衬底20的导体。半导体芯片15可以是用于电子的众多不同类型的电路器件的任何一种，例如，应用专用集成电路、存储器件或类似的微处理器、图形处理器、结合微处理器/图形处理器、以及可以是单一或多核心。可以使用硅、锗或其它半导体材料制造半导体芯片15。如果需要，可将该芯片15制造为绝缘体上覆半导体的衬底或主体半导体。半导体芯片15可通过未见于图1的多个导体结构与衬底20电互连。
衬底20可由所需的陶瓷或有机材料组成。如是有机，衬底20可实际由多个金属化层和电介质材料层构成，其电气互连半导体芯片15到一些其它组件，如板(未显示)。衬底20可以各种方式(如通过引脚栅格阵列、地栅格阵列、球栅格阵列或其它配置)电互连外部设备(如另一电路板)。衬底20的个别的层的数量主要是设计裁量的问题。在某些示范实施例中，层数可能自四到十六不同。如果选这种积累的设计，可使用标准的核心、薄核心或无核心配置。电介质材料可为例如，有无玻璃纤维填充的环氧树脂。当然，衬底20可配置为封装衬底之外的东西，如作为主板的印刷电路板、子板、卡或一些其它类型的板。
底部填充材料30设计为减少芯片15和衬底20之间的在CTE的差异的效应。底部填充材料30可由已知的环氧树脂材料(如，含有或不含有二氧化硅填料和酚或类似的环氧树脂)组成。二个例子是从Namics公司可得到的8437-2和2BD型。
可选的盖体25可配置为所披露的顶盖设计，浴缸形构体设计或其它一些配置。盖体25可由所需要的塑料，陶瓷或金属材料组成。一些示范性的材料包括镀镍铜、铝阳极、铝-硅-碳，氮化铝，氮化硼或类似。盖体25可通过由所需要的已知触变性粘合剂或其它已知的封装粘合剂类型所组成的粘合剂固定在衬底20。然而如果要无盖的设计，盖体25可完全省略。
通过参阅图3，其为翻转半导体芯片15以揭示前侧面40的视图，可理解半导体芯片15的更多细节。于此图中，半导体芯片15的背面35是被遮蔽。半导体芯片15可包括主体半导体部分45、、于主体半导体层45上的主动电路层47和在主动电路层47上的互连层50。如果芯片15是实施作为绝缘上半导体的设计，则埋藏绝缘层可位在在主动电路层47之内或电路层47和底层主体半导体层45之间。主动电路层47包括许多晶体管、电容、电阻等执行各种功能的电路器件。互连层50可由多个堆迭导体和层间电介质层所组成。
薄钝化层55提供在互连层50上并可实际上由多层堆迭所组成，其以碳硅粘附层开始，有利于粘附器件层50的上部延伸。在薄钝化层55的上层可形成钝化层材料(例如，氮化硅和二氧化硅或其它类型的介质材料)的堆栈。二氧化硅和氮化硅的交替层数种类繁多。于示范实施例中，可提供各三层二氧化硅和氮化硅共6层。应该了解的是，器件层50可不仅包括形成于半导体材料内的各种主动器件，而且还包括从该各种主动器件上依序堆栈的多个互连层从。
聚合物层60形成在钝化结构55上并可由中央部分65，内框70和外框75所组成。内框70空间上与该中央部分分离以定义沟道80。外框75空间上与该内框分离以定义另一沟道85。该沟道80和85可分别形成围绕中央部分65和内框70的整个周围。可选择地，框70和75可以通过小型指形零件连接起来。在此说明的实施例，框70和75和沟道80和85一般具有矩形的覆盖区。然而，其它形状都是可能的。此外，框和沟道的数量可以依所需是一个或多个。在另一种变化例中，框70和75可分段。如果分段，该些段可偏移以至于不建立裂缝扩展途径。
多个导体结构或凸块90形成在聚合物层60的中央部分65上，并电气连接在未见于图3的互连层50的各种互连结构。所描述的是几十个导体结构90，然而，熟此技艺人员可明白，依据半导体芯片15的复杂性和大小，有可能是几十，几百甚至成千上万的这种导体结。
聚合物层60是旨在保护底层钝化结构55和在器件层50上层区域的各种电路结构。聚合物层60的示范材料包括，例如，聚酰亚胺、苯并环丁烯或类似。可将旋转涂布、化学气相沉积或其它沉积工艺用于施于聚合物层60上。已知的光刻技术可用于图案化内和外框70和75和沟道80和85。在此说明的实施例中，聚合物层60是由聚酰亚胺组成。内和外框70和75设计为裂缝阻挡以防止图1和2绘示的在填充材料层30的裂缝扩展入芯片15和导体结构90内部区域。为了帮助理解图4绘示的结构，可分开标记内框70的脚95和外框75的脚100。脚95和100在图4中可见。
图4是图2在截面4-4的剖视图。互连层50可由多层互连结构(其中之一是可见且标记为102)和层间电介质材料104(其可由多个组合层所组成)组成。半导体芯片15经由多个互连(其中两个是可见的和分别标记105和110)与衬底20电气互连。互连105和110是半导体芯片15和衬底20之间的互连的阵列的一部分，其数量可到数百甚至数千。互连105和110的阵列的形状和间距可规则或不规则。在此互连105和110的描述将对半导体芯片15其余部分说明。互连105可由冶金结合至导体结构或凸块下金属化层(UBM)120的焊料接合115所组成，，凸块下金属化层(UBM)120形成在聚合物层60的中央部分65中。焊料接合115可通过图3绘示的焊料凸块90之一的冶金联合和位在衬底20上的其它焊料结构而形成。可以使用各种焊料，如铅基或无铅焊料两例。在示范过程中，高铅焊料，如(97Pb 3Sn)可用于凸块90以及共晶锡铅焊料组合可用于接近基板20的焊料部分。接下来，UBM层120冶金连接到在半导体层105的凸块垫125。在功能方面，UBM层120设计为防止垫125的成分至焊料接合115的扩散。半导体芯片15包括此导体结构或UBM结构120的阵列以容纳多个焊料接合。在使用铜作为垫125的材料的示范实施例中，UBM 120可由通过物理气相沉积或其它已知技术沉积的铬，铜和镍的堆栈所组成。凸块垫125可包括铜、金、银、及其组合或类似物。另一侧上，焊料接合115是冶金结合凸块垫130，其连接到另一垫135。垫130和135，可包括镍、金、铜、银、钯、及其组合或类似物。互连110可具有相同的配置，然而为简洁说明，接合100的独立组件不单独标记。垫130是经由未图示的导体结构电气连接到芯片15的其它部分。在衬底20的导体结构的垫135同样。在另一种实施例，互连105和110可由铜、银、金、铝、及其组合或通过焊接在半导体芯片15和衬底20类似物的导电支柱。
半导体芯片15可提供具有内部裂缝结构阻挡区域140，其可包括从一个或多个多层次金属互连结构的集合制造的传统制造的图框式裂缝阻挡结构，该一个或多个多层次金属互连结构组合可和半导体芯片15的其它导体结构在同一时间图案化。裂缝阻挡区域140的目的是保护半导体芯片15的内部145防止从边缘150扩展到半导体芯片15的临界电路结构所位在的内部145的裂缝，。裂缝阻挡区域140可由已知的多层导体结构的集合所组成，其中两个显示和标记为160和165，各层由多个导体结构175、180、185、190、195、200、205、210、215和217组成。裂缝阻挡结构140可以结构相似凸块垫130在同一时间制造的凸块垫218覆盖。导体结构175、180、185、190、195、200、205、210、215和217可散布在可多层的电介质104，但为简洁说明而显示单一结构。导体结构175、180、185、190、195、200、205、210、215和217可以多种材料组成。一些理想特性包括抵抗与差热膨胀和裂缝扩展相关的应力的机械强度、没有不匹配半导体芯片15和衬底20的热膨胀特性和易于制造。示范材料包括铜、铝、金、银、钯、铂金、及其组合或类似物。另可能的材料为在环氧树脂基体的奈米碳管。需理解的是，可有多种裂缝阻挡结构140的层数。例如，在层中使用用于制造互连层(例如，结构102)的相同的掩膜、蚀刻和沉积物质工艺以建立裂缝阻挡区域140可以是有利的。
为了说明的目的，假设裂缝220已形成在底部填充30并横向地朝该聚合物层的外框的壁部分100进行。当裂缝220遇到外壁部分100和内壁部分95之间的沟道85时，在点225的底部填充30的存在往往会阻挡裂缝220进一步沿底部填充30和脚100之间的接口扩展。如果，例如裂缝220甚至进一步横向扩展和在底部填充30遇到点230，同样是适用的。根据沟道80和85允许底部填充30侵入和形成机械接合的事实，此将禁止裂缝横向往半导体芯片15的内部和/或互连105和110扩展。
在上述说明的实施例，内和外框70和75之间的沟道80和85一般具有矩形的覆盖区。然而，该沟道和框可采取各种配置。一替代实施例示于图5，其是半导体芯片15’的俯视图，提供有由中央部分65’，内框部分70’和外框部分75’所组成的聚合物层60。再者，自中央部分60’投影来显示焊接凸点90的阵列。内框70’经由沟道80’与中央部分65’分离且外框75’经由沟道85’与内框70’横向分离。在这里，以蜿蜒的配置制造沟道80’和85’。因为蜿蜒的配置提供更大的周围，相应地，提供机械的更大的区域以仅对抗随后沉积的底部填充和聚合物层60’之间的化学结合，蜿蜒的配置可是有利的。当然，不同的形状可结合。例如，一框或沟道可为蜿蜒和另一矩形或一些其它形状。
半导体芯片15”的另一替代的示范实施例绘示在图6，其为如图5是俯视图。此说明实施例相当类似绘示在图3中的芯片15的实施例。有鉴于此，半导体芯片15”可包括由中央部分65”，内框70”和外框75”组成的聚合物层60”，其中内框70”通过沟道80”和中央部分65’分离以及外框75”可通过沟道85”与内框70”分离。焊接凸点90的阵列自中央部分65”向上投影。再者，自中央部分65”向上投影出焊料凸块90的阵列。由虚线圆235划界线芯片15”的小部分。虚线圆235划界线的部分将在图7放大显示，以加以说明外框75”的另外特性。
现将注意力转向图7，像刚才所指出的，是通过虚线椭圆235划界线的图6的部分的放大显示。沿沟道85”的部分和芯片15”的边缘240可见外框75”。位在框75”的右侧和标记为245的半导体芯片15”的部分可由在图3和4所示和标记为55的类型的钝化堆栈所组成。外框75”可包括多个沟槽250a、250B、250C、250d、250e、和250f。沟槽250a、250B、250C、250d、250e和250f的目的是提供空间，其中，随后沉积的填充材料可侵入以及在底部填充与外框75”之间形成多个微机械接合。沟槽250a、250B、250C、250d、250e和250f的数量主要是设计裁量的问题，并可为一个或多个。虽然沟槽250a、250B、250C、250d、250e和250f和外框75”是绘示为沿轴253连续，需了解的是，沟槽250a、250B、250C、250d、250e和250f和外框75”可制造为沿轴253延伸的段的各自群组。更确切地说，对于本文所披露的这个或其它实施方案，整个外框75”可分段。如果需要，沟槽250a、250B、250C、250d、250e和250f可以延伸围绕外框75”的整个周围。相应的槽沟或槽沟集(不可见)也可以提供在内框70”。
沟槽250a、250B、250C、250d、250e和250f的更多细节可通过参阅图8而理解，图8是图7在截面8-8的剖视图。为了简化说明，绘示半导体芯片15”具有单片结构255，在其上形成钝化堆栈245。应了解，实际上单片结构255可以多层组成，例如，图3和4所示的45、47、50和55。沟槽250a、250B、250C、250d、250e和250f可由上部255A、255B、255c、255d、255E和255f和相对较宽的下部260A、260B、260C、260d、260e和260f所组成。当底部填充(未显示)侵入沟槽250a、250B、250C、250d、250e和250f并在固化过程中硬化，各自的上部255A、255B、255c、255d、255E和255f和下部260A、260B、260C、260d、260e和260f将建立没有不同的几个小榫和沟缝的机械接合。
现在伴随着图9、10、11、12和13来描述制造沟槽250a、250B、250C、250d、250e和250f的示范方法。此说明会着眼于外框75”，而也适用于在图6显示的内框70”。从图9开始，在芯片15”的主要部分255上的钝化堆栈245的形成之后，通过已知的材料沉积和光刻步骤可制造外框75”和沟道85”。在这个阶段，通过已知的化学气相沉积或其它材料沉积技术在外框75”上形成牺牲氧化层265。参阅至图10，适当的掩膜牺牲氧化层265和使其受蚀刻工艺以定义出多个部分270A、270B、270C、270d、270e和270f。此蚀刻可为干式蚀刻或湿式蚀刻工艺。在蚀刻时，可将沟道85”、主芯片部分255上的钝化堆栈245和外框75”掩膜以防止侵害。
现在参阅图11，经由覆盖先前形成的牺牲氧化物的部分270A、270B、270C、270d、270e和270f的材料沉积步骤，使外框75”高度增加。此可通过只沉积聚合物材料的额外数量来实现。一些额外聚合物材料275可实际上沉积在沟道85”和在钝化堆栈245的其它部分上。如果需要，可通过适当的掩膜和蚀刻随后移除该额外聚合物材料。参阅图12，可适当掩膜和定向蚀刻外框75”以在框75”内建立向下延伸至牺牲氧化物的部分270A、270B、270C、270d、270e和270f的上沟部分255A、255B、255c、255d、255E和255f，。此蚀刻可以用来从部分半导体芯片15”清除多余的聚合物材料，如沟道85”和钝化堆栈245的其它部分。
参阅至图13，执行湿式蚀刻工艺以去除牺牲氧化段，从而在外框75”内造成上述沟槽250a、250B、250C、250d、250e和250f。上沟槽部分255A、255B、255c、255d、255E和255f使湿蚀刻溶液能到达并蚀刻牺牲氧化物段270A、270B、270C、270d、270e和270f。应该了解，当半导体芯片15”是部分的大形半导体工件时，如晶圆或切单以后(如果需要的话)，可完成任何所披露的实施方案的的内和外框的图案化。对于本文所披露的任何实施方案是相同。
为了说明在外框75”的多数沟槽250a、250B、250C、250d、250e和250f的机械的优势，现将注意力转向图14，其绘示半导体芯片15”覆晶安装在封装衬底20和随后沉积的底部填充材料30。在底部填充30沉积之前，将半导体芯片15”移动到相对衬底20的位置以及例如，执行控制的倒塌和回流工艺以建立多个焊料接合，其中的例子是在图4的标示105。此时，可沉积底部填充材料30以及毛细管作用通过半导体芯片15”和衬底20之间的接口275来扩展底部填充。选择性地，凸块化前可使用底部填充工艺，其中底部填充材料沉积在衬底20上。底部填充30侵入沟槽250a、250B、250C、250d、250e和250f以形成与外框75”多个微机械接合，这些T形接合提供结构性接合以及底部填充30和外框75”之间的化学结合。熟此技艺人员会明白，沟槽250a、250B250C、250d、250e和250f的数量和间距可能是多种多样的，很大程度上取决于可用的工艺、最小特征尺寸和光刻技术等而定。
已经由图式中的范例显示以及已于本文中详细说明具体实施例，同时本发明容许各种修改和替代型式。然而，应了解的是，本发明不受限于所揭露的特定形式。再者，本发明是涵盖所有修改、等效物或于本发明的精神及范畴内的替换，如以下附加的权利要求所定义。

Claims (21)

1.一种制造半导体芯片(15)的方法，包括下列步骤：
提供具有钝化层(55)的该半导体芯片(15)；及
在该钝化层(55)上形成聚合物层(60)，该聚合物层(60)具有中央部分(65)和空间上与该中央部分(65)分离的第一框部分(70)以定义延伸至而不穿透该钝化层(55)的第一沟道(80)。
2.如权利要求1所述的方法，包括耦合多个焊料结构(90)至该中央部分(65)。
3.如权利要求1所述的方法，包括形成具有矩形覆盖区的该第一框部分(70)。
4.如权利要求1所述的方法，包括形成该第一框部分(70)以定义具有蜿蜒的覆盖区的该第一沟道(80’)。
5.如权利要求1所述的方法，包括在远离该半导体芯片(15”)的该钝化层(55)的该第一框部分(75”)的表面形成沟槽(250a)。
6.如权利要求5所述的方法，其中，该沟槽(250a)延伸围绕该第一框部分(75”)的周围。
7.如权利要求1所述的方法，包括形成具有空间上与该第一框部分(70)分离的第二框部分(75)的该聚合物层(60)以定义第二沟道(85)。
8.一种制造半导体芯片(15)的方法，包括：
在该半导体芯片(15)的钝化层(55)上形成聚合物层(60)，该聚合物层(60)具有中央部分(65)和空间上与该中央部分(65)分离的第一框部分(70)以定义延伸至而不穿透该钝化层(55)的第一沟道(80)；
以该钝化层(55)面对衬底(20)但与该衬底(20)分离的方式来耦合该半导体芯片(15)至该衬底(20)以留下接口区域；以及
放置底部填充(30)于该接口区域中，该底部填充的一部分侵入该沟道(80)以在该聚合物层(60)和该底部填充(30)之间建立机械接合。
9.如权利要求8所述的方法，包括在该半导体芯片(15)与该衬底(20)之间形成多个互连(105，110)。
10.如权利要求9所述的方法，其中，该互连包括焊料接合。
11.如权利要求8所述的方法，包括形成具有矩形覆盖区的该第一框部分(70)。
12.如权利要求11所述的方法，包括形成该第一框部分以定义具有矩形覆盖区的第一沟道(80)。
13.如权利要求8所述的方法，包括形成该第一框部分以定义具有蜿蜒的覆盖区的第一沟道(80’)。
14.如权利要求8所述的方法，包括在远离该半导体芯片(15”)的该钝化层(55)的该第一框部分(75”)的表面形成沟槽(250a)。
15.如权利要求14所述的方法，其中，该沟槽(250a)延伸围绕该第一框部分的周围。
16.如权利要求8所述的方法，包括形成具有空间上与该第一框部分分离的第二框部分的该聚合物层以定义第二沟道。
17.一种半导体工艺设备，包括：
具有一钝化层(55)的半导体芯片(15)；及
在该钝化层(55)上的聚合物层(60)，该聚合物层(60)具有中央部分(65)和空间上与该中央部分(65)分离的第一框部分(70)以定义延伸至而不穿透该钝化层(55)的第一沟道(80)。
18.如权利要求17所述的设备，包括多个耦合到该中央部分的焊料结构(115)。
19.如权利要求17所述的设备，其中，该第一框部分(70)包括矩形的覆盖区。
20.如权利要求19所述的设备，其中，该第一沟道(80)包括矩形的覆盖区。
21.如权利要求17所述的设备，其中，该第一沟道(80’)包括蜿蜒的覆盖区。
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