CN102280478A - 可堆栈式功率mosfet、功率mosfet堆栈及其制备工艺 - Google Patents

可堆栈式功率mosfet、功率mosfet堆栈及其制备工艺 Download PDF

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CN102280478A
CN102280478A CN2011101091470A CN201110109147A CN102280478A CN 102280478 A CN102280478 A CN 102280478A CN 2011101091470 A CN2011101091470 A CN 2011101091470A CN 201110109147 A CN201110109147 A CN 201110109147A CN 102280478 A CN102280478 A CN 102280478A
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substrate
straight
hole
conduction
drain
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CN102280478B (zh
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冯涛
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Chongqing Wanguo Semiconductor Technology Co ltd
Alpha and Omega Semiconductor Ltd
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Alpha and Omega Semiconductor Inc
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Abstract

本发明涉及一种可堆栈式功率MOSFET、功率MOSFET堆栈及其制备工艺。本发明提出了一种薄的可堆栈式功率MOSFET及其方法。该可堆栈式垂直功率MOSFET含有带有底部漏极金属层的半导体衬底。形成在半导体衬底上方的是，带沟槽的栅极区和源极本体区。带图案的栅极金属层和源极本体金属层分别接触带沟槽的栅极区和源极本体区。提供直通衬底连接通孔(TSDV)、直通衬底栅极通孔(TSGV)、直通衬底源极通孔(TSSV)中的至少一个。穿过半导体衬底形成，并与漏极金属层相接触的导电直通衬底漏极通孔，具有顶部漏极接触垫和底部漏极接触垫，以便在上面制备顶部和底部接头。与之类似，穿过半导体衬底形成，并与栅极金属层相接触的导电直通衬底栅极通孔，具有顶部栅极接触垫和底部栅极接触垫。同样地，穿过半导体衬底形成，并与源极本体金属层相接触的导电直通衬底源极通孔，具有顶部源极接触垫和底部源极接触垫。

Description

可堆栈式功率MOSFET、功率MOSFET堆栈及其制备工艺
技术领域
本发明主要涉及半导体器件结构领域。更确切地说，本发明是涉及制备功率半导体器件(例如功率金属氧化物半导体场效应管(MOSFET)和绝缘栅双极晶体管(IGBT))的可堆栈式芯片的器件结构和制备方法。
背景技术
正如市场所需求的那样，当今电子产品的主流趋势就是，带有极其丰富功能的产品的微型化。电力电子领域也具有同样的趋势。因此，在功率半导体器件领域中，仍然需要在满足降低器件的内部电阻以及高效的热耗散等功能要求的同时，做到产品微型化。
由于功率半导体器件的多个薄芯片具有在保持很小的封装引线的同时，减小体型器件电阻的优势，因此半导体行业急需制备和堆栈功率半导体器件的多个薄芯片。以下简要概述了一些制备和堆栈多芯片的原有技术。
图1摘自SunWon KANG等人发明的题为《芯片堆栈封装》美国专利公开号为20090108469的专利中的图2，该专利在下文中称为US 20090108469。如图所示，US20090108469的芯片堆栈封装500包括一个布线的衬底10、多个芯片100以及多个粘合层108，其中芯片100通过粘合层108相互堆栈并粘合在一起，利用一个晶圆级或芯片级工艺，作为布线衬底10上的中间媒介。利用直通通孔电极102，芯片100相互电耦合，直通通孔电极102穿过芯片100形成，并且直通通孔电极102电耦合到布线衬底10上。芯片100形成在一个硅晶圆上，直通通孔电极102穿过硅晶圆形成。每个外部输入/输出(I/O)端110的形状都与焊锡球类似，它们都形成在布线衬底10的底面上。每个粘合层108都是一个粘合带。
图2摘自Yuui Shimizu发明的题为《能够区分多个堆栈在同一封装中的存储器芯片的半导体存储器》美国专利申请公开号为20090135638的专利中的图1，该专利在下文中称为US 20090135638。更确切地说，图2表示依据US20090135638的第一实施例，一种多芯片封装结构存储器件(半导体存储器件)100结构的透视图。将一个电阻值变化的存储器元件用作存储器单元，把四个电阻值变化的存储器芯片(以下称为存储器芯片)111A至111D，堆栈在同一封装中。本实施例的存储器件100含有四个存储器芯片111A至111D，它们连续堆栈在一个封装衬底101中。这四个存储器芯片111A至111D都具有相同的结构(规格)，通过堆栈，使它们作为一个整体，垂直地相互重叠起来。存储器芯片111A至111D中的每一个芯片都带有多个(在本实施例中为九个)垫121至129，以及一个芯片地址标识电路150。垫121至129中的垫121和122用作第一和第二存储器的位置探测垫P1(Vtest)和P2(Vss)，以便分别识别芯片的地址。其他垫123至129分别用作输入/输出(I/0)、控制、电源(Vdd)和基态(Vss)垫。利用一个直通通孔(垂直通孔技术)103，将每个存储器芯片111A至111D的垫121至129相互连接起来。例如，示例中所示的垫121。直通通孔103连接在存储器芯片111A的垫121和存储器芯片111B的垫121之间，存储器芯片111B的垫121和存储器芯片111C的垫121之间，以及存储器芯片111C的垫121和存储器芯片111D的垫121之间。通过最低的直通通孔103，存储器芯片111A的垫121连接到封装衬底101上。下文还将详述，每个存储器芯片111A至111D的垫121至129都具有一个直通硅通孔结构(TSV)。根据这种直通硅通孔结构(TSV)，垫121至129在每个芯片的正面和背面上都有一个电极。第一和第二存储器位置探测垫121(P1)和122(P2)短接起来。依据本实施例，通过一个位于封装衬底101的表面上最低的直通通孔103之间的封装框导线分布图131，将第一和第二存储器位置探测垫121(P1)和122(P2)连接起来。更确切地说，利用八个直通通孔103以及一个导线分布图131，将存储器芯片111A至111D的第一和第二存储器位置探测垫121(P1)和122(P2)传导起来。因此，从外部测试器(图中没有表示出)开始，在最高的存储器芯片111D的第一和第二存储器位置探测垫121(P1)上，加载测试电压Vtest。存储器芯片111D的第二存储器位置探测垫122(P2)连接到基态(Vss)。通过这种方式，电流从存储器芯片111D的第一存储器位置探测垫121(P1)，流至第二存储器位置探测垫122(P2)。尽管本文没有说明，但是在除了最高的存储器芯片111D的垫121至129以外的周围区域，封装衬底101上的存储器芯片111A至111D都是利用树脂等密封器进行密封的。
除了上述内容，以下原有技术也是关于直接芯片堆栈的：
美国专利：US5818107，US6002177，US7217995，US7446420，US7494909，US7507637，US7595559，US7598617.
美国专利申请公开：US20080157357，US20090032928，US20090209063，US20090261457，US20090001543，US20090065950，US20090160051，US20090020855.
虽然上述原有技术是关于仅仅具有顶部电极的横向器件，但是并没有表示出在顶部和底部都有电极的垂直半导体晶片(尤其是功率半导体器件)是如何堆栈的。鉴于上述原有技术，本发明提出了一种可堆栈式功率MOSFET结构，用于直接堆栈功率MOSFET器件(这些器件在顶部和底部都具有电极)，以便在有限的封装引脚和尺寸中，获得较高的使用性能。
图3A和图3B分别摘自Khalil Hosseini等人发明的题为《利用带有表面可安装的外部接头的引线技术进行功率半导体零部件堆栈及其制备方法》美国专利申请公开号为20080150105的专利中的图3和图4，该专利在下文中称为US20080150105。更确切地说，图3A表示一个并联的MOSFET功率半导体零部件堆栈30的两个MOSFET功率半导体零部件2和3的示意、带开口的、透视图，该并联的MOSFET功率半导体零部件堆栈30如图3B所示。此时，在并联的MOSFET功率半导体零部件堆栈的中间平面14中，两个源极电极S一个接一个地安装在一起，两个栅极外部接头G也同样地相互校准在一起。对于并联电路而言，中间平面14中的这两个源极和两个栅极外部接头相互校准，并且通过一个焊锡层，相互电连接。从而形成如图3B所示的MOSFET功率半导体零部件堆栈30。
图3B表示一种并联的MOSFET功率半导体零部件堆栈30的示意透视图，该并联的MOSFET功率半导体零部件堆栈30在其顶部具有一个漏极外部接头D、一个源极外部接头S以及一个栅极外部接头G。在这种情况下，栅极外部接头G和源极外部接头S，通过中间平面14，向下循环到MOSFET功率半导体零部件堆栈30的下面5，同时在MOSFET功率半导体零部件堆栈30的顶部13上的漏极外部接头D，利用导电带32，以便将漏极外部接头D从MOSFET功率半导体零部件堆栈30的顶部13，引导至MOSFET功率半导体零部件堆栈30的下面5的能级上。如果除了如图3所示的中间平面14上的源极外部接头S和栅极外部接头G之外，还提供相应的漏极外部接头的话，那么在串联电路中，就可以省去导电带32。
但是US20080150105仅说明了在封装式零部件能级上堆栈MOSFET的方法。而且，并没有说明如何轻松堆栈两个以上的MOSFET零部件。
图4表示带有多个交叉指型源极本体区23a-23i以及带沟槽的栅极区24a-24j的传统MOSFET 10，带沟槽的栅极区24a-24j位于带有底部漏极金属层22的半导体衬底21顶部。在本例中，半导体衬底21可以由一个位于重掺杂的衬底层21a上方的外延层21b。多个源极本体区23a-23i相互接触，并联到带图案的源极本体金属层25c上。与之类似，尽管为了避免产生不必要的混淆，本文没有详述连接的具体细节，但是带沟槽的栅极区24a-24j是相互接触的，并联到顶部钝化物29下方的带图案的栅极金属层26h上。要注意的是，顶部源极金属25c和底部漏极金属22位于半导体器件的对边，这使得堆栈这种器件非常困难，尤其是在使用了直通通孔时。
发明内容
本发明提出了一种可堆栈式垂直功率MOSFET器件。这种可堆栈式垂直功率MOSFET具有超薄的厚度，并且包括：
一个形成在它上面的带有底部漏极金属层的半导体衬底。作为示例，半导体衬底本身可以含有一个上部轻掺杂的漂流层以及一个下部重掺杂的接触层，以便接触漏极金属层。
多个形成在半导体衬底上方的交叉指型的带有沟槽的栅极区和源极本体区。
一个带图案的栅极金属层和一个带图案的源极本体金属层，它们分别接触带沟槽的栅极区和源极本体区。
下列项目中的至少一个：
a.一个导电直通衬底漏极通孔(TSDV)，穿过半导体衬底，并与漏极金属层接触。该导电直通衬底漏极通孔具有一个顶部漏极接触垫和一个底部漏极接触垫，分别在顶面和底面电接触到导电直通衬底漏极通孔上。相应地，每个位于导电直通衬底漏极通孔附近的源极本体区，都带有一个距离导电直通衬底漏极通孔足够远的源极本体切断剖面，以承载它们之间的漏极源极电压。
b.一个导电直通衬底栅极通孔(TSGV)，穿过半导体衬底，并与栅极金属层接触。该导电直通衬底栅极通孔具有一个顶部栅极接触垫和一个底部栅极接触垫，分别在顶面和底面电接触到导电直通衬底栅极通孔上。
c.一个导电直通衬底源极通孔(TSSV)，穿过半导体衬底，并与源极本体金属层接触。该导电直通衬底源极通孔具有一个顶部源极接触垫和一个底部源极接触垫，分别在顶面和底面电接触到导电直通衬底源极通孔上。
一旦多个可堆栈式垂直功率MOSFET器件一个压一个地向上堆栈并粘合起来，所形成的可堆栈式垂直功率MOSFET堆栈就会起堆栈式MOSFET器件的并联导电连接的作用，从而降低了导通电阻Rds、增大了载流能力、减少了封装引脚并缩小了封装高度。此外，可堆栈式垂直功率MOSFET堆栈也可以与各种封装零部件一同封装，以便将堆栈与其外部的作业环境互联起来。
在一个较详细的实施例中，导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔在它们各自的可堆栈式垂直功率MOSFET单元的主器件平面内，都设置在恰当的位置，因此，一旦将它们堆栈起来：
可堆栈式垂直功率MOSFET单元的顶部漏极接触垫和底部漏极接触垫就会分别与它们相邻的可堆栈式垂直功率MOSFET单元的底部漏极接触垫和顶部漏极接触垫对齐。
可堆栈式垂直功率MOSFET单元的顶部栅极接触垫和底部栅极接触垫就会分别与它们相邻的可堆栈式垂直功率MOSFET单元的底部栅极接触垫和顶部栅极接触垫对齐。
可堆栈式垂直功率MOSFET单元的顶部源极接触垫和底部源极接触垫就会分别与它们相邻的可堆栈式垂直功率MOSFET单元的底部源极接触垫和顶部源极接触垫对齐。
在一个较典型的实施例中，可堆栈式垂直功率MOSFET器件厚度约为5微米至100微米。
在一个较典型的实施例中，每个导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔都用铜或一种金属填充，并且都有一个通孔绝缘层包围着，从而使它与半导体衬底绝缘。该通孔绝缘层可以由一种半导体氧化物、氮化物或一种聚合物材料制成。还可选择，每个导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔都以铜或一种金属制成的空心壳体的形式制备。
本发明还提出了一种封装的多单元可堆栈式垂直功率MOSFET堆栈的制备方法，该封装的多单元可堆栈式垂直功率MOSFET堆栈具有多个可堆栈式垂直功率MOSFET单元一个压一个地向上粘合，并且相互并联。该方法包括：
制备多个可堆栈式垂直功率MOSFET单元。
可堆栈式垂直功率MOSFET单元一个压一个地向上堆栈并粘合，以构成带有由导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔实现的并联连接的多单元可堆栈式垂直功率MOSFET堆栈。
将该堆栈与其外部作业环境互联。
在一个较典型的实施例中，其中每个可堆栈式垂直功率MOSFET单元都具有超薄的厚度，以便减小多单元可堆栈式垂直功率MOSFET堆栈的相应的厚度以及导通电阻Rds，制备每个可堆栈式垂直功率MOSFET单元包括：
一个原始厚度的衬底晶圆上，制备可堆栈式垂直功率MOSFET单元的顶部，
在衬底晶圆上方连接一个临时的晶圆承载器件。
将衬底晶圆的底部减薄至所需的超薄厚度，平行制备以下项目：
a.导电直通衬底漏极通孔加上其底部漏极接触垫、导电直通衬底栅极通孔加上其底部栅极接触垫、导电直通衬底源极通孔加上其底部源极接触垫。
除去临时的晶圆承载器件。
在上述内容中，制备可堆栈式垂直功率MOSFET的顶部部分包括，在需要导电直通衬底漏极通孔的位置处将源极本体金属层分段，并在上面制备顶部漏极接触垫。而且，制备导电直通衬底漏极通孔加上其底部漏极接触垫包括：
制备底部漏极金属层，并在需要导电直通衬底漏极通孔的位置处打开它。
一起制备导电直通衬底漏极通孔及其底部漏极接触垫，使导电直通衬底漏极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部漏极接触垫以及底部漏极接触垫接触。
在一个较详细的实施例中，并行制备导电直通衬底漏极通孔加上其底部漏极接触垫、导电直通衬底栅极通孔加上其底部栅极接触垫、导电直通衬底源极通孔加上其底部源极接触垫包括：
制备底部漏极金属层，并在需要导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔的不同位置处打开它。
同时制备以下项目：
a.一起制备导电直通衬底漏极通孔及其底部漏极接触垫，使导电直通衬底漏极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部漏极接触垫以及底部漏极接触垫接触。
b.一起制备导电直通衬底栅极通孔及其底部栅极接触垫，使导电直通衬底栅极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部栅极接触垫以及底部栅极接触垫接触。
c.一起制备导电直通衬底源极通孔及其底部源极接触垫，使导电直通衬底源极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部源极接触垫以及底部源极接触垫接触。
在一个较详细的实施例中，一起制备导电直通衬底漏极通孔加上其底部漏极接触垫包括：
在漏极金属层上沉积漏极金属钝化物，并形成图案，同时包围着需要导电直通衬底漏极通孔的位置。
带开口的漏极金属层和带图案的漏极金属钝化物作为掩膜，穿过半导体衬底定向刻蚀，以制成一个直通衬底隧道，触及分段的源极本体金属层，但受到分段的源极本体金属层的限制。
在直通衬底隧道内部，制备导电直通衬底漏极通孔，以及在漏极金属层和漏极金属钝化物上制备底部漏极接触垫。这还需要：
a.在半导体衬底的底部上方和直通衬底隧道的裸露表面，沉积一个通孔绝缘层。
b.定向刻蚀掉通孔绝缘层的所有的水平导向层，以便裸露出分段的源极本体金属层和漏极金属层。
c.用导电通孔材料，过填充直通衬底隧道和带图案的漏极金属钝化物。
d.将导电通孔材料的底部形成图案，以制成底部漏极接触垫。
在上述内容中，制备可堆栈式垂直功率MOSFET顶部部分包括，在栅极金属层上方制备顶部栅极接触垫。而且，制备导电直通衬底栅极通孔加上其底部栅极接触垫包括：
制备底部漏极金属层，并在需要导电直通衬底栅极通孔的位置处打开它。
一起制备导电直通衬底栅极通孔及其底部栅极接触垫，使导电直通衬底栅极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部栅极接触垫以及底部栅极接触垫接触。
在一个较详细的实施例中，一起制备导电直通衬底栅极通孔加上其底部栅极接触垫包括：
在漏极金属层上沉积漏极金属钝化物，并形成图案，同时包围着需要导电直通衬底栅极通孔的位置。
以带开口的漏极金属层和带图案的漏极金属钝化物作为掩膜，穿过半导体衬底定向刻蚀，以制成一个直通衬底隧道，触及栅极金属层，但受到栅极金属层的限制。
在直通衬底隧道内部制备导电直通衬底栅极通孔，以及在漏极金属层和漏极金属钝化物上制备底部栅极接触垫，。这还需要：
a.在半导体衬底的底部上方和直通衬底隧道的裸露表面，沉积一个通孔绝缘层。
b.直接刻蚀掉通孔绝缘层的所有的水平导向层，以便裸露出栅极金属层。
c.用导电通孔材料，过填充直通衬底隧道和带图案的漏极金属钝化物。
d.将导电通孔材料的底部形成图案，以制成底部栅极接触垫。
在上述内容中，制备可堆栈式垂直功率MOSFET顶部部分包括，在需要导电直通衬底源极通孔的位置处的源极本体金属层上方，制备顶部源极接触垫。而且，制备导电直通衬底源极通孔加上其底部源极接触垫包括：
制备底部漏极金属层，并在需要导电直通衬底源极通孔的位置处打开它。
一起制备导电直通衬底源极通孔及其底部源极接触垫，使导电直通衬底源极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部源极接触垫以及底部源极接触垫接触。
在一个较详细的实施例中，一起制备导电直通衬底源极通孔加上其底部源极接触垫包括：
在漏极金属层上沉积漏极金属钝化物，并形成图案，同时包围着需要导电直通衬底源极通孔的位置。
以带开口的漏极金属层和带图案的漏极金属钝化物作为掩膜，穿过半导体衬底定向刻蚀，以制成一个直通衬底隧道，触及源极本体金属层，但受到源极本体金属层的限制。
在直通衬底隧道内部，以及在漏极金属层和漏极金属钝化物上的底部源极接触垫中，制备导电直通衬底源极通孔。这还需要：
a.在半导体衬底的底部上方和直通衬底隧道的裸露表面，沉积一个通孔绝缘层。
b.直接刻蚀掉通孔绝缘层的所有的水平导向层，以便裸露出源极本体金属层。
c.用导电通孔材料，过填充直通衬底隧道和带图案的漏极金属钝化物。
d.将导电通孔材料的底部形成图案，以制成底部源极接触垫。
对于底部可堆栈式可堆栈式垂直功率MOSFET单元的特殊情况，减薄衬底晶圆的底部并制备导电直通衬底漏极通孔加上其底部漏极接触垫包括：
在需要导电直通衬底漏极通孔的位置处，打开源极本体金属层。
一起制备部分直通衬底漏极通孔(PTSDV及其顶部漏极接触垫，使得：
a.部分导电直通衬底漏极通孔与半导体衬底绝缘。
b.部分导电直通衬底漏极通孔的一部分进入衬底晶圆中，但部分导电直通衬底漏极通孔的底部将缩短至稍后衬底晶圆的减薄处。
将衬底晶圆的底部减薄至所需的超薄厚度，同时裸露出缩短的部分导电直通衬底漏极通孔底部，从而制成导电直通衬底漏极通孔。
在衬底晶圆上方制备底部漏极金属层。
对于本领域的技术人员，阅读本说明的以下内容后，本发明的这些方面及其多个实施例将显而易见。
附图说明
为了更加完整地说明本发明的各种实施例，可参照附图。但是，这些附图仅用作解释说明，并不作为本发明范围的局限。
图1摘自原有技术US 20090108469。
图2摘自原有技术US20090135638。
图3A和图3B摘自原有技术US20080150105。
图4表示一种传统的多沟槽功率MOSFET。
图5表示本发明所述的带有导电直通衬底源极通孔、导电直通衬底栅极通孔以及导电直通衬底漏极通孔的第一实施例可堆栈式垂直功率MOSFET。
图6A表示本发明所述的带有导电直通衬底源极通孔以及导电直通衬底栅极通孔的第二实施例可堆栈式垂直功率MOSFET。
图6B表示本发明所述的带有导电直通衬底漏极通孔的第三实施例可堆栈式垂直功率MOSFET。
图6C表示除了直通衬底通孔的内部结构的变化之外，其他都与图6A的第二实施例类似的本发明所述的第四实施例可堆栈式垂直功率MOSFET。
图6D表示本发明的第五实施例，即两个可堆栈式垂直功率MOSFET单元的堆栈。
图7A表示对应图6D所示的两重可堆栈式垂直功率MOSFET堆栈的等效电路图。
图7B表示对应由本发明所述的四个可堆栈式垂直功率MOSFET单元制成的四重可堆栈式垂直功率MOSFET堆栈的等效电路图。
图8表示本发明的第六实施例，即三个可堆栈式垂直功率MOSFET单元的堆栈。
图9A至图9F表示本发明所述的广义三重可堆栈式垂直功率MOSFET堆栈的独立可堆栈式垂直功率MOSFET单元的顶部和底部示意图，该结构带有大量分别并联的直通衬底源极通孔和直通衬底漏极通孔。
图10A表示本发明所述的四重可堆栈式垂直功率MOSFET堆栈的部分源极接触垫、栅极接触垫、漏极接触垫、直通衬底源极通孔、直通衬底栅极通孔以及直通漏极通孔的三维透视图。
图10B表示本发明所述的四重可堆栈式垂直功率MOSFET堆栈的部分源极接触垫、栅极接触垫、直通衬底源极通孔以及直通衬底栅极通孔的三维透视图。
图10C表示本发明所述的四重可堆栈式垂直功率MOSFET堆栈的部分漏极接触垫以及直通漏极通孔的三维透视图。
图10D表示同引线框和连接板一起封装的四重可堆栈式垂直功率MOSFET堆栈的剖面图。
图11A至图11M表示制备图8所示的三重可堆栈式垂直功率MOSFET堆栈的中间的可堆栈式垂直功率MOSFET单元的详细工艺流程。
图12A至图12G表示制备图8所示的三重可堆栈式垂直功率MOSFET堆栈的底部的可堆栈式垂直功率MOSFET单元的详细工艺流程。
具体实施方式
本文所含的上述及以下说明和附图仅用于说明本发明的一个或多个现有的较佳实施例，以及一些典型的可选件和/或可选实施例。说明及附图用于解释说明，就其本身而言，并不局限本发明。因此，本领域的技术人员将轻松掌握各种改动、变化和修正。这些改动、变化和修正也应认为属于本发明的范围。
图5表示本发明所述的可堆栈式功率沟槽MOSFET20的第一实施例。除了与传统的功率沟槽MOSFET 10(与图4和图5相比较)的那些零部件相同之外，本发明所述的可堆栈式垂直功率MOSFET 20的显著特点是，具有导电直通衬底源极通孔(TSSV)26、导电直通衬底栅极通孔(TSGV)27以及导电直通衬底漏极通孔(TSDV)28。传统的功率沟槽MOSFET 10的典型厚度约为200微米，与之相反，本发明所述的可堆栈式垂直功率MOSFET 20具有超薄的厚度TSVP，例如，其范围约为5微米至100微米。更确切地说，与传统的功率沟槽MOSFET 10相同的零部件包括以下内容：
a.半导体衬底21，底部漏极金属层22形成在上面。作为一个更加详细的示例，半导体衬底21可以由一个上部轻掺杂的漂流层21b和一个下部重掺杂的接触层21a制成，以便接触底部漏极金属层22并支撑半导体器件。
b.多个相互间隔的沟槽栅极区24a-24g和栅极滑道24j，以及形成在半导体衬底21上方的源极本体区23a-23g。
c.一个带图案的栅极金属层26h，接触沟槽栅极区24a-24g和栅极滑道24j，以及带图案的源极本体金属层25a、25c，接触源极本体区23a-23g。源极本体金属层25a和25c在第三维度上相互连接。
然而，与本发明所述的可堆栈式垂直功率MOSFET 20不同的零部件包括以下内容：
a.穿过半导体衬底21并与底部漏极金属层22相接触的导电直通衬底漏极通孔(TSDV)28。该导电直通衬底漏极通孔28具有一个顶部漏极接触垫28a以及一个底部漏极接触垫28b，分别用于将顶面和底面电接触到导电直通衬底漏极通孔28上。要注意的是，顶面电接触到导电直通衬底漏极通孔28上，是通过一个分段的源极本体金属35，分段的源极本体金属35与带图案的源极本体金属层25a和25c分开。为了清楚说明导电直通衬底漏极通孔28，位于导电直通衬底漏极通孔28附近的源极本体区23b和23c都带有源极本体切断结构36，这些结构距离导电直通衬底漏极通孔28足够远，以便当本发明所述的可堆栈式垂直功率MOSFET 20工作时，承载它们之间的漏源电压。
b.穿过半导体衬底21并与带图案的栅极金属层26h相接触的导电直通衬底栅极通孔(TSGV)27。该导电直通衬底栅极通孔27具有一个顶部栅极接触垫27a以及一个底部栅极接触垫27b，分别用于将顶面和底面电接触到导电直通衬底栅极通孔27上。
c.穿过半导体衬底21并与带图案的源极本体金属层25c相接触的导电直通衬底源极通孔(TSSV)26。该导电直通衬底源极通孔26具有一个顶部源极接触垫26a以及一个底部源极接触垫26b，分别用于将顶面和底面电接触到导电直通衬底源极通孔26上。
d.每个顶部漏极接触垫28a、顶部栅极接触垫27a、顶部源极接触垫26a的周围，都通过顶部钝化物29，与下面的器件结构分开。而且，除了在底部漏极接触垫28b和底部漏极金属层22之间直接接触之外，每个底部栅极接触垫27b、底部源极接触垫26b都通过漏极金属钝化物30，与底部漏极金属层22分开。
作为一个较典型的实施例，每个导电直通衬底漏极通孔28、导电直通衬底栅极通孔27和导电直通衬底源极通孔26都用钨或铜、或一般金属填充。导电直通衬底漏极通孔28具有一个漏极通孔绝缘层33包围着它，使它与半导体衬底21绝缘。与之类似，导电直通衬底栅极通孔27具有一个栅极通孔绝缘层32包围着它，使它与半导体衬底21绝缘，导电直通衬底源极通孔26具有一个源极通孔绝缘层31包围着它，使它与半导体衬底21绝缘。通孔绝缘层33、32、31可以由半导体氧化物、氮化物或聚合材料制成。
图6A表示本发明所述的带有导电直通衬底源极通孔26和导电直通衬底栅极通孔27的第二实施例可堆栈式垂直功率MOSFET 2302。该导电直通衬底源极通孔26具有一个顶部源极接触垫26a以及一个底部源极接触垫26b，分别用于将顶面和底面电接触到导电直通衬底源极通孔26上。该导电直通衬底栅极通孔27具有一个顶部栅极接触垫27a以及一个底部栅极接触垫27b，分别用于将顶面和底面电接触到导电直通衬底栅极通孔27上。为了将底面仅仅电接触到底部漏极金属层22上，该可堆栈式垂直功率MOSFET 2302具有一个不带有导电直通衬底漏极通孔的底部漏极接触垫28b。在堆栈式器件中，可堆栈式垂直功率MOSFET 2302可以位于堆栈的顶部。
图6B表示本发明所述的仅仅带有与底部漏极金属层22直接接触的导电直通衬底漏极通孔28，不带有底部漏极接触垫的第三实施例可堆栈式垂直功率MOSFET 1301。该导电直通衬底漏极通孔28具有一个顶部漏极接触垫28a，用于将顶面电接触到导电直通衬底漏极通孔28上。为了将顶面电接触到带图案的源极本体金属层25c上，该可堆栈式垂直功率MOSFET 1301具有一个不带有导电直通衬底源极通孔的顶部源极接触垫26a。为了将顶面仅仅电接触到带图案的栅极金属层26h上，该可堆栈式垂直功率MOSFET 1301具有一个不带有导电直通衬底栅极通孔的顶部栅极接触垫27a。在堆栈式器件中，可堆栈式垂直功率MOSFET 1301可以位于堆栈的底部。
图6C表示本发明所述的可堆栈式垂直功率MOSFET 2302a的第四实施例，其中直通衬底通孔的内部结构发生了变化，不再是实心导电内核，取而代之的是导电直通衬底栅极通孔27具有一个空壳导电内核40加上栅极通孔绝缘层32，导电直通衬底源极通孔26具有一个空壳导电内核38加上源极通孔绝缘层31，除此之外都与图6A所示的可堆栈式垂直功率MOSFET 2302的第二实施例相类似。空壳导电内核40与空壳导电内核38可以由钨、铜或其他金属制成。因此，空壳导电内核40是一个导电层，穿过栅极通孔绝缘层32，遍布在导电直通衬底栅极通孔27的侧壁上。虽然空壳导电内核所具有的电阻高于同种材料制成的实心导电内核的电阻，但是只要空壳导电内核电阻仍远低于可堆栈式垂直功率MOSFET 2302a的器件内部电阻，就仍然可以维持较低的直通衬底电阻。在这种情况下，空壳导电内核的优势在于，减少材料消耗，降低内在的材料应力，在某些情况下，比其他实心导电内核更加易于制备。
图6D表示两重可堆栈式垂直功率MOSFET堆栈300的第五实施例，这两个堆栈是图6B所示的两个可堆栈式垂直功率MOSFET单元可堆栈式垂直功率MOSFET 1301以及图6A所示的可堆栈式垂直功率MOSFET 2302。此时，导电直通衬底漏极通孔28、导电直通衬底栅极通孔27以及导电直通衬底源极通孔26在它们各自可堆栈式垂直功率MOSFET单元的主器件平面(XY平面)内适当地设置，从而在它们的堆栈上：
a.可堆栈式垂直功率MOSFET 1301的顶部漏极接触垫28a与可堆栈式垂直功率MOSFET 2302的底部漏极接触垫28b排成直线。
b.可堆栈式垂直功率MOSFET 1301的顶部源极接触垫26a与可堆栈式垂直功率MOSFET 2302的底部源极接触垫26b排成直线。
c.可堆栈式垂直功率MOSFET 1301的顶部栅极接触垫27a与可堆栈式垂直功率MOSFET 2302的底部栅极接触垫27b排成直线。
图7A表示两个并联MOSFET等效电路图352，对应图6D所示的两重可堆栈式垂直功率MOSFET堆栈300。要注意的是，尽管这两个可堆栈式垂直功率MOSFET单元FET 1和FET 2(图6D中的可堆栈式垂直功率MOSFET1301和可堆栈式垂直功率MOSFET 2302)是并联的，但是所有物理互联的元件都表现出在FET 1和FET 2之间的寄生互联电阻的有限量。例如，寄生漏极互联电阻Rdv来自于可堆栈式垂直功率MOSFET 1301的导电直通衬底漏极通孔28。又例如，寄生栅极互联电阻Rgv来自于可堆栈式垂直功率MOSFET 2302的导电直通衬底栅极通孔27。再例如，寄生源极互联电阻Rsv来自于可堆栈式垂直功率MOSFET 2302的导电直通衬底源极通孔26。图7B表示四个并联MOSFET等效电路图354，对应由本发明所述的四个可堆栈式垂直功率MOSFET单元(FET 1、FET 2、FET 3、FET 4)制成的四重可堆栈式垂直功率MOSFET堆栈。由于独立的可堆栈式垂直功率MOSFET的各个直通衬底通孔的寄生互联电阻都对总电阻有贡献，因此相应的互联电阻就会随堆栈可堆栈式垂直功率MOSFET单元数量的增加而增大。
因此，本发明提出的另一个重要思想是，制备多重并联的直通衬底通孔，以降低互联电阻，这在下文将作详细介绍。另外，也可以通过用金属等高导电率材料制备直通通孔，来降低通孔电阻(例如Rsv)。在这些电路中，当路由信号从栅极垫到栅极沟槽电极传输时，所有的MOSFET中都有内部栅极电阻Rg。
图8表示三重可堆栈式垂直功率MOSFET堆栈400的第六实施例，即三个可堆栈式垂直功率MOSFET单元可堆栈式垂直功率MOSFET 1401、可堆栈式垂直功率MOSFET 2402以及可堆栈式垂直功率MOSFET 3403的堆栈。可堆栈式垂直功率MOSFET 1401对应图6B所示的可堆栈式垂直功率MOSFET 301，可堆栈式垂直功率MOSFET 3402对应图5所示的可堆栈式垂直功率MOSFET 20，可堆栈式垂直功率MOSFET 3403对应图6A所示的可堆栈式垂直功率MOSFET 302。此时，导电直通衬底漏极通孔28、导电直通衬底栅极通孔27以及导电直通衬底源极通孔26在它们各自可堆栈式垂直功率MOSFET单元的主器件平面(XY平面)内适当地设置，从而在它们的堆栈上：
a.可堆栈式垂直功率MOSFET 1401的顶部漏极接触垫28a与可堆栈式垂直功率MOSFET 2402的底部漏极接触垫28b排成直线；可堆栈式垂直功率MOSFET 2402的顶部漏极接触垫28a与可堆栈式垂直功率MOSFET 3403的底部漏极接触垫28b排成直线。
b.可堆栈式垂直功率MOSFET 1401的顶部源极接触垫26a与可堆栈式垂直功率MOSFET 2402的底部源极接触垫26b排成直线；可堆栈式垂直功率MOSFET 2402的顶部源极接触垫26a与可堆栈式垂直功率MOSFET 3403的底部源极接触垫26b排成直线。
c.可堆栈式垂直功率MOSFET 1401的顶部栅极接触垫27a与可堆栈式垂直功率MOSFET 2402的底部栅极接触垫27b排成直线；可堆栈式垂直功率MOSFET 2402的顶部栅极接触垫27a与可堆栈式垂直功率MOSFET 3403的底部栅极接触垫27b排成直线。
然而，可堆栈式垂直功率MOSFET 3403的导电直通衬底源极通孔(导电直通衬底源极通孔)46的顶部源极接触垫26a，用于外部源极接触到三重可堆栈式垂直功率MOSFET堆栈400上。同样地，可堆栈式垂直功率MOSFET3403的导电直通衬底栅极通孔(导电直通衬底栅极通孔)47的顶部源极接触垫27a，用于外部源极接触到三重可堆栈式垂直功率MOSFET堆栈400上。
至此，本领域的技术人员应明确，只要各种顶部和底部接触垫(26a、26b、27a、27b、28a、28b)用于可堆栈式垂直功率MOSFET堆栈的作用相同，例如突起和多个球形接头，那么就可以其他形式实现它们。这些接触垫可以由铜、金属和/或用于铜铜直接接合或焊锡焊锡接合的焊锡材料制成。然而，对于底部可堆栈式垂直功率MOSFET 1401而言，在导电直通衬底漏极通孔(导电直通衬底漏极通孔)48底部的底部漏极金属层22，已经用作外部接头。
如上所述，本发明的一个重要方面在于，制备多个并联的直通衬底通孔，以降低总互联电阻，如图9A至图9F所示，类似于图8所示的堆栈400的一种一般的三重可堆栈式垂直功率MOSFET堆栈。图9A和图9B分别表示其顶部可堆栈式垂直功率MOSFET单元的顶面和底面示意图。图9C和图9D分别表示其中部可堆栈式垂直功率MOSFET单元的顶面和底面示意图。图9E和图9F分别表示其底部可堆栈式垂直功率MOSFET单元的顶面和底面示意图。因此，图9A表示顶部栅极接触垫27a和顶部源极接触垫26a。图9B、图9C、图9D和图9E表示在平行于XY平面的顶部和底部视图中，一个导电直通衬底栅极通孔27、23个导电直通衬底漏极通孔28以及24个导电直通衬底源极通孔26相互间隔的阵列，图9F表示底部可堆栈式垂直功率MOSFET单元的底部漏极金属层22。这23个导电直通衬底漏极通孔28通过每个可堆栈式垂直功率MOSFET单元的底部漏极金属层22并联，同时，这24个导电直通衬底源极通孔26通过每个可堆栈式垂直功率MOSFET单元的顶部源极接触垫26a以及顶部源极金属(图中没有表示出)并联。虽然，这种并联体系也可适用于直通衬底栅极通孔，但是在本例中却并没有采用，这是由于MOSFET器件的栅极电流明显远低于漏极和源极电极的电流，因此一个单独的栅极通孔就已足够了。源极和漏极通孔相互间隔，使得直通衬底连接无需将源极短接至漏极，就可以降低横向导通电阻。实际上，将多个本发明所述的具有一个挨一个地相互间隔的直通通孔的超薄可堆栈式垂直功率MOSFET器件堆栈并接合起来，所形成的可堆栈式垂直功率MOSFET堆栈作为堆栈式可堆栈式垂直功率MOSFET器件的并联连接，可相应地减少导通电阻Rds，降低电流承载能力，减少封装引脚，并且封装高度与以前相同。源极和漏极直通通孔在整个晶片上相互间隔，使得直通衬底连接无需将源极短接至漏极，就能降低横向导通电阻。
图10A至图10C表示对于由可堆栈式垂直功率MOSFET 1601、可堆栈式垂直功率MOSFET 2602、可堆栈式垂直功率MOSFET 3603以及可堆栈式垂直功率MOSFET 4604(每个都带有各自的顶部源极接触垫26a和底部漏极接触垫28b)制成的一种一般的四重可堆栈式垂直功率MOSFET堆栈600，利用多个并联的直通衬底通孔另一示例的三维透视图，以便降低总互联电阻以及传导电阻。栅极连接是通过四个顶部栅极接触垫27a制成的，顶部栅极接触垫27a连接有一个单独的导电直通衬底栅极通孔(TSGV)47。为了表示清晰，图10A仅仅表示四重可堆栈式垂直功率MOSFET堆栈600的部分源极接触垫、栅极接触垫、漏极接触垫、直通衬底源极通孔、直通衬底栅极通孔以及直通衬底漏极通孔。因此，并联的导电直通衬底漏极通孔是48，并联的导电直通衬底源极通孔是46。同样地，为了表示清晰，图10B仅仅表示四重可堆栈式垂直功率MOSFET堆栈600的部分源极接触垫、栅极接触垫、直通衬底源极通孔、直通衬底栅极通孔。同样地，为了表示清晰，图10C仅仅表示四重可堆栈式垂直功率MOSFET堆栈600的部分漏极接触垫和直通衬底通孔。要注意的是，导电直通衬底源极通孔46可以无需接触，就能穿过漏极接触垫28b，同样地，导电直通衬底漏极通孔48也可以无需接触，就能穿过源极接触垫26a。因此，可以形成相互间隔的源极和漏极通孔，以便分别并联堆栈式MOSFET的源极和漏极，并且无需将源极短接至漏极，就能降低传导电阻。
图10D表示封装的多单元功率MOSFET堆栈500的剖面图，其中封装图10A所示的四重可堆栈式垂直功率MOSFET堆栈600，用作带有引线框502和接合板506(如美国申请11/906,136所述)的外部运行环境。然而，四重可堆栈式垂直功率MOSFET堆栈600可以通过引线框502上方的晶片接合材料504(例如焊锡或导电环氧树脂)接合起来，引线框502可以用印刷电路板(PCB)或普通的多层电路层压板等其他类型的电路衬底代替。同样地，接合板506可以用接合线等其他封装元件代替。另外地，尽管在此没有详述，封装的多单元功率MOSFET堆栈500也可以用成型混料密封。如上所述，传统的MOSFET 10的典型厚度约为200微米，与之相反，本发明所述的每个可堆栈式垂直功率MOSFET单元(可堆栈式垂直功率MOSFET 1601、可堆栈式垂直功率MOSFET 2602、可堆栈式垂直功率MOSFET 3603、可堆栈式垂直功率MOSFET 4604)的超薄厚度TSVP约为5微米至100微米。因此，封装的多单元功率MOSFET堆栈500的优点在于，与之前相同封装高度下的小封装引脚，极其低的Rdson。另一优势在于，多个并联的导电直通衬底漏极通孔48和导电直通衬底源极通孔46用于将横向电流(平行于XY平面)局限在每个MOSFET的源极金属和漏极金属内。这将降低相关的传导电阻。
图11A至图11M表示制备图8所示的三重可堆栈式垂直功率MOSFET堆栈400的中间可堆栈式垂直功率MOSFET单元可堆栈式垂直功率MOSFET2402(也可参见图5所示的可堆栈式垂直功率MOSFET单元20)的详细工艺流程。由该工艺可知，从图11A至图11E表示在一个原始厚度的衬底晶圆上，制备可堆栈式垂直功率MOSFET 2402的顶部，无需以下内容：
导电直通衬底漏极通孔加上其底部漏极接触垫、导电直通衬底栅极通孔加上其底部栅极接触垫、导电直通衬底源极通孔加上其底部源极接触垫。
然后，图11F至图11M表示将衬底晶圆的底部减薄至所需的超薄厚度，并制备以下内容：
导电直通衬底漏极通孔加上其底部漏极接触垫、导电直通衬底栅极通孔加上其底部栅极接触垫、导电直通衬底源极通孔加上其底部源极接触垫。
在图11A中，被钝化层34覆盖的多个相互间隔的源极本体区23a-23g以及带沟槽的栅极区24a-24h，都制备在半导体衬底21上方，半导体衬底21的原始厚度为TORG。作为一个典型示例，半导体衬底21具有一个下部重掺杂的接触层21a以及一个上部轻掺杂的漂流层21b。例如，钝化层34的材料为含有硼酸的硅玻璃(BPSG)。要注意的是，源极本体区23b、23c都带有源极本体切断结构36，以便清除稍后在它们之间形成的导电直通衬底漏极通孔。源极本体区23f、23g不带有栅极沟槽或在中间的源极区，以便为稍后形成的导电直通衬底源极通孔留有空隙。
在图11B中，将钝化层34形成栅极钝化物分段的图案，对应源极本体区23a-23g以及带沟槽的栅极区24a-24h，然后进行源极本体接触刻蚀以及本体接触植入。
在图11C中，沉积顶部金属，然后形成图案，以制备带图案的栅极金属层26h、带图案的源极本体金属层25a以及带图案的源极本体金属层25c，并带有之间的分段顶部漏极金属35，位于稍后的导电直通衬底漏极通孔的位置处。对于本领域的技术人员而言，源极本体金属层25a和25c在第三维度上相互连接。
在图11D中，沉积顶部钝化层，并形成图案，以制备带图案的顶部钝化元件29a、29b、29c、29d，邻近带图案的源极本体金属层25c、分段的源极本体金属35以及带图案的栅极金属层26h。顶部钝化元件29a-29d可以用氧化物、氮化物或两者的组合制成。
在图11E中，顶部漏极接触垫28a、顶部源极接触垫26a以及顶部栅极接触垫27a都同时形成在上方，使顶部漏极接触垫28a接触分段的顶部漏极金属35，顶部源极接触垫26a接触带图案的源极本体金属层25c，并且顶部栅极接触垫27a接触带图案的栅极金属层26h。这可以通过以下方式完成，例如溅射种子层，在种子层上方电镀铜，然后对镀铜形成图案。还可选择，使用无电、无掩膜的镍金电镀工艺。此后，可以利用可选的化学机械抛光(CMP)和/或退火工艺，使顶面平坦光滑，以消除内部材料应力。
在图11F中，还可选择在制备中的器件上方连接一个临时的支撑器件(图中没有表示出)，并将半导体衬底21从原始厚度TORG减薄至所需的超薄厚度TSVP，例如5微米至100微米。在制备中的半导体器件上连接一个临时的支撑器件，有利于向下减薄其背面，这在本领域中是众所周知的。作为示例，也可以在制备中的器件顶部，连接一个玻璃板或硅晶圆。
在图11G中，在制备中的器件上沉积一个底部漏极金属层22，然后形成在之间带有开口的漏极金属元件22a-22d的图案，以容纳稍后形成的各种导电直通衬底漏极通孔、导电直通衬底源极通孔和导电直通衬底栅极通孔。作为一个典型示例，沉积底部漏极金属层22，可以通过背部刻蚀，以及用界面钛或铝进行背面金属沉积。
在图11H中，在制备中的器件上沉积一个底部漏极金属钝化物30(例如一种氧化物)，然后形成漏极金属钝化物元件30a-30d的图案。
在图11I中，通过直接刻蚀穿过半导体衬底21，制成直通衬底隧道128、126、127，带图案的漏极金属元件22和漏极金属钝化元件30作为硬掩膜。要注意，直通衬底隧道128触及分段顶部漏极金属35和钝化层34，但是受分段顶部漏极金属35和钝化层34的限制。与之类似，直通衬底隧道126触及带图案的源极本体金属层25c和钝化层34，但是受带图案的源极本体金属层25c和钝化层34的限制。与之类似，直通衬底隧道127触及带图案的栅极金属层26h和钝化层34，但是受带图案的栅极金属层26h和钝化层34的限制。
在图11J中，在制备中的器件上方，沉积底部通孔绝缘层130(例如氧化物或聚合材料)，也就是说，在半导体衬底21的底部和漏极金属22以及钝化物30的上方，以及直通衬底隧道128、126、127裸露的表面上方。
在图11K中，直接刻蚀掉(例如通过直接等离子刻蚀工艺)通孔绝缘层130所有的水平定向层部分，使分段的顶部漏极金属35、带图案的源极本体金属层25c、带图案的栅极金属层26h以及漏极金属元件22裸露出来，保留分别位于直通衬底隧道128、126、127的侧壁上方的漏极通孔绝缘层33、源极通孔绝缘层31以及栅极通孔绝缘层32。
在图11L中，用导电通孔材料132过填充直通衬底隧道128、126、127、漏极金属钝化物30以及漏极金属22。作为一个示例工艺，首先在制备中的器件所有裸露的底面上方，溅射一个种子层。然后，在种子层上方，电镀厚金属，直到电镀的厚金属填满并形成导电通孔材料132为止。作为一种示例材料，厚金属为铜，种子层是由钛和铜制成。还可选择，用CMP平整化导电通孔材料132的底面，并对制备中的器件退火，以消除其内部应力。作为另一种选择，可以用第一金属化过程，填充通孔，然后用第二金属化过程，在通孔上方，形成底部接触垫。
在图11M中，形成导电通孔材料132的底部图案，以制成所需的底部漏极接触垫28b、底部源极接触垫26b和底部栅极接触垫27b，它们分别是导电直通衬底漏极通孔28、导电直通衬底源极通孔26和导电直通衬底栅极通孔27的一部分。然后，从制备中的器件上除去临时的支撑器件，以制成厚度为TSVP的最终的可堆栈式垂直功率MOSFET 2402。要注意的是，我们的目的是：
a.导电直通衬底漏极通孔28与半导体衬底21和顶部源极接触垫26a绝缘，同时，与漏极金属层22、顶部漏极接触垫28a以及底部漏极接触垫28b相接触。
b.导电直通衬底源极通孔26与半导体衬底21和底部漏极金属层22绝缘，同时，与顶部源极接触垫26a以及底部源极接触垫26b相接触。
c.导电直通衬底栅极通孔27与半导体衬底21和底部漏极金属层22绝缘，同时，与顶部栅极接触垫27a以及底部栅极接触垫27b相接触。
图12A至图12G表示制备图8所示的三重可堆栈式垂直功率MOSFET堆栈400的底部可堆栈式垂直功率MOSFET单元可堆栈式垂直功率MOSFET1401的详细化简工艺流程。该工艺简化为底部可堆栈式垂直功率MOSFET单元401，导电直通衬底源极通孔26和导电直通衬底栅极通孔27都不需要该工艺。
图12A中除了不带有分段的顶部漏极金属35(图11C)，并且相互间隔的源极本体区和带沟槽的栅极区数量有所增加之外，其他都与图11C类似。因此，对于本领域的技术人员而言，只要相应地调整掩膜设备，就可以用与图11C相同的工艺制备图12A所示的制备中的器件。要注意的是，在带图案的源极本体金属层25a和带图案的源极本体金属层25c之间的源极本体金属层中，要留有开口，以用于将来的导电直通衬底漏极通孔。
图12B至图12E表示部分直通衬底漏极通孔(PTSDV)138及其顶部漏极接触垫28a的制备。
在图12B中，沉积一个顶部钝化层，并形成图案，以制备带图案的顶部钝化元件29，邻近带图案的源极本体金属层25a、带图案的源极本体金属层25c以及带图案的栅极金属层26h。顶部钝化元件29a29d可以用氧化物、氮化物或两者的组合制成。
在图12C中，通过直接部分刻蚀到半导体衬底21中，制备衬底中的沟槽134，顶部钝化元件29、带图案的源极本体接触25c以及带图案的栅极金属层26h作为硬掩膜。
在图12D中，在制备中的器件(包括衬底中的沟槽134裸露的表面)上方，沉积通孔绝缘材料130(例如氧化物或聚合材料)，然后各向异性地回刻，以除去它的水平部分，同时保留衬底中的沟槽134侧壁上的漏极通孔绝缘层33。
在图12E中，用导电通孔材料132，过填充衬底中的沟槽134和顶部钝化物29，以制备部分直通衬底漏极通孔部分导电直通衬底漏极通孔138，直通衬底漏极通孔部分导电直通衬底漏极通孔138通过通孔绝缘层130，与半导体衬底21绝缘。然后，形成导电通孔材料132的顶部图案，以制备所需的顶部漏极接触垫28a、顶部源极接触垫26a以及顶部栅极接触垫27a，顶部漏极接触垫28a作为部分导电直通衬底漏极通孔138的一部分。要注意的是，从图12A至图12E所示的全部工艺都是在原始厚度为TORG的半导体衬底21上进行的。
在图12F中，通过背部减薄，将半导体衬底21的厚度减至所需的超薄厚度TSVP。由于，设计的部分导电直通衬底漏极通孔138要部分穿过半导体衬底21，从而使部分导电直通衬底漏极通孔的底部将触及到稍后减薄的厚度为T的半导体衬底21上方，同时，底部减薄将变短后的部分导电直通衬底漏极通孔底部裸露出来，用于外部接触。由于，底部晶片除了回刻和背部金属化之外，不再需要其他处理(即，不需要再形成导电直通通孔)，因此，在这种情况下，其实不需要临时支撑器件。但是，如果的确需要，仍可选用临时支撑器件。
在图12G中，在减薄的半导体衬底21上方，形成一个底部漏极金属层22。最终的可堆栈式垂直功率MOSFET 1401的厚度为TSVP，并且具有一个直通衬底漏极通孔28。参照上述制备如图8所示的三重可堆栈式垂直功率MOSFET堆栈400的中间可堆栈式垂直功率MOSFET 2402和底部可堆栈式垂直功率MOSFET 1401的详细工艺，本领域的技术人员应掌握，如何制备三重可堆栈式垂直功率MOSFET堆栈400的顶部可堆栈式垂直功率MOSFET 3403。
尽管上述说明含有许多具体参数，但是这些参数仅仅用作对本发明现有的较佳实施例的解释说明，而不应作为本发明范围的局限。例如，除了MOSFET之外，本发明也可用于一般的垂直功率半导体器件，在这些器件中，器件电流主要集中在其正面和背部衬底之间，例如绝缘栅双极晶体管(IGBT)。
通过说明和附图，给出了关于典型结构的各种典型实施例。对于本领域的技术人员应显而易见，本发明可以用于各种其他特殊形式，上述各种实施例经过轻松修改，就可以适合于其他具体应用。本专利文件旨在说明，本发明的范围不应局限于上述说明中的典型实施例，而应由以下的权利要求书来界定。任何和所有来自于权利要求书中内容或同等范围中的修正，都将被认为属于本发明的保护范围之内。

Claims (21)

1.一种可堆栈式垂直功率MOSFET(SVP-MOSFET)器件包括：
一个形成在它上面的带有底部漏极金属层的半导体衬底；
多个形成在半导体衬底上方的交叉指型的栅极区和源极本体区；
一个带图案的栅极金属层和一个带图案的源极本体金属层，它们分别接触栅极区和源极本体区；以及下列顶目中的至少一个：
一个导电直通衬底漏极通孔(TSDV)，穿过半导体衬底，并与漏极金属层接触，但与半导体衬底绝缘，具有一个顶部漏极接触结构和一个底部漏极接触结构，分别在顶面和底面电接触到导电直通衬底漏极通孔上；
一个导电直通衬底栅极通孔(TSGV)，穿过半导体衬底，并与栅极金属层接触，但与半导体衬底绝缘，具有一个顶部栅极接触结构和一个底部栅极接触结构，分别在顶面和底面电接触到导电直通衬底栅极通孔上；以及
一个导电直通衬底源极通孔(TSSV)，穿过半导体衬底，并与源极本体金属层接触，但与半导体衬底绝缘，具有一个顶部源极接触结构和一个底部源极接触结构，分别在顶面和底面电接触到导电直通衬底源极通孔上；
当多个可堆栈式垂直功率MOSFET器件一个压一个地向上堆栈起来，所形成的可堆栈式垂直功率MOSFET堆栈就会起并联导电连接的作用，从而降低了导通电阻Rds、增大了载流能力并减少了封装引脚。
2.如权利要求1所述的可堆栈式垂直功率MOSFET，其特征在于，可堆栈式垂直功率MOSFET器件厚度约为5微米至100微米。
3.如权利要求1所述的可堆栈式垂直功率MOSFET，其特征在于，每个位于导电直通衬底漏极通孔附近的所述的源极本体区，都带有一个源极本体切断剖面，距离导电直通衬底漏极通孔足够远，以承载它们之间的漏极源极电压。
4.如权利要求1所述的可堆栈式垂直功率MOSFET，其特征在于，每个所述的导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔还包括一个相应的通孔绝缘层包围着它，从而使它与半导体衬底绝缘。
5.一种封装多单元可堆栈式垂直功率MOSFET的堆栈包括：
多个可堆栈式功率MOSFET单元一个压一个地向上粘合，每个可堆栈式功率MOSFET单元包括：
一个形成在它上面的带有底部漏极金属层的半导体衬底；
多个形成在半导体衬底上方的交叉指型的栅极区和源极本体区；
一个带图案的栅极金属层和一个带图案的源极本体金属层，它们分别接触栅极区和源极本体区；以及下列项目中的至少一个：
一个导电直通衬底漏极通孔(TSDV)，穿过半导体衬底，并与漏极金属层接触，但与半导体衬底绝缘，具有一个顶部漏极接触结构和一个底部漏极接触结构，分别在顶面和底面电接触到导电直通衬底漏极通孔上；
一个导电直通衬底栅极通孔(TSGV)，穿过半导体衬底，并与栅极金属层接触，但与半导体衬底绝缘，具有一个顶部栅极接触结构和一个底部栅极接触结构，分别在顶面和底面电接触到导电直通衬底栅极通孔导电直通衬底栅极通孔上；以及
一个导电直通衬底源极通孔(TSSV)，穿过半导体衬底，并与源极本体金属层接触，但与半导体衬底绝缘，具有一个顶部源极接触结构和一个底部源极接触结构，分别在顶面和底面电接触到导电直通衬底源极通孔上；
使得该堆栈起到可堆栈式功率MOSFET器件的并联导电连接的作用，从而降低了导通电阻Rds、增大了载流能力并减少了封装引脚。
6.如权利要求5所述的封装堆栈，其特征在于，在含有导电直通衬底源极通孔和/或导电直通衬底漏极通孔的一个可堆栈式功率MOSFET单元中，导电直通衬底源极通孔和/或导电直通衬底漏极通孔分布在整个MOSFET单元的有源区上。
7.如权利要求5所述的封装堆栈，其特征在于，在含有多个导电直通衬底源极通孔和导电直通衬底漏极通孔的一个可堆栈式功率MOSFET单元中，导电直通衬底源极通孔和导电直通衬底漏极通孔相互间隔，相互电绝缘。
8.如权利要求5所述的封装堆栈，其特征在于，导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔在它们各自的可堆栈式功率MOSFET单元的主器件平面内，都设置于恰当的位置，因此，一旦将它们堆栈起来：
功率MOSFET单元的顶部漏极接触结构和底部漏极接触结构就会分别与它们相邻的功率MOSFET单元的底部漏极接触结构和顶部漏极接触结构对齐；
功率MOSFET单元的顶部栅极接触结构和底部栅极接触结构就会分别与它们相邻的功率MOSFET单元的底部栅极接触结构和顶部栅极接触结构对齐；并且
功率MOSFET单元的顶部源极接触结构和底部源极接触结构就会分别与它们相邻的功率MOSFET单元的底部源极接触结构和顶部源极接触结构对齐。
9.如权利要求5所述的封装堆栈，其特征在于，每个位于导电直通衬底漏极通孔附近的所述的源极本体区，都带有一个源极本体切断剖面，距离导电直通衬底漏极通孔足够远，以承载它们之间的漏极源极电压。
10.如权利要求5所述的封装堆栈，其特征在于，每个所述的导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔还包括一个相应的通孔绝缘层包围着它，从而使它与半导体衬底绝缘。
11.如权利要求5所述的封装堆栈，其特征在于，最底部的功率MOSFET单元仅含有导电直通衬底漏极通孔，最顶部的功率MOSFET单元仅含有导电直通衬底栅极通孔和导电直通衬底源极通孔，并且其中如果有中间的功率MOSFET单元，则中间功率MOSFET单元含有导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔。
12.一种封装的多单元功率MOSFET堆栈的制备方法，该封装的多单元功率MOSFET堆栈具有多个功率MOSFET单元一个压一个地向上粘合，并且相互并联，该方法包括：
制备多个可堆栈式功率MOSFET单元，每个可堆栈式功率MOSFET单元都具有：
一个形成在它上面的带有底部漏极金属层的半导体衬底；
多个形成在半导体衬底上方的交叉指型的栅极区和源极本体区；
一个带图案的栅极金属层和一个带图案的源极本体金属层，它们分别接触栅极区和源极本体区；并且直通衬底通孔含有下列顶目中的至少一个：
一个导电直通衬底漏极通孔(TSDV)，与漏极金属层接触，具有一个顶部漏极接触结构和一个底部漏极接触结构，分别在顶面和底面电接触到导电直通衬底漏极通孔上；
一个导电直通衬底栅极通孔(TSGV)，与栅极金属层接触，具有一个顶部栅极接触结构和一个底部栅极接触结构，分别在顶面和底面电接触到导电直通衬底栅极通孔上；以及
一个导电直通衬底源极通孔(TSSV)，与源极本体金属层接触，具有一个顶部源极接触结构和一个底部源极接触结构，分别在顶面和底面电接触到导电直通衬底源极通孔上；
将功率MOSFET单元一个压一个地向上堆栈并粘合，以构成带有由导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔实现的并联连接的多单元功率MOSFET堆栈；并且
将该堆栈与其外部作业环境互联。
13.如权利要求12所述的方法，其特征在于，在含有导电直通衬底漏极通孔和/或导电直通衬底源极通孔的一个功率MOSFET单元中，该方法还包括将导电直通衬底漏极通孔和/或导电直通衬底源极通孔分布在整个MOSFET单元的有源区上。
14.如权利要求12所述的方法，其特征在于，每个功率MOSFET单元都有一个超薄厚度，以便减少多单元功率MOSFET堆栈相应的厚度和导通电阻Rds，因此，制备每个功率MOSFET单元还包括：
制备功率MOSFET单元的顶部；
将衬底晶圆的底部减薄至所需的超薄厚度，并制备导电直通衬底漏极通孔加上其底部漏极接触结构、导电直通衬底栅极通孔加上其底部栅极接触结构以及导电直通衬底源极通孔加上其底部源极接触结构的至少其中之一。
15.如权利要求14所述的方法，其特征在于：
制备导电直通衬底漏极通孔加上其底部漏极接触结构、导电直通衬底栅极通孔加上其底部栅极接触结构以及导电直通衬底源极通孔加上其底部源极接触结构的至少其中之一；
还包括将它们并行进行。
16.如权利要求15所述的方法，其特征在于，还包括：
制备一个底部漏极金属层，并且如果需要，就在各个需要导电直通衬底漏极通孔、导电直通衬底栅极通孔和导电直通衬底源极通孔的位置处，打开底部漏极金属层；以及
如果需要，就同时制备：
在需要导电直通衬底漏极通孔的位置处，一起制备导电直通衬底漏极通孔及其底部漏极接触结构，使导电直通衬底漏极通孔与半导体衬底绝缘，同时，与顶部漏极接触结构、底部漏极接触结构以及底部漏极金属层电接触；
在需要导电直通衬底栅极通孔的位置处，一起制备导电直通衬底栅极通孔及其底部栅极接触结构，使导电直通衬底栅极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部栅极接触结构、底部栅极接触结构以及栅极金属层电接触；并且
在需要导电直通衬底源极通孔的位置处，一起制备导电直通衬底源极通孔及其底部源极接触结构，使导电直通衬底源极通孔与半导体衬底以及漏极金属层绝缘，同时，与顶部源极接触结构、底部源极接触结构以及源极本体金属层电接触。
17.如权利要求12所述的方法，其特征在于，为底部可堆栈式功率MOSFET单元，制备导电直通衬底漏极通孔加上其底部漏极接触结构，还包括：
在需要导电直通衬底漏极通孔的位置处，打开源极本体金属层；
在需要导电直通衬底漏极通孔的位置处，一起制备一个部分直通衬底漏极通孔(PTSDV)及其顶部漏极接触结构，使部分直通衬底漏极通孔：与半导体衬底绝缘；并且
部分穿入半导体晶圆中；
将衬底晶圆的底部减薄至所需厚度，同时将部分直通衬底漏极通孔的底部裸露出来，以制成导电直通衬底漏极通孔；并且
在衬底晶圆上形成一个底部漏极金属层。
18.如权利要求12所述的方法，其特征在于，制备直通衬底通孔还包括：
在半导体衬底上方，制备一个顶部金属层；
将顶部金属层分段设置成源极本体金属层、栅极金属层以及在需要导电直通衬底漏极通孔的位置处，设置顶部漏极金属层；
制备一个底部漏极金属层，并在需要直通衬底通孔的位置处，打开它；并且
在需要直通衬底通孔的位置处，制备带有底部接触结构的直通衬底通孔，使直通衬底通孔与半导体衬底绝缘，同时与合适的顶部分段金属层和底部接触结构相接触，其中，导电直通衬底源极通孔和导电直通衬底栅极通孔与底部漏极金属绝缘。
19.如权利要求18所述的方法，其特征在于，制备直通衬底通孔还包括：
在底部漏极金属层上，沉积一个漏极金属钝化物并形成图案，同时包围着需要直通衬底通孔处；
以带开口的底部漏极金属层和带图案的漏极金属钝化物作为掩膜，对半导体衬底进行定向刻蚀，以形成一个直通衬底隧道，触及分段的顶部金属层，但受分段的顶部金属层限制；并且
在直通衬底隧道内，制备直通衬底通孔，并且在底部漏极金属层和漏极金属钝化物上，制备底部接触结构。
20.如权利要求19所述的方法，其特征在于，制备直通衬底通孔还包括：
在直通衬底隧道裸露的表面上方，制备一个通孔绝缘层；
定向刻蚀掉通孔绝缘层的所有的水平导向层，以便裸露出在直通衬底隧道末端的分段的顶部金属层；
用导电通孔材料，过填充直通衬底隧道和带图案的漏极金属钝化物；并且
形成导电通孔材料底部的图案，以形成底部接触结构。
21.如权利要求20所述的方法，其特征在于，用导电通孔材料过填充包括：
在半导体衬底的背面，溅射一个种子层；
在种子层上方电镀厚金属，直到厚金属过填充直通衬底隧道以及带图案的漏极金属钝化物为止，从而构成一个底面金属层。
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