CN102217037A - 制备用于制造异质结构体的蓝宝石衬底的表面 - Google Patents

制备用于制造异质结构体的蓝宝石衬底的表面 Download PDF

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Publication number
CN102217037A
CN102217037A CN2009801460442A CN200980146044A CN102217037A CN 102217037 A CN102217037 A CN 102217037A CN 2009801460442 A CN2009801460442 A CN 2009801460442A CN 200980146044 A CN200980146044 A CN 200980146044A CN 102217037 A CN102217037 A CN 102217037A
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CN
China
Prior art keywords
substrate
bonding
sapphire
baking
silicon
Prior art date
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Pending
Application number
CN2009801460442A
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English (en)
Chinese (zh)
Inventor
圭塔兹·戈丹
马克·肯纳德
马瑟奥·皮钦
约努茨·拉杜
亚历山大·沃弗雷达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
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Soitec SA
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Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN102217037A publication Critical patent/CN102217037A/zh
Pending legal-status Critical Current

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1922Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00Bonding of wafers, substrates or parts of devices
    • H10P10/12Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19Preparing inhomogeneous wafers
    • H10P90/1904Preparing vertically inhomogeneous wafers
    • H10P90/1906Preparing SOI wafers
    • H10P90/1914Preparing SOI wafers using bonding
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10Isolation regions comprising dielectric materials
    • H10W10/181Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Ceramic Products (AREA)
CN2009801460442A 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面 Pending CN102217037A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0857854A FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
FR0857854 2008-11-19
PCT/EP2009/065202 WO2010057842A1 (en) 2008-11-19 2009-11-16 Preparing a surface of a sapphire substrate for fabricating heterostructures

Publications (1)

Publication Number Publication Date
CN102217037A true CN102217037A (zh) 2011-10-12

Family

ID=40796247

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801460442A Pending CN102217037A (zh) 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面

Country Status (7)

Country Link
US (1) US20120015497A1 (enExample)
EP (1) EP2359391A1 (enExample)
JP (1) JP2012509581A (enExample)
KR (1) KR20110086038A (enExample)
CN (1) CN102217037A (enExample)
FR (1) FR2938702B1 (enExample)
WO (1) WO2010057842A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190835A (zh) * 2013-05-01 2015-12-23 信越化学工业株式会社 混合基板的制造方法和混合基板
CN108493321A (zh) * 2018-03-26 2018-09-04 华灿光电(浙江)有限公司 一种发光二极管芯片及其制备方法
CN114695602A (zh) * 2020-12-29 2022-07-01 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN119812021A (zh) * 2024-12-27 2025-04-11 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2012136267A1 (de) 2011-04-08 2012-10-11 Ev Group E. Thallner Gmbh Verfahren zum permanenten bonden von wafern
FR2977260B1 (fr) 2011-06-30 2013-07-19 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiale epaisse de nitrure de gallium sur un substrat de silicium ou analogue et couche obtenue par ledit procede
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
CN107195541B (zh) * 2012-07-24 2020-07-24 Ev 集团 E·索尔纳有限责任公司 永久结合晶圆的方法及装置
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9608433B2 (en) * 2013-03-14 2017-03-28 Hubbell Incorporated GFCI test monitor circuit
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
FR3034252B1 (fr) * 2015-03-24 2018-01-19 Soitec Procede de reduction de la contamination metallique sur la surface d'un substrat
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components
FR3042649B1 (fr) * 2015-10-20 2019-06-21 Soitec Procede de fabrication d'une structure hybride
EP3640971A1 (de) * 2016-02-16 2020-04-22 EV Group E. Thallner GmbH Verfahren und vorrichtung zum bonden von substraten
FR3068508B1 (fr) 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
CN111041423B (zh) * 2019-12-10 2021-11-19 太原理工大学 蓝宝石表面结构与成分梯度层设计改善其焊接性能的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH05235312A (ja) * 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
JP3250721B2 (ja) * 1995-12-12 2002-01-28 キヤノン株式会社 Soi基板の製造方法
EP1018153A1 (en) * 1997-08-29 2000-07-12 Sharon N. Farrens In situ plasma wafer bonding method
US6423613B1 (en) * 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6281146B1 (en) * 1999-09-15 2001-08-28 Taiwan Semiconductor Manufacturing Company Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US6930041B2 (en) * 2000-12-07 2005-08-16 Micron Technology, Inc. Photo-assisted method for semiconductor fabrication
US6576564B2 (en) * 2000-12-07 2003-06-10 Micron Technology, Inc. Photo-assisted remote plasma apparatus and method
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
SE521938C2 (sv) * 2001-12-27 2003-12-23 Cerbio Tech Ab Keramiskt material, förfarande för framställning av keramiskt material och benimplantat, tandfyllnadsimplantat och biocement innefattande det keramiska materialet
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
DE10326578B4 (de) * 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190835A (zh) * 2013-05-01 2015-12-23 信越化学工业株式会社 混合基板的制造方法和混合基板
CN105190835B (zh) * 2013-05-01 2018-11-09 信越化学工业株式会社 混合基板的制造方法和混合基板
CN108493321A (zh) * 2018-03-26 2018-09-04 华灿光电(浙江)有限公司 一种发光二极管芯片及其制备方法
CN114695602A (zh) * 2020-12-29 2022-07-01 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN114695602B (zh) * 2020-12-29 2025-12-16 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN119812021A (zh) * 2024-12-27 2025-04-11 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法
CN119812021B (zh) * 2024-12-27 2025-06-27 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法

Also Published As

Publication number Publication date
FR2938702B1 (fr) 2011-03-04
US20120015497A1 (en) 2012-01-19
EP2359391A1 (en) 2011-08-24
KR20110086038A (ko) 2011-07-27
FR2938702A1 (fr) 2010-05-21
JP2012509581A (ja) 2012-04-19
WO2010057842A1 (en) 2010-05-27

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Application publication date: 20111012