CN102217037A - 制备用于制造异质结构体的蓝宝石衬底的表面 - Google Patents

制备用于制造异质结构体的蓝宝石衬底的表面 Download PDF

Info

Publication number
CN102217037A
CN102217037A CN2009801460442A CN200980146044A CN102217037A CN 102217037 A CN102217037 A CN 102217037A CN 2009801460442 A CN2009801460442 A CN 2009801460442A CN 200980146044 A CN200980146044 A CN 200980146044A CN 102217037 A CN102217037 A CN 102217037A
Authority
CN
China
Prior art keywords
substrate
bonding
sapphire
baking
silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801460442A
Other languages
English (en)
Chinese (zh)
Inventor
圭塔兹·戈丹
马克·肯纳德
马瑟奥·皮钦
约努茨·拉杜
亚历山大·沃弗雷达
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec SA filed Critical Soitec SA
Publication of CN102217037A publication Critical patent/CN102217037A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Ceramic Products (AREA)
CN2009801460442A 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面 Pending CN102217037A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0857854 2008-11-19
FR0857854A FR2938702B1 (fr) 2008-11-19 2008-11-19 Preparation de surface d'un substrat saphir pour la realisation d'heterostructures
PCT/EP2009/065202 WO2010057842A1 (en) 2008-11-19 2009-11-16 Preparing a surface of a sapphire substrate for fabricating heterostructures

Publications (1)

Publication Number Publication Date
CN102217037A true CN102217037A (zh) 2011-10-12

Family

ID=40796247

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801460442A Pending CN102217037A (zh) 2008-11-19 2009-11-16 制备用于制造异质结构体的蓝宝石衬底的表面

Country Status (7)

Country Link
US (1) US20120015497A1 (enExample)
EP (1) EP2359391A1 (enExample)
JP (1) JP2012509581A (enExample)
KR (1) KR20110086038A (enExample)
CN (1) CN102217037A (enExample)
FR (1) FR2938702B1 (enExample)
WO (1) WO2010057842A1 (enExample)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190835A (zh) * 2013-05-01 2015-12-23 信越化学工业株式会社 混合基板的制造方法和混合基板
CN108493321A (zh) * 2018-03-26 2018-09-04 华灿光电（浙江）有限公司 一种发光二极管芯片及其制备方法
CN114695602A (zh) * 2020-12-29 2022-07-01 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN119812021A (zh) * 2024-12-27 2025-04-11 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2695183A1 (de) 2011-04-08 2014-02-12 Ev Group E. Thallner GmbH Verfahren zum permanenten bonden von wafern
FR2977260B1 (fr) 2011-06-30 2013-07-19 Soitec Silicon On Insulator Procede de fabrication d'une couche epitaxiale epaisse de nitrure de gallium sur un substrat de silicium ou analogue et couche obtenue par ledit procede
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US10052848B2 (en) 2012-03-06 2018-08-21 Apple Inc. Sapphire laminates
CN104488065B (zh) * 2012-07-24 2017-09-05 Ev 集团 E·索尔纳有限责任公司 永久结合晶圆的方法及装置
US9221289B2 (en) 2012-07-27 2015-12-29 Apple Inc. Sapphire window
US9232672B2 (en) 2013-01-10 2016-01-05 Apple Inc. Ceramic insert control mechanism
US9608433B2 (en) * 2013-03-14 2017-03-28 Hubbell Incorporated GFCI test monitor circuit
US9632537B2 (en) 2013-09-23 2017-04-25 Apple Inc. Electronic component embedded in ceramic material
US9678540B2 (en) 2013-09-23 2017-06-13 Apple Inc. Electronic component embedded in ceramic material
US9154678B2 (en) 2013-12-11 2015-10-06 Apple Inc. Cover glass arrangement for an electronic device
US9225056B2 (en) 2014-02-12 2015-12-29 Apple Inc. Antenna on sapphire structure
FR3034252B1 (fr) * 2015-03-24 2018-01-19 Soitec Procede de reduction de la contamination metallique sur la surface d'un substrat
US10406634B2 (en) 2015-07-01 2019-09-10 Apple Inc. Enhancing strength in laser cutting of ceramic components
FR3042649B1 (fr) * 2015-10-20 2019-06-21 Soitec Procede de fabrication d'une structure hybride
KR102580005B1 (ko) * 2016-02-16 2023-09-18 에베 그룹 에. 탈너 게엠베하 기판을 접합하기 위한 방법 및 장치
FR3068508B1 (fr) 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
CN111041423B (zh) * 2019-12-10 2021-11-19 太原理工大学 蓝宝石表面结构与成分梯度层设计改善其焊接性能的方法

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5849627A (en) * 1990-02-07 1998-12-15 Harris Corporation Bonded wafer processing with oxidative bonding
JPH0636413B2 (ja) * 1990-03-29 1994-05-11 信越半導体株式会社 半導体素子形成用基板の製造方法
JPH05235312A (ja) * 1992-02-19 1993-09-10 Fujitsu Ltd 半導体基板及びその製造方法
US5441591A (en) * 1993-06-07 1995-08-15 The United States Of America As Represented By The Secretary Of The Navy Silicon to sapphire bond
JP3250721B2 (ja) * 1995-12-12 2002-01-28 キヤノン株式会社 Ｓｏｉ基板の製造方法
US6180496B1 (en) * 1997-08-29 2001-01-30 Silicon Genesis Corporation In situ plasma wafer bonding method
US6423613B1 (en) * 1998-11-10 2002-07-23 Micron Technology, Inc. Low temperature silicon wafer bond process with bulk material bond strength
US6281146B1 (en) * 1999-09-15 2001-08-28 Taiwan Semiconductor Manufacturing Company Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
US6930041B2 (en) * 2000-12-07 2005-08-16 Micron Technology, Inc. Photo-assisted method for semiconductor fabrication
US6576564B2 (en) * 2000-12-07 2003-06-10 Micron Technology, Inc. Photo-assisted remote plasma apparatus and method
US20030089950A1 (en) * 2001-11-15 2003-05-15 Kuech Thomas F. Bonding of silicon and silicon-germanium to insulating substrates
SE521938C2 (sv) * 2001-12-27 2003-12-23 Cerbio Tech Ab Keramiskt material, förfarande för framställning av keramiskt material och benimplantat, tandfyllnadsimplantat och biocement innefattande det keramiska materialet
US7339187B2 (en) * 2002-05-21 2008-03-04 State Of Oregon Acting By And Through The Oregon State Board Of Higher Education On Behalf Of Oregon State University Transistor structures
US6911375B2 (en) * 2003-06-02 2005-06-28 International Business Machines Corporation Method of fabricating silicon devices on sapphire with wafer bonding at low temperature
DE10326578B4 (de) * 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
FR2884966B1 (fr) * 2005-04-22 2007-08-17 Soitec Silicon On Insulator Procede de collage de deux tranches realisees dans des materiaux choisis parmi les materiaux semiconducteurs
US7601271B2 (en) * 2005-11-28 2009-10-13 S.O.I.Tec Silicon On Insulator Technologies Process and equipment for bonding by molecular adhesion

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105190835A (zh) * 2013-05-01 2015-12-23 信越化学工业株式会社 混合基板的制造方法和混合基板
CN105190835B (zh) * 2013-05-01 2018-11-09 信越化学工业株式会社 混合基板的制造方法和混合基板
CN108493321A (zh) * 2018-03-26 2018-09-04 华灿光电（浙江）有限公司 一种发光二极管芯片及其制备方法
CN114695602A (zh) * 2020-12-29 2022-07-01 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN114695602B (zh) * 2020-12-29 2025-12-16 广东中图半导体科技股份有限公司 一种双层图形化蓝宝石衬底、制备方法及led外延片
CN119812021A (zh) * 2024-12-27 2025-04-11 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法
CN119812021B (zh) * 2024-12-27 2025-06-27 杭州芯聚半导体有限公司 一种蓝宝石衬底与硅衬底热压键合涨缩问题的改善方法

Also Published As

Publication number Publication date
EP2359391A1 (en) 2011-08-24
JP2012509581A (ja) 2012-04-19
FR2938702B1 (fr) 2011-03-04
US20120015497A1 (en) 2012-01-19
KR20110086038A (ko) 2011-07-27
WO2010057842A1 (en) 2010-05-27
FR2938702A1 (fr) 2010-05-21

Similar Documents

Publication Publication Date Title
CN102217037A (zh) 制备用于制造异质结构体的蓝宝石衬底的表面
CN101601123B (zh) 键合两个衬底的方法
US20110195560A1 (en) Method of producing a silicon-on-sapphire type heterostructure
US8314007B2 (en) Process for fabricating a heterostructure with minimized stress
CN100477150C (zh) 制造包含薄半导体层的结构的方法、所获得的中间结构以及该方法的应用
US8202785B2 (en) Surface treatment for molecular bonding
CN107533953B (zh) 具有可控膜应力的在硅衬底上沉积电荷捕获多晶硅膜的方法
JP6373354B2 (ja) ライトポイント欠陥と表面粗さを低減するための半導体オンインシュレータウエハの製造方法
JP5926527B2 (ja) 透明ｓｏｉウェーハの製造方法
JP5065748B2 (ja) 貼り合わせウエーハの製造方法
KR101541940B1 (ko) Ｓｏｉ 기판의 제조 방법
JP2008021971A (ja) 電子工学、光学または光電子工学に使用される２つの基板を直接接合する方法
WO2002043153A1 (fr) Procede de fabrication de plaquette de semi-conducteur
JP2001345435A (ja) シリコンウェーハ及び貼り合わせウェーハの製造方法、並びにその貼り合わせウェーハ
KR20080036209A (ko) 스트레인드 실리콘-온-인슐레이터 구조의 제조 방법
CN102986020A (zh) 对绝缘体基材上的硅进行精整的方法
WO2013102968A1 (ja) 貼り合わせｓｏｉウェーハの製造方法
JP5336101B2 (ja) Ｓｏｉ基板の製造方法
CN107615445B (zh) 绝缘体上硅晶圆的制造方法
CN101027769B (zh) 具有对要键合表面的处理的转移方法
WO2006035864A1 (ja) Ｓｏｉウエーハの洗浄方法
WO2014017368A1 (ja) Ｓｏｓ基板の製造方法及びｓｏｓ基板
CN118633150A (zh) 用于制造双绝缘体上半导体结构的方法
CN102272901A (zh) 用于制造电子领域中的衬底的修整方法
JP5368000B2 (ja) Ｓｏｉ基板の製造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20111012