CN102208388B - 半导体装置以及半导体装置的制造方法 - Google Patents

半导体装置以及半导体装置的制造方法 Download PDF

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CN102208388B
CN102208388B CN201110081344.6A CN201110081344A CN102208388B CN 102208388 B CN102208388 B CN 102208388B CN 201110081344 A CN201110081344 A CN 201110081344A CN 102208388 B CN102208388 B CN 102208388B
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electrode
semiconductor particles
circuit substrate
electronic devices
solder
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CN102208388A (zh
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樱井大辅
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

本发明提供一种窄间距、且确保高连接可靠性的简易结构的半导体装置及其制造方法。本发明包括：对电子元器件(1)的多个电极(1a)的至少一个电极赋予两个以上的焊料粒子(3)的工序；将电子元器件(1)的电极(1a)与电路基板(2)的电极(2a)相对配置的工序；使赋予电子元器件(1)的电极(1a)表面的焊料粒子(3)与电路基板(2)的电极(2a)相抵接的工序；以及加热焊料粒子(3)的工序，通过焊料粒子(3)熔融后的两个以上的焊料接合体(8)将电子元器件(1)的电极(1a)和电路基板(2)的电极(2a)进行电连接。

Description

半导体装置以及半导体装置的制造方法
技术领域
本发明涉及半导体装置以及半导体装置的制造方法。 
背景技术
近年来，为了进一步兼顾半导体元件的高密度化和电极端子的多引脚化，力图使半导体元件的电极端子实现窄间距化，力图使面积缩小。 
通常，在倒装芯片安装中，在LSI等半导体元件的电极端子上形成焊料凸点等突起电极，将该半导体元件通过面朝下与安装基板的连接端子进行压接、加热以进行凸点连接，由此进行安装。 
但是，由于窄间距化的进展显著，因此，在像以往那样将电极端子配置于外围的方法中，有时在电极端子之间发生短路，或因半导体元件和安装基板的热膨胀系数之差而发生连接不良等。因此，采用了通过将电极端子配置成区域状、来扩大电极端子之间的间距的方法，但是，近年来，即使是区域配置，窄间距化的进展也很显著。 
作为形成焊料凸点的方法，采用了如下工艺：通过丝网印刷、涂布机、电镀在电极上形成焊料，之后，通过利用回流炉加热至焊料熔点以上，形成突起状的焊料凸点。 
但是，近年来，由于焊料接合部的间距进一步变窄，半导体元件、基板电极之间的间隙也进一步变小，因此，引起了如下问题：在倒装芯片安装时的加热工序中，熔融的焊料变形，因焊料的表面张力而导致发生焊料凸点彼此连接的焊料桥接的不良情况。 
作为与这种要求相对应的方法，提出有对凸点采用两层结构的方法。 
例如，存在如下方法：形成含有金属粒子的绝缘性皮膜，以覆盖由金、铜形成的突起电极表面(例如，参照专利文献1)。根据该方法，绝缘性皮膜和突起电极在倒装芯片时不会熔融，能通过注入到半导体元件和基板之间 的密封树脂的固化收缩所产生的压缩方向的力，来实现电导通，从而能防止发生桥接，能应对窄间距化。 
然而，由于近年来所要求的电极之间的间距的窄间距化的要求非常严格，因此，像专利文献1那样，若金属粒子和金属电极是不进行扩散接合而仅通过接触来确保导通的连接形态，则会存在如下问题：若电极面积变小，则介于电极之间的导电粒子的数量当然会变少，连接电阻增加，信号的传送损耗增大。 
因此，采用如下方法：对凸点采用由下层金属和上层金属形成的两层结构，在由高熔点金属形成的下层金属上形成由焊料形成的上层金属(例如，参照专利文献2)。 
图7是示意性表示专利文献2中记载的实施例的半导体装置的剖视图。 
先在半导体元件11上形成由高熔点金属形成的电极11a，在电极11a上形成焊料13，使半导体元件11的电极11a与在电路基板12上形成的电极12a相对，从而进行位置对准，从电路基板12的上方装载半导体元件11，并进行加热和加压，从而半导体元件11的电极11a和电路基板12的电极12a彼此的整个表面通过焊料13进行扩散接合。 
根据该方法，与由一层焊料形成的凸点相比，能减少焊料量，在倒装芯片安装时朝平面方向的焊料浪费量减少，不仅能防止发生焊料桥接，而且，由于焊料和基板电极进行扩散接合，因此连接电阻降低，也不会增大信号的传送损耗。 
专利文献1：日本专利特开2003-282617号公报 
专利文献2：日本专利特开平9-97791号公报 
发明内容
然而，若对于利用低介电常数膜作为层间绝缘膜的半导体元件，采用上述那样的专利文献2的半导体装置制造技术，则在倒装芯片工序中的焊料熔融后的冷却过程中，存在脆弱的低介电常数膜产生剥离和龟裂的问题。 
出于与近年来所要求的布线规则的微细化和高速信号处理相对应的目的，利用低介电常数膜(所谓低k膜或ULK(超低k)膜等)作为半导体元件的层 间绝缘膜。为了降低介电常数，低介电常数膜本身采用具有大量的数nm的空孔的多孔状(多孔质)。 
图8(a)以及图8(b)是示意性表示在对于利用这种低介电常数绝缘膜14的半导体元件15采用了专利文献2的半导体装置制造技术的情况下、倒装芯片工序中的焊料熔融后的冷却过程中的半导体装置的剖视图。 
在采用了专利文献2那样的半导体装置制造技术的情况下，在倒装芯片工序中的焊料熔融后的冷却过程中，因半导体元件15与电路基板12的弹性率及线膨胀系数之差，而导致产生半导体元件15相对于电路基板12向翘曲的方向的热应力。该热应力集中于半导体元件15的转角部分的焊料13的接合部。因此，该热应力直接传递到半导体元件15的电极11a的正下方，如图8(a)及图8(b)所示，存在位于电极11a的正下方的脆弱的低介电常数绝缘膜14产生剥离和龟裂的问题。 
此外，即使在产生急剧温度差那样的使用环境下，也会产生同样的热应力集中，存在位于电极11a的正下方的脆弱的低介电常数绝缘膜14产生剥离和龟裂的问题。 
本发明鉴于上述问题，其目的在于提供一种在具有脆弱的膜的半导体元件中、能确保高连接可靠性的简易结构的半导体装置以及半导体装置的制造方法。 
为了解决上述问题，第一本发明是一种半导体装置，该半导体装置通过焊料将电子元器件的电极、和与该电极相对配置的电路基板的电极相接合，其特征在于， 
所述电子元器件的电极和所述电路基板的电极相对配置的至少一个电极组通过两个以上的焊料接合体相接合。 
此外，第二本发明是第一本发明的半导体装置，其特征在于， 
所述电极组有多个， 
具有最大相对间隔的所述电子元器件的电极和所述电路基板的电极通过两个以上的所述焊料接合体相接合。 
此外，第三本发明是一种半导体装置的制造方法，其特征在于， 
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的焊料 粒子的工序；将所述电子元器件的电极与电路基板的电极相对配置的工序；使赋予所述电子元器件的电极表面的焊料粒子与所述电路基板的电极相抵接的工序；以及加热所述焊料粒子的工序， 
所述电子元器件的电极和所述电路基板的电极通过所述焊料粒子熔融生成的两个以上的焊料接合体进行电连接。 
此外，第四本发明是一种半导体装置的制造方法，其特征在于， 
包括：对电路基板的多个电极的至少一个电极赋予两个以上的焊料粒子的工序；将所述电路基板的电极与电子元器件的电极相对配置的工序；使赋予所述电路基板的电极表面的焊料粒子与所述电子元器件的电极相抵接的工序；以及加热所述焊料粒子的工序， 
所述电路基板的电极和所述电子元器件的电极通过所述焊料粒子熔融生成的两个以上的焊料接合体进行电连接。 
此外，第五本发明是一种半导体装置的制造方法，其特征在于， 
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的第一焊料粒子的工序；对电路基板的多个电极的至少一个电极赋予两个以上的第二焊料粒子的工序；将所述电子元器件的电极与所述电路基板的电极相对配置的工序；进行使所述第一焊料粒子与所述电路基板的电极相抵接、使所述第二焊料粒子与所述电子元器件的电极相抵接、和使所述第一焊料粒子与所述第二焊料粒子相抵接中的至少一种抵接的工序；以及加热所述第一焊料粒子和所述第二焊料粒子的工序， 
对于所述相对配置的至少一个电极组，所述电路基板的电极和所述电子元器件的电极通过所述第一焊料粒子及所述第二焊料粒子熔融生成的两个以上的焊料接合体进行电连接。 
此外，第六本发明是第五本发明的半导体装置的制造方法，其特征在于， 
赋予所述电子元器件的电极表面的第一焊料粒子、和赋予所述电路基板的电极表面的第二焊料粒子的粒子间隔不同。 
此外，第七本发明是第五本发明的半导体装置的制造方法，其特征在于， 
赋予所述电子元器件的电极表面的第一焊料粒子、和赋予所述电路基板的电极表面的第二焊料粒子的粒子直径不同。 
此外，第八本发明是第六本发明的半导体装置的制造方法，其特征在于， 
赋予所述电子元器件的电极表面的第一焊料粒子、和赋予所述电路基板的电极表面的第二焊料粒子的粒子直径不同。 
此外，第九本发明是第五至第八的任一项的本发明的半导体装置的制造方法，其特征在于， 
赋予所述电子元器件的电极表面的第一焊料粒子的粒子间隔大于赋予所述电路基板的电极表面的第二焊料粒子的粒子直径。 
此外，第十本发明是第五至第八的任一项的本发明的半导体装置的制造方法，其特征在于， 
赋予所述电路基板的电极表面的第二焊料粒子的粒子间隔大于赋予所述电子元器件的电极表面的第一焊料粒子的粒子直径。 
根据上述半导体装置及其制造方法，在半导体装置中的具有脆弱的低介电常数膜的半导体元件的倒装芯片安装中，能确保优良的连接可靠性。 
根据本发明，能提供一种在具有脆弱的膜的半导体元件中、能确保高连接可靠性的简易结构的半导体装置以及半导体装置的制造方法。 
附图说明
图1是示意性表示本发明的实施方式1中的半导体装置的剖视图。 
图2(a)～图2(f)是示意性表示本发明的实施方式1中的半导体装置的制造方法的剖视图。 
图3(a)～图3(f)是示意性表示本发明的实施方式2中的半导体装置的制造方法的剖视图。 
图4(a)～图4(i)是示意性表示本发明的实施方式3中的半导体装置的制造方法的剖视图。 
图5(a)、图5(b)是示意性表示本发明的实施方式3中的焊料粒子附着基材的剖视图，图5(c)是示意性表示本发明的实施方式3中的半导体装置的剖 视图。 
图6(a)、图6(b)是示意性表示本发明的实施方式3中的焊料粒子附着基材的其他结构的焊料粒子配置的俯视图，图6(c)是示意性表示本发明的实施方式3中的、将采用了其他结构的焊料粒子配置的焊料粒子附着基材时的半导体元件安装于电路基板的工序的剖视图。 
图7是示意性表示现有的半导体装置的剖视图。 
图8(a)、图8(b)是示意性表示在采用了现有的半导体装置制造技术的情况下的、倒装芯片工序中的焊料熔融后的冷却过程中的半导体装置的剖视图。 
具体实施方式
下面，参照附图，详细说明本发明的实施方式。 
(实施方式1) 
图1是示意性表示本发明的实施方式1中的半导体装置的剖视图。 
在半导体元件1的电极面的内层，设置有包括例如由Cu、Al形成的微细布线层和脆弱的低介电常数绝缘膜(例如，低k层或超低k层)的多层布线层1c，利用区域配置在其最外表面上设置有多个电极端子1b。例如，电极端子1b由Al、Cu形成。在该电极端子1b上设置有由Ti/Cu、Ti/W/Cu等形成的籽晶层，其上设置有由Ni/Au、Au、Cu等焊料浸润的金属形成的突起状电极1a。 
另一方面，在安装了半导体元件1的电路基板2(例如由玻璃环氧多层基板、芳族聚酰胺多层基板、硅形成)上，具有与半导体元件1的突起状电极1a相对配置的电极端子2a。电极端子2a例如由Ni/Au、Ni/Pd/Au等形成。 
另外，半导体元件1相当于本发明的电子元器件的一个示例。此外，突起状电极1a相当于本发明的电子元器件的电极的一个示例，电极端子2a相当于本发明的电路基板的电极的一个示例。 
半导体元件1的突起状电极1a与电路基板2的电极端子2a通过焊料接合部3c进行电和机械连接，焊料接合部3c与突起状电极1a之间、以及焊料接合部3c与电极端子2a之间发生固相扩散或固液扩散反应，在中间形成合金 层7，牢固地进行接合。 
这里，在半导体元件1与电路基板2的间隔(图1中的B)成为最大的位置(图1中的A)的电极之间的焊料接合部3c由两个微小焊料接合体8形成。 
另外，微小焊料接合体8相当于本发明的焊料接合体的一个示例。 
在制造半导体装置时的焊料熔融工序的焊料熔融后的冷却过程中，由于半导体元件1与电路基板2的线膨胀系数不同，因此，在位于半导体元件1的最外围的接合部分附近，变得最容易发生翘曲，从而半导体元件1与电路基板2的间隔大多变得最大。 
而且，在半导体元件1的面内，在位于最外围的接合部分附近，热应力也变得最大。虽然像这样在间隔最大的位置A受到最大的热应力，但通过利用两个微小焊料接合体8进行连接，从而利用比一个微小焊料接合体时要小的面积来连接突起状电极1a及电极端子2a，在该面积较小的连接部分受到拉伸方向的力，由此，增加了对焊料部分的应力集中，应力集中点从包括脆弱的低介电常数绝缘膜的多层布线层1c向焊料接合部3c转移。 
但是，即使应力集中点向焊料接合部3c转移，但由于由两个微小焊料接合体8形成的焊料接合部3c的伸长率增大，突起状电极1a与电极端子2a牢固地进行接合，因此，焊料接合部3c也不会损坏而伸长，能防止多层布线层1c的脆弱的低介电常数绝缘膜发生剥离或龟裂。 
焊料的组成例如由SnAg、SnAgCu、SnZn、SnZnBi、SnPb、SnBi、SnAgBiIn、SnIn、In、Sn等形成，能根据焊料伸长率自由选择材料，以与最大间隔A的大小相匹配。 
例如，在半导体元件1的电极端子1b的间隔是0.05mm的情况下，突起状电极1a的直径是0.020～0.035mm，高度是0.05～0.20mm，电路基板2的电极端子2a的直径是0.020～0.035mm，高度是0.05～0.10mm，微小焊料接合体8的直径是0.002～0.010mm，直径的伸长率是50％。 
虽然未图示，但半导体元件1与电路基板2的电极面之间也可以填充密封树脂。通过填充密封树脂，进一步提高可靠性。 
图2(a)～图2(f)是示意性表示本实施方式1中的半导体装置的制造方法的剖视图。对于与图1相同的结构部分，使用相同的标号。 
利用图2，在下面说明本实施方式1的半导体装置的制造方法。 
首先，如图2(a)所示，通过溅射法或蒸镀，在晶圆形态的半导体元件1的电极面的整个表面上形成籽晶层。接下来，通过电镀工艺在整个表面上形成金属膜。在形成感光保护层、将电极端子1b的位置的突起状电极1a的形成部分曝光之后，利用剥离液将感光保护层剥离。通过该工序，在电极端子1b上形成突起状电极1a。例如，籽晶层使用Ti/Cu，金属膜使用Ni/Au，但并不限于此。另外，在形成籽晶层之前，在半导体元件1的电极面一侧，形成包括脆弱的低介电常数绝缘膜的多层布线层1c。 
接下来，如图2(b)所示，在对准突起状电极1a的位置、挖通成比突起状电极1a要大的形状的孔的转印用金属模4中，利用喷雾器或涂布机等方法对金属模4的整个表面提供粘接层5之后，对整个表面均匀地赋予焊料粒子3。 
接下来，如图2(c)所示，使半导体元件1的突起状电极1a、与对应于该突起状电极1a而设置于金属模4的凹孔相对，以这样的方式将金属模4和半导体元件1的位置对准，并进行加热和加压。由此，焊料粒子3和突起状电极1a熔融，且焊料粒子3彼此在保留粒子形状那样的温度、时间条件下进行加热加压。此时，若利用微细的焊料粒子3，则氧化皮膜所占的面积较大，容易阻碍熔融，能在保留粒子形状的状态下进行扩散。例如，焊料粒子3的直径为0.002～0.008mm时，在金属模4的温度：210℃、加压时间：10～50s下，并在大气压下进行了加压。 
接下来，如图2(d)所示，通过将金属模4从半导体元件1剥离，形成以粒子形状赋予焊料粒子3的突起状电极1a。之后，如图2(e)所示，通过刀片切割或激光切割等手段，将半导体元件1形成一个个单片。 
接下来，如图2(f)所示，与半导体元件1的突起状电极1a相对而使得与电路基板2的电极端子2a对准位置之后，进行加热，一边施加上拉负荷，一边以低负荷将半导体元件1装载在电路基板2上。此时，虽然焊料成为液体状，但通过低负荷加压到彼此相邻的焊料粒子3不会形成一体化的程度。例如，也可在加热温度：220～240℃、加压时间：3～10秒下进行加压。另外，也可以在装载半导体元件1之前提供助焊剂。即使是难以熔融的粒子形状的微细的焊料粒子3，也可通过助焊剂，提高焊料的浸润性，容易形成微细的 焊料接合部3c。 
这里，在焊料成为液体状的状态下以低负荷进行装载，从而半导体元件1和电路基板2无法保持平行而以倾斜状态进行按压，半导体元件1和电路基板2的平行度变差。但是，即使是半导体元件1的端部与电路基板2的距离最大的部位的电极彼此之间，由于微小焊料接合体8的部分像图2(f)那样伸长成鼓状而进行接合，因此，也能吸收平行度的恶化。 
在图2(f)的将半导体元件1安装于电路基板2时的焊料熔融工序的焊料熔融后的冷却过程中，若在焊料的熔点以上，则液体的焊料粒子3伸长，若低于焊料的凝固点，则同时焊料凝固，维持该形状。若进一步冷却，则由于焊料接合部3c的间隔因半导体元件1与电路基板2的线膨胀系数之差而变宽，因此，固体的焊料接合部3c在弹性区域内伸长，完成半导体装置。 
像图2(f)所示的焊料接合部3c那样，将伸长成鼓状的状态的微细焊料定义为“微小焊料接合体8”。半导体元件1的突起状电极1a和电路基板2的电极端子2a利用两个以上的微小焊料接合体8进行电连接。这里，半导体元件1与电路基板2的距离最小的部位的电极彼此可以利用多个微小焊料接合体8进行电连接，也可以利用与以往相同的一个焊料接合体进行电连接。 
通过截面研磨，对利用本实施方式1的制造方法制作的半导体装置进行截面分析，其结果能确认，位于最外围的焊料接合体3c由两个微小焊料接合体8形成，并确认多层布线层1c所包含的脆弱的低介电常数绝缘膜也没有发生剥离和龟裂。而且，投入到温度循环试验(1个循环：-45℃、85℃各5分钟)的结果是，即使是1000cyc(循环)，也能确保稳定的连接电阻。 
在利用本实施方式1的制造方法制作的半导体装置中，由于对使用环境下的温度变化，微小焊料接合体8在焊料接合部3c的弹性区域内进行伸缩，因此，利用焊料接合部3c的部分吸收缓和热应力，不会将应力传递到电极正下方，从而这样使用时能确保稳定的连接电阻。 
这样，处于半导体元件1与电路基板2的间隔离得最远的位置的焊料接合部3c利用两个微小焊料接合体8而形成，从而能减小脆弱的低介电常数绝缘膜受到的应力，确保高连接可靠性。 
(实施方式2) 
图3(a)～图3(f)是示意性表示本发明的实施方式2中的半导体装置的制造方法的剖视图。对于与图1及图2相同的结构部分，使用相同的标号。 
利用图3，在下面说明本实施方式2的半导体装置的制造方法。 
首先，如图3(a)所示，通过溅射法或蒸镀，在晶圆形态的半导体元件1的电极面的整个表面上形成籽晶层。接下来，通过电镀工艺在整个表面上形成金属膜。在形成感光保护层、将电极端子1b的位置的突起状电极1a的形成部分曝光之后，利用剥离液将感光保护层剥离。通过该工序，在电极端子1b上形成突起状电极1a。例如，籽晶层使用Ti/Cu，金属膜使用Cu，但并不限于此。另外，在半导体元件1的电极面一侧形成包括脆弱的低介电常数绝缘膜的多层布线层1c。 
接下来，如图3(b)所示，通过对半导体元件1进行刀片切割、激光加工，将半导体元件1形成一个个单片。 
接下来，如图3(c)所示，在由玻璃环氧多层基板形成的电路基板2上通过化学镀工艺形成突起状的电极端子2a。例如，电极端子2a的组成选定Ni/Au、Ni/Pd/Au、Cu等焊料的浸润性良好的材料。之后，为了对整个表面均匀地赋予焊料粒子3，因此，利用喷雾器或涂布机等方法对电路基板2的整个表面提供粘接层5。 
接下来，如图3(d)所示，利用回流炉等加热手段，对在整个表面上均匀地赋予了焊料粒子3的电路基板2进行加热，焊料粒子3和电极端子2a熔融，且在沿平面方向不引起焊料桥接而保留粒子形状那样的温度、时间、气体气氛的条件下进行加热。这里，若利用微细的焊料粒子3，则由于氧化皮膜所占的面积较大，容易阻碍熔融，因此，能在相邻的端子彼此之间不引起焊料桥接，而在保留粒子形状的状态下进行扩散。例如，焊料在利用Sn3.0Ag0.5Cu、焊料粒子直径为0.003～0.008mm时，在温度：225℃、加压时间：3～8s下，并在甲酸气体气氛中进行了加热。 
接下来，如图3(e)所示，将电路基板2浸渍于清洗液中，并施加超声波进行了清洗。通过该工序，存在于电极端子2a之间的焊料粒子3被去除，焊料粒子3以与电极端子2a进行扩散接合的状态赋予在突起状的电极端子2a上。 
接下来，如图3(f)所示，与半导体元件1的突起状电极1a相对而使得与电路基板2的电极端子2a对准位置之后，进行加热，一边施加上拉负荷，一边以低负荷将半导体元件1装载在电路基板2上。此时，虽然焊料成为液体状，但通过低负荷加压到彼此相邻的焊料粒子3不会形成一体化的程度。例如，在加热温度：250～260℃、加压时间：3～10秒、氮气气氛下进行了加压。另外，也可以在装载半导体元件1之前提供助焊剂或含有助焊剂成分的密封树脂。即使是难以熔融的微细焊料，也可通过助焊剂，提高焊料的浸润性，容易形成微小焊料接合体8。这里，虽然由于以低负荷进行装载，从而导致半导体元件1和电路基板2的平行度变差，但是，由于微小焊料接合体8的部分像图3(f)那样伸长成鼓状而进行接合，因此，能吸收平行度的恶化。 
通过截面研磨，对利用本实施方式2的制造方法制作的半导体装置进行截面分析，其结果能确认，在位于最外围的突起状电极1a、电极端子2a，半导体元件1与电路基板2的间隔离得最远，焊料接合体3c由三个微小焊料接合体8形成，并确认多层布线层1c所包含的脆弱的低介电常数绝缘膜也没有发生剥离和龟裂。而且，投入到温度循环试验(1个循环：-45℃、85℃各5分钟)的结果是，即使是1000cyc(循环)，也能确保稳定的连接电阻。 
这样，在对电路基板2的电极侧而不是对半导体元件1的电极侧赋予焊料粒子3的情况下，处于半导体元件1与电路基板2的间隔离得最远的位置的焊料接合部3c也利用两个以上的微小焊料接合体8形成，从而能减小脆弱的低介电常数绝缘膜受到的应力，确保高连接可靠性。 
(实施方式3) 
图4(a)～图4(i)是示意性表示本发明的实施方式3中的半导体装置的制造方法的剖视图。对于与图1及图2相同的结构部分，使用相同的标号。 
利用图4，在下面说明本实施方式3的半导体装置的制造方法。 
首先，如图4(a)所示，在晶圆形态、且由硅形成的半导体元件1的由Al形成的电极端子1b上，利用化学镀工艺形成由Ni-P/Au形成的突起状电极1a。 
另一方面，利用喷雾器或撒布机、刮条涂布机(bar coater)、旋涂机等手 段，在例如由PET或PEN形成的基材6的整个表面上涂布粘接层5，使焊料粒子3以均匀分散的方式附着于其上。例如，作为焊料粒子3，可使用组成为Sn3.5Ag8.0In0.5Bi、粒子直径为0.002～0.006mm的粒子。 
接下来，如图4(b)所示，对基材6的附着有焊料粒子3的面和半导体元件1的突起状电极1a的面彼此进行加热、加压，将其粘贴。这里，焊料粒子3局部熔融，与突起状电极1a进行扩散接合，且在沿平面方向不引起焊料桥接而保留粒子形状那样的温度、时间条件下进行加热加压。 
另外，粘接层5优选使用具有将焊料粒子3保持于基材6的功能、去除焊料氧化皮膜的功能、以及脱模功能的材料，但并不限于此。虽然未图示，但也可以进一步在基材6上提供助焊剂、脱模材料等材料。 
接下来，如图4(c)所示，一边加热，一边将基材6从半导体元件1剥离。通过该工序，存在于突起状电极1a之间的焊料粒子3保持附着于基材6侧而从半导体元件1上去除，焊料粒子3以与突起状电极1a进行扩散接合的状态赋予在突起状电极1a上。 
接下来，通过与图4(a)～图4(c)所示的半导体元件1中的工序相同的图4(e)～图4(g)的工序，对于晶圆形态、且由硅形成的电路基板2，焊料粒子3也以与电极端子2a进行扩散接合的状态赋予在电路基板2的电极端子2a上。 
接下来，如图4(d)及图4(h)所示，通过刀片切割、激光切割工艺，将半导体元件1及电路基板2分别形成一个个单片。 
接下来，如图4(i)所示，与半导体元件1的突起状电极1a相对而使得与电路基板2的电极端子2a对准位置之后，进行加热，一边施加上拉负荷，一边以低负荷将半导体元件1装载在电路基板2上。例如，在加热温度：210～230℃、加压时间：2～9秒、氮气气氛下进行了加压。 
另外，也可以在装载半导体元件1之前提供助焊剂或含有助焊剂成分的密封树脂。即使是难以熔融的微细焊料，也可通过助焊剂，提高焊料的浸润性，容易形成微小焊料接合体8。 
这里，虽然由于以低负荷进行装载，从而导致半导体元件1和电路基板2的平行度变差，但是，由于微小焊料接合体8的部分像图4(i)那样伸长成鼓状而进行接合，因此，能吸收平行度的恶化。 
通过截面研磨，对利用本实施方式3的制造方法制作的半导体装置进行截面分析，其结果能确认，在位于最外围的突起状电极1a、电极端子2a，半导体元件1与电路基板2的间隔离得最远，焊料接合体3c由两个微小焊料接合体8形成，并确认脆弱的低介电常数绝缘膜也没有发生剥离和龟裂。而且，投入到温度循环试验(1个循环：-55℃、125℃各5分钟)的结果是，即使是1000cyc(循环)，也能确保稳定的连接电阻。 
这样，在对半导体元件1的突起状电极1a和电路基板2的电极端子2a的两侧赋予焊料粒子3的情况下，处于半导体元件1与电路基板2的间隔离得最远的位置的焊料接合部3c利用两个以上的微小焊料接合体8形成，并且，由于微细焊料接合体8的高度变高，从而起到缓和在温度循环试验中受到的剪切方向的应力的效果，因此，能更减小脆弱的低介电常数绝缘膜受到的应力，确保高连接可靠性。 
此外，图5(a)及图5(b)是示意性表示本实施方式3中的焊料粒子附着基材的俯视图，图5(c)是示意性表示本实施方式3中的半导体装置的剖视图。 
在图5(a)中，微细的焊料小粒子3a分散配置在整个表面涂布有粘接层5的基材6a上。在图5(b)中，微细的焊料大粒子3b分散配置在整个表面涂布有粘接层5的基材6b上。这里，焊料小粒子3a的粒子直径小于焊料大粒子3b的粒子直径，优选是在焊料大粒子3b的粒子直径的1/2以下。此外，相互的焊料小粒子3a的中心之间的间隔的距离(间距)小于相互的焊料大粒子3b的中心之间的间隔的距离(间距)。 
在图5(c)中，对半导体元件1使用附着有焊料大粒子3b的基材6b，对电路基板2使用附着有焊料小粒子3a的基材6a，通过上述制造方法，使微细焊料粒子与各自的突起状电极1a、电极端子2a进行扩散接合。通过该工序，对于半导体元件1，较大的焊料大粒子3b与电极进行扩散接合，对于电路基板2，较小的焊料小粒子3a与电极进行扩散接合。 
然后，在将半导体元件1安装于电路基板2的工序(图4(i))中，由于以电路基板2的电极端子2a上的焊料小粒子3a进入半导体元件1的突起状电极1a上的焊料大粒子3b的间隙的形态进行装载，进行啮合，因此，即使在加热中电路基板2的翘曲变大，也能抑制半导体元件1与电路基板2在平面方向的 位置偏移，并形成上述微小焊料接合体8。 
另外，也可以对半导体元件1赋予焊料小粒子3a，对电路基板赋予焊料大粒子3b。 
此外，图6(a)及图6(b)是示意性表示本实施方式3中的焊料粒子附着基材的其他结构的焊料粒子配置的俯视图，图6(c)是示意性表示使用了图6(a)及图6(b)的焊料粒子附着基材6c及6d时的将半导体元件1安装于电路基板2的工序的剖视图。 
在图6(a)中，微细的焊料小粒子3a分散配置在整个表面涂布了电路基板2用的粘接层5的基材6c上，在图6(b)中，微细的焊料大粒子3b分散配置在整个表面涂布了半导体元件1用的粘接层5的基材6d上。这里，焊料小粒子3a、焊料大粒子3b均以同一间距E(图6(a)及图6(b)中用E表示的焊料粒子的各中心的间隔的距离)进行排列。此外，焊料大粒子3b的直径F为焊料小粒子3a的相邻粒子之间的间隔f以下。 
另外，也可以将焊料小粒子3a配置于半导体元件1的突起状电极1a，将焊料大粒子3b配置于电路基板2的电极端子2a。 
然后，若实施与上述相同的工序，则在将半导体元件1安装于电路基板2的工序中，如图6(c)所示，以电路基板2的电极端子2a上的焊料小粒子3a进入半导体元件1的突起状电极1a上的焊料大粒子3b的间隙的形态进行装载。因而，由于焊料大粒子3b与焊料小粒子3a能交替配置，因此，即使加热中电路基板2等的翘曲变大，半导体元件1与电路基板2在平面方向的位置偏移变大，也可通过间隔变窄的焊料大粒子3b和焊料小粒子3a来形成微小焊料接合体8。由此，通过两个以上的微小焊料接合体8，能将一组半导体元件1的突起状电极1a和电路基板2的电极端子2a进行电连接。 
在以上的各实施方式中，虽然举例示出半导体元件1作为电子元器件进行了说明，但并不限于此。在使用电极端子之间的间距较窄的电容器、线圈、电阻等无源元器件的情况下，也可得到相同的效果。此外，半导体元件虽然举例示出晶圆形态进行了说明，但也并不限于此。即使将半导体元件以形成一个个单片的状态制造成长方形或正方形，也可得到相同的效果。 
此外，在各实施方式中，虽然通过利用焊料粒子3在一个电极上形成多 个微小焊料接合体，但只要能在一个电极上形成多个微小焊料接合体，也可以使用粒子状以外的形状的焊料。例如，即使将微小带状的焊料以条状配置在电极上，来代替将焊料粒子3赋予在电极上，也可得到相同的效果。 
根据本发明，由于柔软且易于伸长的微小焊料接合体受到半导体装置的转角电极的热应力集中的作用，因此，起到如下效果：位于电极正下方的脆弱的低介电常数绝缘膜受到的热应力降低，能防止脆弱的低介电常数绝缘膜产生剥离和龟裂，能确保高连接可靠性。 
根据本发明，即使对于窄间距的连接，也能实现高可靠性，在对朝窄间距化发展的半导体元件、具有由低介电常数材料等形成的层间绝缘膜的半导体元件等进行安装的安装领域特别有用。 
工业上的实用性 
本发明所涉及的半导体装置以及半导体装置的制造方法在具有脆弱的膜的半导体元件中，具有能以简易的结构确保高连接可靠性的效果，在对朝窄间距化发展的半导体元件、具有由低介电常数材料等形成的层间绝缘膜的半导体元件等进行安装的安装领域特别有用。 
标号说明 
1、11、15  半导体元件 
1a  突起状电极 
1b、2a  电极端子 
1c  多层布线层 
2、12  电路基板 
3  焊料粒子 
3a  焊料小粒子 
3b  焊料大粒子 
3c  焊料接合部 
4  金属模 
5  粘接层 
6、6a、6b、6c、6d  基材 
7  合金层 
8  微小焊料接合体 
11a、12a  电极 
13  焊料 
14  低介电常数绝缘膜 

Claims (5)

1.一种半导体装置的制造方法，其特征在于，
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的第一焊料粒子的工序；对电路基板的多个电极的至少一个电极赋予两个以上的第二焊料粒子的工序；将所述电子元器件的电极与所述电路基板的电极相对配置的工序；进行如下所述抵接中的至少一种抵接的工序：使所述第一焊料粒子与所述电路基板的电极相抵接、使所述第二焊料粒子与所述电子元器件的电极相抵接、和使所述第一焊料粒子与所述第二焊料粒子相抵接；以及加热所述第一焊料粒子和所述第二焊料粒子的工序，
对于所述相对配置的至少一个电极组，所述电路基板的电极和所述电子元器件的电极、通过所述第一焊料粒子及所述第二焊料粒子熔融生成的两个以上的焊料接合体来进行电连接，
赋予所述电子元器件的电极表面的第一焊料粒子、和赋予所述电路基板的电极表面的第二焊料粒子相比，两者的粒子间隔不同，
在彼此相对配置的所述电路基板的电极和所述电子元器件的电极之间，配置有分离的2个以上的微小焊料接合体。
2.一种半导体装置的制造方法，其特征在于，
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的第一焊料粒子的工序；对电路基板的多个电极的至少一个电极赋予两个以上的第二焊料粒子的工序；将所述电子元器件的电极与所述电路基板的电极相对配置的工序；进行如下所述抵接中的至少一种抵接的工序：使所述第一焊料粒子与所述电路基板的电极相抵接、使所述第二焊料粒子与所述电子元器件的电极相抵接、和使所述第一焊料粒子与所述第二焊料粒子相抵接；以及加热所述第一焊料粒子和所述第二焊料粒子的工序，
对于所述相对配置的至少一个电极组，所述电路基板的电极和所述电子元器件的电极、通过所述第一焊料粒子及所述第二焊料粒子熔融生成的两个以上的焊料接合体来进行电连接，
赋予所述电子元器件的电极表面的第一焊料粒子、和赋予所述电路基板的电极表面的第二焊料粒子相比，两者的粒子直径不同，
在彼此相对配置的所述电路基板的电极和所述电子元器件的电极之间，配置有分离的2个以上的微小焊料接合体。
3.一种半导体装置的制造方法，其特征在于，
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的第一焊料粒子的工序；对电路基板的多个电极的至少一个电极赋予两个以上的第二焊料粒子的工序；将所述电子元器件的电极与所述电路基板的电极相对配置的工序；进行如下所述抵接中的至少一种抵接的工序：使所述第一焊料粒子与所述电路基板的电极相抵接、使所述第二焊料粒子与所述电子元器件的电极相抵接、和使所述第一焊料粒子与所述第二焊料粒子相抵接；以及加热所述第一焊料粒子和所述第二焊料粒子的工序，
对于所述相对配置的至少一个电极组，所述电路基板的电极和所述电子元器件的电极、通过所述第一焊料粒子及所述第二焊料粒子熔融生成的两个以上的焊料接合体来进行电连接，
赋予所述电子元器件的电极表面的第一焊料粒子的粒子间隔大于赋予所述电路基板的电极表面的第二焊料粒子的粒子直径，
在彼此相对配置的所述电路基板的电极和所述电子元器件的电极之间，配置有分离的2个以上的微小焊料接合体。
4.一种半导体装置的制造方法，其特征在于，
包括：对电子元器件的多个电极的至少一个电极赋予两个以上的第一焊料粒子的工序；对电路基板的多个电极的至少一个电极赋予两个以上的第二焊料粒子的工序；将所述电子元器件的电极与所述电路基板的电极相对配置的工序；进行如下所述抵接中的至少一种抵接的工序：使所述第一焊料粒子与所述电路基板的电极相抵接、使所述第二焊料粒子与所述电子元器件的电极相抵接、和使所述第一焊料粒子与所述第二焊料粒子相抵接；以及加热所述第一焊料粒子和所述第二焊料粒子的工序，
对于所述相对配置的至少一个电极组，所述电路基板的电极和所述电子元器件的电极、通过所述第一焊料粒子及所述第二焊料粒子熔融生成的两个以上的焊料接合体来进行电连接，
赋予所述电路基板的电极表面的第二焊料粒子的粒子间隔大于赋予所述电子元器件的电极表面的第一焊料粒子的粒子直径，
在彼此相对配置的所述电路基板的电极和所述电子元器件的电极之间，配置有分离的2个以上的微小焊料接合体。
5.如权利要求1至4中任一项所述的半导体装置的制造方法，其特征在于，
所述微小焊料接合体处于伸长成鼓状的状态。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103959451B (zh) * 2012-01-17 2016-12-21 松下知识产权经营株式会社 半导体装置制造方法以及半导体装置
JP2013183094A (ja) * 2012-03-02 2013-09-12 Nec Corp 電子部品の実装方法及び半導体装置
JP2013214557A (ja) 2012-03-30 2013-10-17 Olympus Corp 電極形成体、配線基板、および半導体装置
JP5923725B2 (ja) * 2012-05-15 2016-05-25 パナソニックＩｐマネジメント株式会社 電子部品の実装構造体
EP2747132B1 (en) * 2012-12-18 2018-11-21 IMEC vzw A method for transferring a graphene sheet to metal contact bumps of a substrate for use in semiconductor device package
JP6089732B2 (ja) * 2013-01-30 2017-03-08 日立金属株式会社 導電性部材の接続構造、導電性部材の接続方法、及び光モジュール
US8969191B2 (en) * 2013-07-16 2015-03-03 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for forming package structure
US9583470B2 (en) * 2013-12-19 2017-02-28 Intel Corporation Electronic device with solder pads including projections
US20150318259A1 (en) * 2014-05-02 2015-11-05 KyungOe Kim Integrated circuit packaging system with no-reflow connection and method of manufacture thereof
US11024608B2 (en) 2017-03-28 2021-06-01 X Display Company Technology Limited Structures and methods for electrical connection of micro-devices and substrates
FR3070550B1 (fr) * 2017-08-24 2020-07-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede d'assemblage de connecteurs electriques
JP2019176056A (ja) * 2018-03-29 2019-10-10 富士通株式会社 電子装置
JP7189672B2 (ja) * 2018-04-18 2022-12-14 新光電気工業株式会社 半導体装置及びその製造方法
US11101417B2 (en) * 2019-08-06 2021-08-24 X Display Company Technology Limited Structures and methods for electrically connecting printed components
US11502056B2 (en) * 2020-07-08 2022-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Joint structure in semiconductor package and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574846A (ja) * 1991-07-14 1993-03-26 Sony Chem Corp 電気的接続方法
CN1132931A (zh) * 1994-12-30 1996-10-09 卡西欧计算机公司 连接一个电子元件的端子到另一个电子元件的端子的方法
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
CN101138078A (zh) * 2005-03-09 2008-03-05 松下电器产业株式会社 金属粒子分散组合物以及使用了它的倒装片安装方法及隆起焊盘形成方法
CN101276796A (zh) * 2006-09-29 2008-10-01 英特尔公司 纳米管增强的焊料帽、组成方法及其芯片封装和系统
CN101416568A (zh) * 2006-04-03 2009-04-22 松下电器产业株式会社 部件接合方法和部件接合结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0997791A (ja) * 1995-09-27 1997-04-08 Internatl Business Mach Corp <Ibm> バンプ構造、バンプの形成方法、実装接続体
US6624522B2 (en) * 2000-04-04 2003-09-23 International Rectifier Corporation Chip scale surface mounted device and process of manufacture
US7098072B2 (en) * 2002-03-01 2006-08-29 Agng, Llc Fluxless assembly of chip size semiconductor packages
JP2003282617A (ja) 2002-03-25 2003-10-03 Citizen Watch Co Ltd 半導体装置およびその製造方法
US7315081B2 (en) * 2003-10-24 2008-01-01 International Rectifier Corporation Semiconductor device package utilizing proud interconnect material
CN100533701C (zh) * 2005-03-16 2009-08-26 松下电器产业株式会社 使用了导电性粒子的倒装片安装方法
WO2006103948A1 (ja) * 2005-03-29 2006-10-05 Matsushita Electric Industrial Co., Ltd. フリップチップ実装方法およびバンプ形成方法
US20090085227A1 (en) * 2005-05-17 2009-04-02 Matsushita Electric Industrial Co., Ltd. Flip-chip mounting body and flip-chip mounting method
KR101208028B1 (ko) * 2009-06-22 2012-12-04 한국전자통신연구원 반도체 패키지의 제조 방법 및 이에 의해 제조된 반도체 패키지

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0574846A (ja) * 1991-07-14 1993-03-26 Sony Chem Corp 電気的接続方法
CN1132931A (zh) * 1994-12-30 1996-10-09 卡西欧计算机公司 连接一个电子元件的端子到另一个电子元件的端子的方法
CN1498417A (zh) * 2000-09-19 2004-05-19 纳诺皮尔斯技术公司 用于在无线频率识别装置中装配元件和天线的方法
CN101138078A (zh) * 2005-03-09 2008-03-05 松下电器产业株式会社 金属粒子分散组合物以及使用了它的倒装片安装方法及隆起焊盘形成方法
CN101416568A (zh) * 2006-04-03 2009-04-22 松下电器产业株式会社 部件接合方法和部件接合结构
CN101276796A (zh) * 2006-09-29 2008-10-01 英特尔公司 纳米管增强的焊料帽、组成方法及其芯片封装和系统

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