TWI518808B - 半導體裝置及半導體裝置之製造方法 - Google Patents

半導體裝置及半導體裝置之製造方法 Download PDF

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Publication number
TWI518808B
TWI518808B TW100108737A TW100108737A TWI518808B TW I518808 B TWI518808 B TW I518808B TW 100108737 A TW100108737 A TW 100108737A TW 100108737 A TW100108737 A TW 100108737A TW I518808 B TWI518808 B TW I518808B
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Taiwan
Prior art keywords
solder
electrode
semiconductor device
solder particles
semiconductor element
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TW100108737A
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English (en)
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TW201201289A (en
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櫻井大輔
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松下電器產業股份有限公司
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Publication of TW201201289A publication Critical patent/TW201201289A/zh
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Description

半導體裝置及半導體裝置之製造方法 發明領域
本發明係有關於一種半導體裝置及半導體裝置之製造方法。
 發明背景
近年來，為促進半導體元件之高密度化及電極端子之多腳化之並立，而謀求半導體元件之電極端子之窄間距化、面積縮小化。
通常，在覆晶封裝中，於LSI等半導體元件之電極端子上形成銲點凸塊等突起電極，藉以倒裝使該半導體元件對封裝基板之連接端子壓接、加熱而以凸塊連接來封裝。
然而，由於窄間距化之發展顯著，故如習知，將電極端子配置於周圍之手段中，有在電極端子間產生短路，或因半導體元件與封裝基板之熱膨脹係數之差產生連接不良等的情形。是故，採取了藉將電極端子配置成區域狀，擴大電極端子間間距之方法，而近年來，在區域配置方面，窄間距化之發展亦顯著。
形成銲點凸塊之方法採取了將焊料以網版印刷、分配器或電解電鍍形成於電極上後，藉以迴焊爐加熱至焊料熔點以上，而形成突起狀銲點凸塊之工法。
然而，由於近年來，焊料接合部之間距更窄，半導體元件、基板電極間之間隙亦縮小，故在覆晶封裝時之加熱製程熔融之焊料變化，而因焊料之表面張力，引起諸銲點凸塊連結之錫橋不良產生之問題。
提出了令凸塊為2層結構之方法為因應此種要求者。
舉例言之，有將含有金屬粒子之絕緣性被覆膜形成為覆蓋由金或銅構成之突起電極表面(例如參照專利文獻1)。根據此種方法，絕緣性披覆膜或突起電極於覆晶時不熔融，而藉因注入至半導體元件與基板間之密封樹脂之硬化收縮引起之壓縮方向之力，可電性導通，而可防止錫橋產生，並可因應窄間距化。
然而，由於近年要求之電極間間距之窄間距化的要求非常嚴格，故如專利文獻1般，為金屬粒子與金屬電極不擴散接合，僅以接觸確保導通之連接形態時，當電極面積縮小時，介於電極間之導電粒子之數當然減少，連接電阻增高，而有信號之傳送損失增大之問題。
是故，採用了令凸塊為由下層金屬及上層金屬構成之2層結構，於由高熔點金屬構成之下層金屬上形成由焊料構成之上層金屬之方法(例如參照專利文獻2)。
第7圖係概念地顯示記載於專利文獻2之實施例之半導體裝置的截面圖。
於半導體元件11上形成由高熔點金屬構成之電極11a，並於電極11a上形成焊料13，半導體元件11之電極11a對位成與形成於電路基板12上之電極12a相對，從電路基板12上搭載半導體元件11後，加熱加壓，藉此，半導體元件11之電極11a與電路基板12之電極12a全面可以焊料13擴散接合。
根據此方法，可較由焊料一層構成之凸塊減少焊料量，覆晶封裝時之在平面方向之焊料浪費量減少，不僅可防止錫橋產生，而且焊料與基板電極擴散接合，故連接電阻低，亦不致損害信號之傳送損失。
先行技術文獻 專利文獻
專利文獻1　日本專利公開公報2003-282617號
專利文獻2　日本專利公開公報平9-97791號
然而，當對層間絕緣膜使用低介電常數膜之半導體元件，使用如上述之專利文獻2之半導體裝置製造技術時，在覆晶製程之焊料熔融後之冷卻過程中，有脆弱之低介電常數膜剝離或龜裂產生之問題。
為了因應近年要求之配線規則之細微化及高速信號處理，半導體元件之層間絕緣膜乃使用了低介電常數膜(所謂之Low-k膜或ULK(Ultra Low-k)膜等)。低介電常數膜自身為降低介電常數，而具有許多數nm空孔之多孔狀(多孔質)。
第8(a)圖及第8(b)圖係概念地顯示對使用此種低介電常數絕緣膜14之半導體元件15，使用專利文獻2之半導體裝置製造技術時，覆晶製程之焊料熔融後之冷卻過程之半導體裝置的截面圖。
使用專利文獻2之半導體裝置製造技術時，在覆晶製程之焊料熔融後之冷卻過程中，因半導體元件15與電路基板12之彈性率及線膨脹係數之差，產生往半導元件15相對於電路基板12翹曲之方向之熱應力。此熱應力集中於半導體元件15之角部份之焊料13之接合部。因此，該熱應力直接傳遞至半導體元件15之電極11a正下方，而如第8(a)圖及第8(b)圖所示，有使位於電極11a正下方之脆弱之低介電常數絕緣膜14之剝離或龜裂產生之問題。
又，在諸如產生急遽之溫度差之使用環境下，亦產生相同之熱應力集中，而有位於電極11a正下方之脆弱之低介電常數絕緣膜14之剝離或龜裂產生的問題。
本發明鑑於上述問題，其目的係提供在具有脆弱之膜之半導體元件，可確保高連接可靠度之簡易構造之半導體裝置及半導體裝置之製造方法。
為解決上述課題，第1本發明係一種電子零件之電極及與該電極相對向配置之電路基板之電極藉由焊料接合的半導體裝置，其特徵在於前述電子零件之電極及前述電路基板之電極相對向配置之至少1個電極組藉由2個以上之焊料接合體接合。
又，第2本發明係在第1本發明之半導體裝置中，前述電極組有複數個，具有最大之相對向間隔之前述電子零件之電極及前述電路基板之電極透過2個以上之前述焊料接合體接合。
又，第3本發明係一種半導體裝置之製造方法，其特徵在於具有以下步驟：對電子零件之複數個電極之至少1個電極供給2個以上之焊料粒子；將前述電子零件之電極與電路基板之電極相對向配置；使供給至前述電子零件之電極表面之焊料粒子與前述電路基板之電極抵接；及將前述焊料粒子加熱；該半導體裝置之製造方法並將前述電子零件之電極與前述電路基板之電極透過前述焊料粒子熔融而生成之2個以上之焊料接合體而電性連接。
又，第4本發明係一種半導體裝置之製造方法，其特徵在於具有以下步驟：對電路基板之複數個電極之至少1個電極供給2個以上之焊料粒子；將前述電路基板之電極與電子零件之電極相對向配置；使供給至前述電路基板之電極表面之焊料粒子與前述電子零件之電極抵接；及將前述焊料粒子加熱；該半導體裝置之製造方法並將前述電路基板之電極與前述電子零件之電極透過前述焊料粒子熔融而生成之2個以上之焊料接合體而電性連接。
又，第5本發明係一種半導體裝置之製造方法，其特徵在於具有以下步驟：對電子零件之複數個電極之至少1個電極供給2個以上之第1焊料粒子；對電路基板之複數個電極之至少1個電極供給2個以上之第2焊料粒子；將前述電子零件之電極與電路基板之電極相對向配置；進行前述第1焊料粒子與前述電路基板之電極之抵接、前述第2焊料粒子與前述電子零件之電極之抵接及前述第1焊料粒子與前述第2焊料粒子之抵接中的至少1個抵接；及將前述第1焊料粒子及前述第2焊料粒子加熱；又，關於前述相對向配置之至少1個電極組，係將前述電路基板之電極與前述電子零件之電極透過前述第1焊料粒子及前述第2焊料粒子熔融而生成之2個以上之焊料接合體而電性連接。
又，第6本發明係在第5本發明之半導體裝置之製造方法中，供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子的粒子間隔不同。
又，第7本發明係在第5本發明之半導體裝置之製造方法中，供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子的粒子徑不同。
又，第8本發明係在第6本發明之半導體裝置之製造方法中，供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子的粒子徑不同。
又，第9本發明係在第5~8任一本發明之半導體裝置之製造方法中，供給至前述電子零件之電極表面之第1焊料粒子的粒子間隔大於供給至前述電路基板之電極表面之第2焊料粒子的粒子徑。
又，第10本發明係在第5~8任一本發明之半導體裝置之製造方法中，供給至前述電路基板之電極表面之第2焊料粒子的粒子間隔大於供給至前述電子零件之電極表面之第1焊料粒子的粒子徑。
根據上述半導體裝置及其製造方法，在半導體裝置之具有脆弱之低介電常數膜之半導體元件之覆晶封裝中，可確保優異之連接可靠度。
根據本發明，可提供在具有脆弱之膜之半導體元件中，可確保高連接可靠度之簡易之構造的半導體裝置及半導體裝置之製造方法。
圖式簡單說明
第1圖係概念地顯示本發明第1實施形態之半導體裝置之截面圖。
第2(a)圖~第2(f)圖係概念地顯示本發明第1實施形態之半導體裝置之製造方法的截面圖。
第3(a)圖~第3(f)圖係概念地顯示本發明第2實施形態之半導體裝置之製造方法的截面圖。
第4(a)圖~第4(i)圖係概念地顯示本發明第3實施形態之半導體裝置之製造方法的截面圖。
第5(a)圖、第5(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之平面圖，第5(c)圖係概念地顯示本發明第3實施形態之半導體裝置之截面圖。
第6(a)圖、第6(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之另一結構之焊料粒子配置的平面圖，第6(c)圖係概念地顯示將使用本發明第3實施形態之另一結構之焊料粒子配置之焊料粒子附著基材時的半導體元件封裝於電路基板之製程之截面圖。
第7圖係概念地顯示習知半導體裝置之截面圖。
第8(a)圖、第8(b)圖係概念地顯示使用習知半導體裝置製造技術時之覆晶製程之焊料熔融後的冷卻過程之半導體裝置之截面圖。
 用以實施發明之形態
以下，參照圖式，詳細說明本發明之實施形態。
第1實施形態
第1圖係概念地顯示本發明第1實施形態之半導體裝置之截面圖。
於半導體元件1之電極面之內層設有具有由Cu或Al構成之細微配線層及脆弱之低介電常數絕緣膜(例如Low-k層或Ultra Low-k層)之多層配線層1c，且複數個電極端子1b以區域配置設於其最表面。舉例言之，電極端子1b由Al或Cu構成。於該電極端子1b上設由Ti/C、Ti/W/Cu等構成之晶種層，於其上設有由Ni/Au、Au、Cu等焊料可浸潤之金屬構成之突起狀電極1a。
另一方面，封裝有半導體元件1之電路基板2(例如由玻璃環氧多層基板、醯胺多層基板、矽構成)具有與半導體元件1之突起狀電極1a相對之配置之電極端子2a。電極端子2a由Ni/Au或Ni/Pd/Au等構成。
此外，半導體元件1相當於本發明之電子零件之一例。又，突起狀電極1a相當於本發明之電子零件之電極之一例，電極端子2a相當於本發明之電路基板之電極之一例。
半導體元件1之突起狀電極1a與電路基板2之電極端子2a藉焊料接合部3c以電性及機械性方式連接，焊料接合部3c與突起狀電極1a及焊料接合部3c與電極端子2a間引發固相擴散或固液擴散反應，於中間形成合金層7，而穩固地接合。
在此，半導體元件1與電路基板2之間隔(第1圖中之B)中最大之位置(第1圖中之A)之電極間之焊料接合部3c由2個微小焊料接合體8構成。
此外，微小焊料接合體8相當於本發明之焊料接合體之一例。
在半導體裝置製造時之焊料熔融製程之焊料熔融後的冷卻過程中，由於因半導體元件1與電路基板2之線膨脹係數之不同，在位於半導體元件1之最外圍之接合部份附近最易產生翹曲，故多為半導體元件1與電路基板2之間距最大之情形。
再者，在半導體元件1之面內，在位於最外圍之接合部份附近熱應力亦最大。如此在間隔最大之位置A，最承受熱應力，而藉以2個微小焊料接合體8連接，可以小於1個微小焊料接合體時之面積，與突起狀電極1a及電極端子2a連接，藉以該面積小之連接部份承受拉伸方向之力，對焊料部份之應力集中增加，應力集中點從具有脆弱之低介電常數絕緣膜之多層配線層1c移至焊料接合部3c。
然而，即使應力集中點移至焊料接合部3c，由於由2個微小焊料接合體8構成之焊料接合部3c之延伸率大，而與突起狀電極1a、電極端子2a穩定地接合，故焊料接合部3c在不破損下延伸，而可防止多層配線層1c之脆弱之低介電常數絕緣膜的剝離或龜裂之產生。
焊料之組成由SnAg、SnAgCu、SnZn、SnZnBi、SnPb、SnBi、SnAgBiIn、SnIn、In、Sn等構成，配合最大間隔A之大小，可從焊料延伸率自由地選擇材料。
舉例言之，若半導體元件1之電極端子1b之間隔為0.05mm時，突起狀電極1a之徑為0.020~0.035mm，高度為0.05~0.20mm，電路基板2之電極端子2a之徑為0.020~0.035mm，高度為0.05~0.10mm，微小焊料接合體8之徑為0.002~0.010mm，徑之延伸率為50%。
雖圖中未顯示，但亦可於半導體元件1與電路基板2之電極面間填充有密封樹脂。藉填充密封樹脂，可更提高可靠度。
第2(a)圖~第2(f)圖係概念地顯示本發明第1實施形態之半導體裝置之製造方法的截面圖。與第1圖相同之構成部份使用相同之標號。
使用第2圖，以下，說明本第1實施形態之半導體裝置之製造方法。
首先，如第2(a)圖所示，以濺鍍法或沉積於為晶圓形態之半導體元件1之電極面全面形成晶種層。接著，以電解電鍍工法，全面形成金屬膜。於形成感光光阻層，將電極端子1b之位置之突起狀電極1a之形成部份曝光後，使用剝離液，將感光光阻層剝離。藉此製程，可於電極端子1b上形成突起狀電極1a。晶種層使用了Ti/Cu，金屬膜使用了Ni/Au，但不限於此。此外，於形成晶種層前，於半導體元件1之電極面側形成有具有脆弱之低介電常數膜之多層配線層1c。
接著，如第2(b)圖所示，配合突起狀電極1a之位置，在挖空成大於突起狀電極1a之形狀之轉印用模具4中，以噴霧器或分配器等方法將黏著層5供給至模具4全面後，可將焊料粒子均一地提供至全面。
然後，如第2(c)圖所示，將模具4與半導體元件1之位置調整成半導體元件1之突起狀電極1a與設在對應於該突起狀電極1a之模具4之凹孔相對，進行加熱加壓。藉此，在焊料粒子3與突起狀電極1a熔融，且焊料粒子3保留粒子形狀之溫度、時間條件下，加熱加壓。此時，當使用細微之焊料粒子3時，氧化被覆膜所佔之面積大，易阻礙熔融，而可以保留粒子形狀之狀態擴散。舉例言之，於焊料粒子3之徑為0.002~0.008mm時，以模具4之溫度：210℃、加壓時間：10~50s，在大氣壓下加壓。
接著，如第2(d)圖所示，藉將模具4從半導體元件1剝除，而形成有以粒子形狀供給了焊料粒子3之突起狀電極1a。之後，如第2(e)圖所示，以刀片切割或雷射切割等手段，將半導體元件1單片化。
然後，如第2(f)圖所示，與電路基板2之電極端子2a對位成與半導體元件1之突起狀電極1a相對後，加熱，一面施加舉升載重，一面以低載重將半導體元件1搭載至電路基板2上。此時，焊料為液狀，而因低載重，相鄰之焊料粒子3加壓至不一體化之程度。舉例言之，以加熱溫度：220~240℃、加壓時間：3~10秒加壓即可。此外，亦可於搭載半導體元件1前，供給助熔劑。即使在熔融不易之粒子形狀之細微焊料粒子3，藉助熔劑，焊料之浸潤性提高，而易形成細微之焊料接合部3c。
在此，藉在焊料為液狀之狀態，以低載重搭載，半導體元件1與電路基板2不保持平行而以傾斜之狀態裝入，半導體元件1與電路基板2之平行度惡化。然而，即使為半導體元件1之端部之與電路基板2之距離最大之處的諸電極，由於微小焊料接合體8之部份如第2(f)圖，延伸成鼓狀而接合，故可吸收平行度之惡化。
在將第2(f)圖之半導體元件1封裝於電路基板2之際之焊料熔融製程之焊料熔融後的冷卻過程中，若在焊料之熔點以上，液體之焊料粒子3延伸，在焊料之凝固點以下時，焊料同時凝固，而可維持其形狀。由於當進一步冷卻時，焊料接合部3c之間隔便可因半導體元件1與電路基板2之線膨脹係數之差而擴大，故固體之焊料接合部3c在彈性區域內延伸，半導體裝置完成。
將如第2(f)圖所示之焊料接合部3c般延伸成鼓狀之細微焊料定義為「微小焊料接合體8」。半導體元件1之突起狀電極1a與電路基板2之電極端子2a以2個上之微小焊料接合體8電性連接。在此，半導體元件1與電路基板2之距離最小之處之諸電極可以複數個微小焊料接合體8電性連接，亦可以與習知相同之1個焊料接合體電性連接。
將使用本第1實施形態之製造方法而製作之半導體裝置以截面研磨來解析截面，結果，確認位於最外圍之焊料接合部3c由2個微小焊料接合體8構成，並確認了多層配線層1c所具有之脆弱之低介電常數絕緣膜也未產生剝離、龜裂。再者，投入至溫度循環實驗(1循環：-45℃、85℃、各5分鐘)，結果，在1000cyc(循環)亦可確保穩定之連接電阻
由於使用本第1實施形態而製造之半導體裝置對使用環境下之溫度變化，在焊料接合部3c之彈性區內，微小焊料接合體8伸縮，故在焊料接合部3c之部份，吸收緩和熱應力，應力可不傳遞至電極正下方，如此，可確保使用時之穩定之連接電阻。
如此，藉位於半導體元件1與電路基板2之間隔最遠之位置的焊料接合部3c以2個微小焊料接合體8構成，可減低脆弱之低介電常數絕緣膜承受之應力，而可確保高連接可靠度。
第2實施形態
第3(a)圖~第3(f)圖係概念地顯示本發明第2實施形態之半導體裝置之製造方法的截面圖。於與第1圖及第2圖相同之結構部份使用相同之標號。
使用第3圖，以下說明本第2實施形態之半導體裝置之製造方法。
首先，如第3(a)圖所示，以濺鍍法或沉積於為晶圓形態之半導體元件1之電極面全面形成晶種層。接著，以電解電鍍工法，全面形成金屬膜。於形成感光光阻層，將電極端子1b之位置之突起狀電極1a之形成部份曝光後，使用剝離液，將感光光阻層剝離。藉此製程，可於電極端子1b上形成突起狀電極1a。晶種層使用了Ti/Cu，金屬膜使用了Cu，但不限於此。此外，於半導體元件1之電極面側形成有具有脆弱之低介電常數絕緣膜之多層配線層1c。
接著，如第3(b)圖所示，將半導體元件1以切割刀片或雷射加工將半導體元件1單片化。
然後，如第3(c)圖所示，以無電解電鍍工法於由玻璃環氧多層基板構成之電路基板2形成突起狀電極端子2a。舉例言之，電極端子2a之組成選定Ni/Au、Ni/Pd/Au、Cu等焊料之浸潤性佳之材料。之後，為將焊料粒子3均一地供給至全面，而以噴霧器或分配器等方法將黏著層5供應至電路基板2全面。
接著，如第3(d)圖所示，以迴焊爐等加熱機構，將焊料粒子3已均一地供給至全面之電路基板2加熱，焊料粒子3與電極端子2a熔融，且不致在平面方向引起錫橋，而在可保留粒子形狀之溫度、時間、氣體環境下加熱。在此，由於當使用細微之焊料粒子3時，氧化被覆膜所佔之面積大，易阻礙熔融，故不致在相鄰之諸端子引起錫橋，而可以保留粒子形狀之狀態擴散。舉例言之，焊料於使用Sn3.0Ag0.5Cu之焊料粒子徑為0.003~0.008mm時，以溫度：225℃、加壓時間：3~8s，在甲酸氣體環境下加壓。
然後，如第3(e)圖所示，將電路基板2浸漬於洗淨液，施加超音波來洗淨。藉此製程，去除存在於電極端子2a間之焊料粒子3，焊料粒子3以與電極端子2a擴散接合之狀態供給至突起狀電極端子2a上，。
接著，如第3(f)圖所示，與電路基板2之電極端子2a對位成與半導體元件1之突起狀電極1a相對後，加熱，一面施加提升載重，一面以低載重將半導體元件1搭載至電路基板2上。此時，焊料為液狀，而因低載重，相鄰之焊料粒子3加壓至不一體化之程度。舉例言之，以加熱溫度：250~260℃、加壓時間：3~10秒，在氮氣環境下加壓。此外，亦可於搭載半導體元件1前，供給助熔劑或含有助熔劑成份之密封樹脂。即使在熔融不易之粒子形狀之細微焊料，藉助熔劑，焊料之浸潤性提高，而易形成微小焊料接合體8。在此，藉以低載重搭載，半導體元件1與電路基板2之平行度惡化，但由於微小焊料接合體8之部份如第3(f)圖，延伸成鼓狀而接合，故可吸收平行度之惡化。
將使用本第2實施形態之製造方法而製作之半導體裝置以截面研磨來解析截面，結果，確認在位於最外圍之突起狀電極、電極端子2a，半導體元件1與電路基板2之間隔最遠，且焊料接合部3c由3個微小焊料接合體8構成，並確認了多層配線層1c所具有之脆弱之低介電常數絕緣膜也未產生剝離、龜裂。再者，投入至溫度循環實驗(1循環：-45℃、85℃、各5分鐘)，結果，在1000cyc(循環)亦可確保穩定之連接電阻。
如此，即使不是將焊料粒子3供給至半導體元件1之電極側而是供給至電路基板2之電極側時，藉位於半導體元件1與電路基板2之間隔最遠之位置的焊料接合部3c以2個以上之微小焊料接合部8構成，可減低脆弱之低介電常數絕緣膜承受之應力，而可確保高連接可靠度。
第3實施形態
第4(a)圖~第4(i)圖係概念地顯示本發明第3實施形態之半導體裝置之製造方法的截面圖。於與第1圖及第2圖相同之結構部份附上相同之標號。
使用第4圖，以下，說明本第3實施形態之半導體裝置之製造方法。
首先，如第4(a)圖所示，於為晶圓形態，且由矽構成之半導體元件1之由Al構成之電極端子1b上使用無電解電鍍工法形成由Ni-P/Au構成之突起狀電極。
另一方面，以噴霧器、分配器、塗佈棒、旋轉塗佈機等手段將黏著層5塗佈於由PET或PEN構成之基材6全面，而使焊料粒子3附著成均等地分散於其上。舉例言之，焊料粒子3可使用組成為Sn3.5Ag8.0In0.5Bi，粒子徑為0.002~0.006mm之粒子。
接著，如第4(b)圖所示，一面將基材6之附著有焊料粒子3之面與半導體元件1之突起狀電極1a之面加熱加壓，一面貼附。在此，在焊料粒子3局部地熔融，與突起狀電極1a擴散接合，且不致在平面方向引起錫橋，而保留粒子形狀之溫度、時間條件下加熱加壓。
此外，黏著層5宜使用具有使焊料粒子3保持於基材6之功能、去除焊料氧化披覆膜之功能及脫模功能之材料，但不限於此。雖圖中未示，但亦可進一步將助熔劑或脫模材等材料供應至基材6上。
然後，如第4(c)圖所示，一面加熱，一面將基材6從半導體元件1剝離。藉此製程，存在於突起狀電極1a間之焊料粒子3直接以附著於基材6側之狀態從半導體元件1上去除，焊料粒子3可以與突起狀電極1a擴散接合之狀態供給至突起狀電極1a上。
之後，以與第4(a)圖~第4(c)圖所示之半導體元件1之製程相同的第4(e)圖~第4(g)圖之製程，在為晶圓形態，且由矽構成之電路基板2，亦將焊料粒子3以與電極端子2a擴散接合之狀態供給至電路基板2之電極端子2a上。
然後，如第4(d)圖及第4(h)圖所示，將半導體元件1及電路基板2分別以刀片切割或雷射切割工法單片化。
接著，如第4(i)圖所示，與電路基板2之電極端子2a對位成與半導體元件1之突起狀電極1a相對後，加熱，一面施加提升載重，一面以低載重將半導體元件1搭載至電路基板2上。舉例言之，以加熱溫度：210~230℃、加壓時間：2~9秒，在氮氣環境下加壓。
此外，亦可於搭載半導體元件1前，供給助熔劑或含有助熔劑成份之密封樹脂。即使在熔融不易之細微焊料，藉助熔劑，焊料之浸潤性亦可提高，而易形成微小焊料接合體8。
在此，藉以低載重搭載，半導體元件1與電路基板2之平行度惡化，但由於微小焊料接合體8之部份如第4(i)圖，延伸成鼓狀而接合，故可吸收平行度之惡化。
將使用本第3實施形態之製造方法而製作之半導體裝置以截面研磨來解析截面，結果，確認在位於最外圍之突起狀電極1a、電極端子2a，半導體元件1與電路基板2之間隔最遠，且焊料接合部3c由2個微小焊料接合體8構成，並確認了脆弱之低介電常數絕緣膜也未產生剝離、龜裂。再者，投入至溫度循環實驗(1循環：-55℃、125℃、各5分鐘)，結果，在1000cyc(循環)亦可確保穩定之連接電阻。
如此，將焊料粒子3供給至半導體元件1之突起狀電極1a與電路基板2之電極端子2a兩側時，由於因位於半導體元件1與電路基板2之間隔最遠之位置的焊料接合部3c以2個以上之微小焊料接合部8構成，並且，細微焊料接合體8之高度增高，而發揮緩和在溫度循環試驗承受之方向之應力的效果，而可確保高連接可靠度。
又，第5(a)圖及第5(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之平面圖，第5(c)圖係概念地顯示本發明第3實施形態之半導體裝置之截面圖。
在第5(a)圖中，細微之焊料小粒子3a分散配置於全面塗佈有黏著層5之基材6a上。在第5(b)圖中，細微之焊料大粒子3b分散配置於全面塗佈有黏著層5之基材6b上。在此，焊料小粒子3a之粒子徑宜小於焊料大粒子3b之粒子徑，為焊料大粒子3b之粒子徑之1/2以下。又，兩個彼此相鄰之焊料小粒子3a之中心的間隔距離(間距)小於兩個彼此相鄰之焊料大粒子3b之中心的間隔距離(間距)。
在第5(c)圖中，半導體元件1使用附著有焊料大粒子3b之基材6b，電路基板2使用附著有焊料小粒子3a之基材6a，以前述之製造方法，使細微焊料粒子擴散接合至各突起狀電極1a、電極端子2a。藉此製程，在半導體元件1，大之焊料大粒子3b擴散接合至電極，在電路基板2，小之焊料小粒子3a擴散接合至電極。
然後，在將半導體元件1封裝於電路基板2之製程(第4(i)圖)中，電路基板2之電極端子2a上之焊料小粒子3a以進入至半導體元件1之突起狀電極1a上之焊料大粒子3b之間隙之狀態搭載咬合，故即使加熱中，電路基板2之翹曲增大，也可一面抑制半導元件1與電路基板2之平面方向之位置偏移，一面形成前述微小焊料接合體8。
此外，亦可將焊料小粒子3a供給至半導體元件1，將焊料大粒子3b供給至電路基板。
又，第6(a)圖及第6(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之另一結構之焊料粒子配置的平面圖，第6(c)圖係概念地顯示將使用第6(a)圖及第6(b)圖之焊料粒子附著基材6c及6d時之半導體元件1封裝於電路基板2之製程的截面圖。
在第6(a)圖中，細微之焊料小粒子3a分散配置於全面塗佈有電路基板2用黏著層5之基材6c上，在第6(b)圖中，細微之焊料大粒子3b分散配置於全面塗佈有半導體元件1用黏著層5之基材6d上。在此，焊料小粒子3a、焊料大粒子3b皆以相同之間距E(在第6(a)圖及第6(b)圖中以E所示之焊料粒子之各中心之間隔距離)排列。又，焊料大粒子3b之徑F為焊料小粒子3a之相鄰之粒子間的間隔f以下。
此外，亦可於半導體元件1之突起狀電極1a配置焊料小粒子3a，於電路基板2之電極端子2a配置焊料大粒子3b。
然後，當施行與前述相同之步驟時，在將半導體元件1封裝於電路基板2之製程中，如第6(c)圖所示，以電路基板2之電極端子2a上之焊料小粒子3a進入至半導體元件1之突起狀電極1a上之焊料大粒子3b之間隙之狀態來搭載。因而，由於焊料大粒子3b與焊料小粒子3a可交互配置，故加熱中，即使電路基板2等之翹曲增大，半導體元件1與電路基板2之平面方向之位置偏移增大，也可以間隔縮小之焊料大粒子3b及焊料小粒子3a形成微小焊料接合體8。藉此，藉由2個以上之微小焊料接合體8，可將1組半導體元件1之突起狀電極1a與電路基板2之電極端子2a電性連接。
在以上之各實施形態中，電子零件例示了半導體元件1來說明，但不限於此。使用電極端間間隙狹小之電容器、線圈、電阻等被動零件時，亦可獲得同樣之效果。又，半導體元件例示了晶圓形態來說明，但亦不限於此。將半導體元件以單片化成長方形或正方形之狀態製造，亦可獲得同樣之效果。
又，在各實施形態中，藉使用焊料粒子3，使1個電極上形成複數個微小焊料接合體，只要可使1個電極上形成複數個微小焊料接合體，亦可使用粒子狀以外之形狀之焊料。舉例言之，將微小線狀之焊料於電極上配置成條紋狀取代將焊料粒子供給至電極上，亦可獲得同樣之效果。
根據本發明，由於柔軟，且易延伸之微小焊料接合體承受半導體裝置之角部位電極之熱應力集中，故可減低位於電極正下方之脆弱之低介電常數絕緣膜承受的熱應力，而可防止脆弱之低介電常數絕緣膜之剝離或龜裂，而可發揮可確保高連接可靠度之效果。
根據本發明，在窄間距之連接，亦可實現高可靠度，而在封裝發展窄間距化之半導體元件或具有由低介電常數材料等構成之層間絕緣膜之半導體元件等的封裝領域特別有用。
產業上之可利用性
本發明之半導體裝置及半導體裝置之製造方法在具有脆弱之膜之半導體元件中，具有可以簡易之構造確保高連接可靠度之效果，而在封裝發展窄間距化之半導體元件或具有由低介電常數材料等構成之層間絕緣膜之半導體元件等的封裝領域特別有用。
1，11，15．．．半導體元件
1a．．．突起狀電極
1b，2a．．．電極端子
1c．．．多層配線層
2，12．．．電路基板
3．．．焊料粒子
3a．．．焊料小粒子
3b．．．焊料大粒子
3c．．．焊粒接合部
4．．．模具
5．．．黏著層
6，6a-6d．．．基材
7．．．合金層
8．．．微小焊料接合體
11a，12a．．．電極
13．．．焊料
14．．．低介電常數絕緣膜
第1圖係概念地顯示本發明第1實施形態之半導體裝置之截面圖。
第2(a)圖~第2(f)圖係概念地顯示本發明第1實施形態之半導體裝置之製造方法的截面圖。
第3(a)圖~第3(f)圖係概念地顯示本發明第2實施形態之半導體裝置之製造方法的截面圖。
第4(a)圖~第4(i)圖係概念地顯示本發明第3實施形態之半導體裝置之製造方法的截面圖。
第5(a)圖、第5(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之平面圖，第5(c)圖係概念地顯示本發明第3實施形態之半導體裝置之截面圖。
第6(a)圖、第6(b)圖係概念地顯示本發明第3實施形態之焊料粒子附著基材之另一結構之焊料粒子配置的平面圖，第6(c)圖係概念地顯示將使用本發明第3實施形態之另一結構之焊料粒子配置之焊料粒子附著基材時的半導體元件封裝於電路基板之製程之截面圖。
第7圖係概念地顯示習知半導體裝置之截面圖。
第8(a)圖、第8(b)圖係概念地顯示使用習知半導體裝置製造技術時之覆晶製程之焊料熔融後的冷卻過程之半導體裝置之截面圖。
1．．．半導體元件
1a．．．突起狀電極
1b，2a．．．電極端子
1c．．．多層配線層
2．．．電路基板
3．．．焊料粒子
3c．．．焊粒接合部
4．．．模具
5．．．黏著層
7．．．合金層
8．．．微小焊料接合體

Claims (6)

  1. 一種半導體裝置之製造方法，其特徵在於具有以下步驟：對電子零件之複數個電極之至少1個電極供給2個以上之第1焊料粒子；對電路基板之複數個電極之至少1個電極供給2個以上之第2焊料粒子；將前述電子零件之電極與前述電路基板之電極相對向配置；進行前述第1焊料粒子與前述電路基板之至少1個電極之抵接、前述第2焊料粒子與前述電子零件之至少一個電極之抵接及前述第1焊料粒子與前述第2焊料粒子之抵接中的至少1個抵接；及將前述第1焊料粒子及前述第2焊料粒子加熱；又，關於前述相對向配置之至少1個電極組，係將前述電路基板之至少1個電極與前述電子零件之至少1個電極透過前述第1焊料粒子及前述第2焊料粒子熔融而生成之2個以上且各個分開之焊料接合體而電性連接。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子的粒子間隔不同。
  3. 如申請專利範圍第1項之半導體裝置之製造方法，其中 供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子之粒子徑不同。
  4. 如申請專利範圍第2項之半導體裝置之製造方法，其中供給至前述電子零件之電極表面之第1焊料粒子與供給至前述電路基板之電極表面之第2焊料粒子之粒子徑不同。
  5. 如申請專利範圍第1~4項中任一項之半導體裝置之製造方法，其中供給至前述電子零件之電極表面之第1焊料粒子的粒子間隔大於供給至前述電路基板之電極表面之第2焊料粒子的粒子徑。
  6. 如申請專利範圍第1~4項中任一項之半導體裝置之製造方法，其中供給至前述電路基板之電極表面之第2焊料粒子的粒子間隔大於供給至前述電子零件之電極表面之第1焊料粒子的粒子徑。
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