JP2013214557A - 電極形成体、配線基板、および半導体装置 - Google Patents
電極形成体、配線基板、および半導体装置 Download PDFInfo
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- JP2013214557A JP2013214557A JP2012082930A JP2012082930A JP2013214557A JP 2013214557 A JP2013214557 A JP 2013214557A JP 2012082930 A JP2012082930 A JP 2012082930A JP 2012082930 A JP2012082930 A JP 2012082930A JP 2013214557 A JP2013214557 A JP 2013214557A
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- bump
- electrode
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- forming body
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- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 11
- 150000002739 metals Chemical class 0.000 claims description 8
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- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 239000000956 alloy Substances 0.000 claims description 6
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- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
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- 238000007740 vapor deposition Methods 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 7
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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Abstract
【解決手段】所定の厚さを有する基材10と、基材の厚さ方向の一方の面に形成された電極部20とを備える電極形成体1において、電極部20は、略円柱状に形成されて基材10上に突出する基礎バンプ21と、基礎バンプ21と金属結合するように基礎バンプと独立して形成された脆弱バンプ22とを有することを特徴とする。
【選択図】図2
Description
ここで、バンプの高さにバラつきがあると、まず高く形成されたバンプに荷重が集中することになり、当該バンプへのダメージが懸念される。このため、接合荷重の低減を図るために、バンプの上面を研削や化学機械研磨(CMP)等により平坦化することも検討されているが、数億個以上のバンプを均一にダメージなく平坦化することは容易ではなく、納期やコストの面でも問題がある。
また、前記基礎バンプは、金、銅、ニッケル、およびこれら金属の少なくとも一つを含む合金のいずれかで形成され、前記脆弱バンプは、金、銅、ニッケル、スズ、およびこれら金属の少なくとも一つを含む合金のいずれかで形成されてもよい。
また、前記脆弱バンプが形成される前記基礎バンプの面の表面粗さRaは、100ナノメートル以下であってもよい。
また、前記脆弱バンプは、メッキにより形成され、前記粒状の金属はメッキ核の成長により形成されてもよい。
また本発明の他の半導体装置は、電極部が形成された配線基板を少なくとも2枚接合して形成された半導体装置であって、前記配線基板の少なくとも一方は、本発明の配線基板または本発明の半導体装置における配線基板であることを特徴とする。
図1は、本実施形態の電極形成体1を示す斜視図である。電極形成体1は、板状またはシート状の基材10と、基材10の面上に形成された複数の電極部20とを備えている。
脆弱バンプの高さh1は、基礎バンプ形成時の高さバラつき(最小値と最大値との差分)以上に設定されるのが好ましい。このようにすると、後述する接合時に、基礎バンプの高さバラつきを好適に吸収して、電極部の接合の確実性を高めることができる。
まず、基材10上にレジスト層101を形成し、図3に示すように、電極部を形成するパターンに応じた複数の開口102をレジスト層101に形成する。開口102は、基材10上に形成され、シード層としても機能する電極パッド11の位置に合わせて形成する。
したがって、接触初期の大きい荷重により基材や電極部がダメージを受けることを好適に抑制することができる。
なお、上述の例のように、相手側の電極部が脆弱バンプを有さず、所定範囲の高さバラつきを有して形成されている場合は、理論上、接合時における電極部間の最大ギャップは、両者の高さバラつきの和となるため、脆弱バンプの高さをこの和以上の値にしておくことで、より確実に電極部どうしの接合を行うことができる。
本発明の配線基板、半導体装置等を単独または接合して構成する半導体装置の種類は特に限定されないが、例えば多数の画素を有する固体撮像装置等においては、非常に多数の電極が狭ピッチで形成される必要があるため、本発明を適用することにより得られるメリットが非常に大きく、本発明の構造を適用するのにきわめて好適である。
10 基材
20、20A、20B 電極部
21、21A 基礎バンプ
22、22A、22B 脆弱バンプ
31 配線基板
Claims (11)
- 所定の厚さを有する基材と、前記基材の厚さ方向の一方の面に形成された電極部とを備える電極形成体であって、
前記電極部は、略円柱状に形成されて前記基材上に突出する基礎バンプと、前記基礎バンプと金属結合するように前記基礎バンプと独立して形成された脆弱バンプと、を有する
ことを特徴とする電極形成体。 - 前記基材は、半導体または絶縁体で形成されていることを特徴とする請求項1に記載の電極形成体。
- 前記基礎バンプは、金、銅、ニッケル、およびこれら金属の少なくとも一つを含む合金のいずれかで形成され、
前記脆弱バンプは、金、銅、ニッケル、スズ、およびこれら金属の少なくとも一つを含む合金のいずれかで形成されていることを特徴とする請求項1または2に記載の電極形成体。 - 前記脆弱バンプが形成される前記基礎バンプの面の表面粗さRaは、100ナノメートル以下であることを特徴とする請求項1から3のいずれか一項に記載の電極形成体。
- 前記脆弱バンプは、粒状の金属で形成されていることを特徴とする請求項1から4のいずれか一項に記載の電極形成体。
- 前記脆弱バンプは、メッキにより形成され、前記粒状の金属はメッキ核の成長により形成されていることを特徴とする請求項5に記載の電極形成体。
- 前記脆弱バンプは、メッキ、蒸着、スパッタリング、および印刷のいずれかにより形成されていることを特徴とする請求項1から4のいずれか一項に記載の電極形成体。
- 請求項2に記載の電極形成体と、
前記基材に設けられ、前記電極部と接続された配線と、
を備えることを特徴とする配線基板。 - 請求項8に記載の配線基板と、
前記基材に設けられた半導体素子と、
を備えることを特徴とする半導体装置。 - 請求項8に記載の配線基板と、
前記基材に設けられた半導体チップまたは半導体パッケージと、
を備えることを特徴とする半導体装置。 - 電極部が形成された配線基板を少なくとも2枚接合して形成された半導体装置であって、前記配線基板の少なくとも一方は、請求項8に記載の配線基板または請求項9または10に記載の半導体装置における配線基板であることを特徴とする半導体装置。
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JP2012082930A JP2013214557A (ja) | 2012-03-30 | 2012-03-30 | 電極形成体、配線基板、および半導体装置 |
CN2013100961875A CN103367292A (zh) | 2012-03-30 | 2013-03-25 | 电极形成体、布线基板以及半导体装置 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01238148A (ja) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | 半導体装置 |
JP2001267371A (ja) * | 2000-03-21 | 2001-09-28 | Hitachi Ltd | 液晶表示装置 |
JP2007109786A (ja) * | 2005-10-12 | 2007-04-26 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置の製造装置 |
JP2009302511A (ja) * | 2008-05-12 | 2009-12-24 | Tanaka Holdings Kk | バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法 |
JP2011210773A (ja) * | 2010-03-29 | 2011-10-20 | Panasonic Corp | 半導体装置の構造および製造方法 |
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US8044511B2 (en) * | 2004-07-29 | 2011-10-25 | Kyocera Corporation | Function element and function element mounting structure |
JP2006261569A (ja) * | 2005-03-18 | 2006-09-28 | Dowa Mining Co Ltd | サブマウントおよびその製造方法 |
US8318596B2 (en) * | 2010-02-11 | 2012-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Pillar structure having a non-planar surface for semiconductor devices |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01238148A (ja) * | 1988-03-18 | 1989-09-22 | Fuji Electric Co Ltd | 半導体装置 |
JP2001267371A (ja) * | 2000-03-21 | 2001-09-28 | Hitachi Ltd | 液晶表示装置 |
JP2007109786A (ja) * | 2005-10-12 | 2007-04-26 | Nec Electronics Corp | 半導体装置の製造方法および半導体装置の製造装置 |
JP2009302511A (ja) * | 2008-05-12 | 2009-12-24 | Tanaka Holdings Kk | バンプ及び該バンプの形成方法並びに該バンプが形成された基板の実装方法 |
JP2011210773A (ja) * | 2010-03-29 | 2011-10-20 | Panasonic Corp | 半導体装置の構造および製造方法 |
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