CN102208384A - 半导体结构及半导体装置的形成方法 - Google Patents

半导体结构及半导体装置的形成方法 Download PDF

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Publication number
CN102208384A
CN102208384A CN2010102246934A CN201010224693A CN102208384A CN 102208384 A CN102208384 A CN 102208384A CN 2010102246934 A CN2010102246934 A CN 2010102246934A CN 201010224693 A CN201010224693 A CN 201010224693A CN 102208384 A CN102208384 A CN 102208384A
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bottom metal
bump bottom
metal layer
extensions
layer
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CN102208384B (zh
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王姿予
谢棋君
苏安治
陈宪伟
郑心圃
林立伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供了一种半导体结构及半导体装置的形成方法，该半导体结构包括用于半导体装置的凸块底金属层结构。上述凸块底金属层结构具有一中心部与自该中心部延伸的多个延伸部。这些延伸部可具有四边形、三角形、圆形、扇形、具有延伸部的扇形或具有圆滑化表面的修正型四边形的一形状。相邻的凸块底金属层结构具有相互对准或相对地经过旋转的各延伸部。可于这些延伸部的一部涂布一助焊层，以使得上方的一导电凸块附着于这些延伸部的一部。本发明可增加半导体装置的可靠性，特别降低了位于凸块底金属层与导电凸块的介面处的应力聚集情形。

Description

半导体结构及半导体装置的形成方法
技术领域
本发明涉及半导体装置及其形成方法，尤其涉及一种适用于半导体装置的凸块底层金属(under-bump metallization，UBM)结构，其具有自一中心部(center portion)向外延展的数个延伸部(extensions)。
背景技术
自集成电路发明以后，由于多样的电子元件(如晶体管、二极管、电阻、电容等)积集密度的持续改善，半导体工业已经历了持续的快速成长。主要地，积集密度的改善来自于最小特征尺寸(minimum feature size)的持续缩减，如此可于一特定区域内整合更多元件。
于过去数十年来，于半导体封装领域中已经历了足以冲击整个半导体工业的多次改变情形。表面粘着技术(surface-mount technology，SMT)与球栅阵列(ball grid array，BGA)封装物的采用为用于众多种类的集成电路装置的高产能组装的普遍重要步骤，其同时减少了印刷电路板上的接垫间距(padpitch)。公知的封装集成电路具有基本上借由位于裸片(die)上的金属垫与散布于模塑树脂封装物(molded resin package)上之间的纤细金线所形成的内部连接情形。另一方面，如芯片级封装物(chip scale package，CSP)或球栅阵列封装物的部分封装物则依靠锡球的凸块以形成介于裸片上接触物与如封装基板、印刷电路板、另一裸片/晶片或相似物的接触物之间的电性连接关系。于如此的实施情形中，于裸片的焊垫上形成有凸块底层金属(under bump metal，UBM)层，且于此凸块底层金属层上设置有一锡球凸块(solder bump)。这些不同膜层构成了通常具有不同热膨胀系数(coefficients of thermal expansions，CTEs)的内部连接物。其结果为，于连接区域出发现有起因于上述热膨胀系数差异所导致的相对大应力，其通常沿着凸块底金属层与锡球凸块间的介面形成破裂情形(cracks)。
于降低介于锡球凸块与凸块底金属层间的应力的方法之一是将凸块底金属层制作的比较大。当于某些装置采用上述方法以降低应力时，凸块底金属层的增大尺寸使得凸块变的平坦且变形，进而造成形变问题(deformationissues)且增加了相邻的锡球凸块的桥接(bridging)或短路(shorting)的可能。
发明内容
有鉴于此，本发明提供了一种半导体结构及半导体装置的形成方法，借以解决上述公知问题。
于一实施例中，本发明提供了一种半导体结构，包括：
一基板，包括一第一焊垫；一保护层，位于该基板与至少该第一焊垫的一部之上；一第一凸块底金属层，设置于该第一焊垫之上并延伸通过该保护层至该第一焊垫，该第一凸块底金属层具有一中心部与自该中心部延伸于该保护层的一顶面上的多个延伸部；以及一导电凸块，位于该第一凸块底金属层之上，使得所述多个延伸部的至少一部凸出于该导电凸块的一边缘。
于另一实施例中，本发明提供了一种半导体结构，包括：
一基板，具有多个焊垫；一保护层，位于该基板上，该保护层具有分别位于所述多个焊垫上的一开口；以及多个凸块底金属结构，所述多个凸块底金属结构分别位于对应的所述开口之一之上，所述多个凸块底金属结构的一具有一中心部与自该中心部突出的多个延伸部，所述多个延伸部位于该保护层之上。
于又一实施例中，本发明提供了一种半导体装置的形成方法，包括：
提供具有一第一焊垫的一第一基板；形成一保护层于该第一基板与该第一焊垫之上；形成一第一开口于该保护层内，露出该第一焊垫的至少一部；以及形成一第一凸块底金属层于该第一开口内，该第一凸块底金属层具有一中心部以及自该中心部向外延伸的多个延伸部，至少所述多个延伸部的一部位于该保护层的一顶面上。
本发明可增加半导体装置的可靠性，特别降低了位于凸块底金属层与导电凸块的介面处的应力聚集情形。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举一优选实施例，并配合所附的附图，作详细说明如下：
附图说明
图1a-图1c为一系列示意图，显示了依据本发明的一实施例的一半导体装置内的凸块底金属层与导电凸块；
图2为一俯视图，显示了依据本发明一实施例的凸块底金属层的排列情形；
图3a-图3c示出了可于依据本发明的一实施例内所得到的介于一导电凸块与一凸块底金属层之间的应力差异；
图4a-图4f为依据本发明的多个实施例内的凸块底金属层所可能具有的不同形状的范例；
图5a-图5d为一系列示意图，显示了依据本发明的一实施例的涂布有助焊剂的凸块底金属层；以及
图6-图9为一系列示意图，示出了依据本发明的一实施例的形成具有一凸块底金属层结构的一半导体装置的不同的中间阶段。
其中，附图标记说明如下：
100～基板；
102～导电凸块；
104～保护层；
106～导电接垫；
108～凸块底金属层；
108a～凸块底金属层的延伸部；
108b～凸块底金属层的中心部；
310、312、314、316～区域；
502～助焊剂；
504～区域；
602～基板；
604～电路；
608～层间介电层；
610～接触物；
612～金属层间介电层；
614～导电接垫；
616～保护层；
618～焊垫；
620～保护层；
622～晶种层；
624～掩模层；
710～凸块底金属层；
810～助焊剂；
910～导电凸块；
LE～延伸部的长度；
WE～延伸部的宽度；
P～相邻的凸块底金属层的间距；
WC～中间部的宽度；
θ～相邻延伸物之间的角度。
具体实施方式
于下文中描述的实施例关于适用于半导体装置的凸块底金属层(under-bump metallization，UBM)。如下文中将讨论的，基于附着一基板与另一基板的目的，于实施例中仅揭示了具有自一中心处向外延伸结构的凸块底金属层结构的使用，其中上述基板可分别为一裸片(die)、一晶片(wafer)、一印刷电路板(printed circuit board，PCB)、一封装基板(package substrate)或相似物，进而可形成裸片-裸片、晶片-裸片、晶片-晶片、芯片/晶片-印刷电路板或封装基板或相似的组装情形。于不同附图与实施情形中，使用相同的标记以显示相同的元件。
图1a与图1b分别为一俯视图与一侧视图，显示了依据本发明的一实施例的具有导电凸块102形成于其上的基板的一部，其中图1b显示了沿着图1a内A-A’线段的情形。此外，图1c为一俯视图，显示了如同图1a的情形但不具有导电凸块形成于其上，其中相同标记代表了相同元件。首先，值得注意的是基板100可为裸片、晶片或相似物的一部。如本领域普通技术人员所知悉，于下文中描述的实施例可应用于需要电性连接于一接触垫(contactpad)的任何情形。
基板100的一外部表面为如聚合物层的一保护层104所覆盖，以保护基板100免于环境的污染并作为一应力缓冲层(stress buffer layer)之用。于保护层104内形成有多个开口，其分别露出位于下方的一导电接垫(conductivepad)106。可于保护层104之上形成位于这些开口内一凸块底金属层108，其具有自一中心部108b的向外辐射延伸的数个延伸部108a，进而形成与下方的导电接垫106的电性连接关系。中心部108b具有约相同于所期望导电凸块的一尺寸。凸块底金属层108可为如铜或其他导电材料。如无铅锡球凸块的导电凸块102则形成于凸块底金属层108上，以形成与如一裸片、晶片、封装基板或相似物的一第二基板(未显示)的电性连接关系。
于一实施例中，延伸部108a的数量至少为3或更多，其中这些延伸部108a具有约为中间部108b的宽度WC的0.19～0.58倍的宽度WE，而这些延伸部108a的长度LE则约为相邻的凸块底金属层108的间距P的0.11-0.15倍。可以发现到上述比例适用于于下文中讨论的工艺技术，且通过了模拟结果显示了这些比例有助于改善应力的特性。然而，值得注意的是，于其他实施例中也可采用不同的比例。
图2示出了依据本发明的一实施例，其将如图1a-图1c所示的凸块底金属层108按照一介面图案(interface pattern)而设置。如先前所知悉的，如图1a-图1c所示的设置情形提供了凸块底金属层一较大的表面积，进而可能降低沿着介于导电凸块102与凸块底金属层108间介面的应力。然而，随着半导体装置的尺寸的缩减，如图2所示的介面图案则可能为较佳选择。于此实施例中，相邻的凸块底金属层108的延伸部108a的位置可彼此偏移。如此的介面图案可借由增加介于凸块底金属层108的延伸部108a之间的距离而降低及/或减少相邻的凸块底金属层108的桥接问题。于一实施例中，相邻的凸块底金属层108旋转了θ/2度，其中θ为相邻延伸物108a之间的角度。
可以理解的是，于此揭示的实施例可借由降低并均匀化介于导电凸块102与凸块底金属层108之间的应力而增加半导体装置的可靠性。特别地，可以理解的是借由延伸凸块底金属层108超过导电凸块102的期望边界，这些延伸部降低了位于凸块底金属层108与导电凸块102的介面处的应力聚集情形。
举例来说，图3a与图3b分别示出了沿着介于导电凸块与凸块底金属层的介面处的主应力(principle stress)与Y应力(Y stress)的应力平面图(stressplots)。于图3a与图3b中，上方附图示出了发现于利用不具有延伸部的凸块底金属层的系统的应力(表示为控制组)，而下方附图则示出了利用了具有如前述的延伸部的凸块底金属层的实施例的应力(表示为实施例)。首先参照图3a，本领域普通技术人员可知道如前所述的实施例具有较均匀的主应力(如破裂应力)，特别是于采用椭圆310与312所标记的区域处。请参照图3b，如椭圆314与316所示，于Y应力(如脱层应力)也发现了一相似结果。图3c则示出了于上述实施例中可降低主应力与Y应力约10％。
图4a-图4f示出了依据本发明的多个实施例中所具有的不同形状的延伸部108a。特别地，于图4a-图4f所示出的实施例中，延伸部108a可分别具有对应于四边形、三角形、圆形、扇形、具有延伸部的扇形以及具有圆滑化表面的修正型四边形的一形状。值得注意的是如图4a-图4f的实施例中基于示出的目的仅显示了四个延伸部，可以理解的是于其他实施例中可则使用更少或更多的延伸部。
图5a-图5d则示出了依据本发明的一实施例，其内使用了一选择性的助焊剂(flux)502。做为参考之用，图5a为参照前述图1a-图1c的一实施例的俯视图，其中相同标记代表相同元件。图5b则为一俯视图，显示了使用图案化的一助焊剂502以使得其自凸块底金属层108的中心部108b沿着凸块底金属层108的延伸部108a而向外延伸。采用沿着延伸部108a的一中心部向外延伸的助焊剂502的结果为导电凸块102也可倾向于朝向延伸部108a的一部而向外延伸，如图5c与图5d内虚线圆形区域504所示，其中图5d为一侧视图，显示了沿图5c内的线段B-B’的情形。上述实施例可帮助降低或减少凸块底金属层的底切(undercut)问题，并借由助焊剂区域所形成的基础控制而增加了凸块-凸块底金属层的附着强度。
图6-图9显示了如前所述的依据本发明的一实施例的半导体装置的形成方法的不同中间阶段。首先请参照图6，显示了依据一实施例的具有一电路604形成于其上的一基板602的一部。基板602可包括如经掺杂或为未经掺杂的块状硅或一绝缘层上覆半导体(semiconductor-on-insulator，SOI)基板的一主动层。通常，绝缘层上覆半导体基板包括形成于一绝缘层之上的如硅的一半导体材料的膜层。绝缘层可以是如埋入氧化物(buried oxide，BOX)层或氧化硅(silicon oxide)层。绝缘层通常形成于如硅基板或玻璃基板的一基板上。也可使用如多膜层(multi-layered)或梯度(gradient)基板的其他基板。
形成于基板602上的电路604可为适用于一特殊应用的任何形式的电路。于一实施例中，电路604包括了形成于基板602上数个电子装置，而基板602具有覆盖上述电子装置的一或多个介电层。也可于上述介电层之间形成数个金属层以于上述电子装置之间发送电子信号。这些电子装置也可形成于一或多个介电层内。
举例来说，电路604可包括数个N型金属氧化物半导体及/或P型金属氧化物半导体装置，并内部连接有如晶体管、电容、电阻、二极管、发光二极管、熔丝或相似物，借以表现出一或多种功能。这些功能可包括存储结构、处理结构、传感器、放大器、电源分布、输入/输出电路或相似物。本领域普通技术人员可以理解到上述实施例是作为解说之用而非用以限定本发明。也可使用其他的电路以提供一特定应用。
图6中也显示了一层间介电(inter-layer dielectric，ILD)层608。层间介电层608可由一低介电常数介电材料所形成，例如磷硅玻璃(PSG)、硼磷硅玻璃(BPSG)、氟化硅玻璃(FSG)、SiOxCy、旋涂玻璃(spin-on glass)、旋转涂布聚合物(spin-on polymer)、碳化硅材料、其化合物、其组成物、其混合物或相似物，其可借由如旋转方式、化学气相沉积及等离子体加强型化学气相沉积等公知的任何适当方法所形成。值得注意的是层间介电层608可包括多个介电层。
如接触物610的接触物可形成并通过层间介电层608，以形成至电路604的一电性接触情形。接触物610可借由使用光刻技术以沉积与图案化一阻剂于层间介电层608之上并露出可成为接触物610的部分的层间介电层608。可使用如为各向异性干蚀刻程序的一蚀刻程序以于层间介电层608内形成数个开口。这些开口内将内衬有一扩散阻障层及/或一粘着层(未显示)且为一导电材料所填满。于一实施例中，扩散阻障层包括TaN、Ta、TiN、Ti、CoW或相似物的一或多个膜层以及包括了铜、钨、铝、银、其组成物或相似物的导电材料，以形成如图6内所示的接触物610。
于层间介电层608上形成有一或多个金属层间介电(inter-metaldielectric，IMD)层612及相关的金属化膜层。通常，可使用此一或多个金属层间介电层612及相关的金属化膜层以形成这些电路604彼此之间的内部连接情形并形成一外部导电连接情形。这些金属层间介电层612可由一低介电常数介电层所形成，如由等离子体加强型化学气相沉积法技术或高密度等离子体加强型化学气相沉积或相似方法所形成的氟掺杂硅玻璃，且可包括位于中间的蚀刻停止层。于最上层的金属层间介电层上形成有数个导电接垫614，以形成外部的电性连接关系。
值得注意的是，可于如层间介电层608与金属层间介电层612之间的相邻介电层之内设置一或多个蚀刻停止层(未显示)。通常，当形成介层物及/或接触物时，蚀刻停止层提供了阻挡一蚀刻工艺的一机制。这些蚀刻停止层是由与如下方半导体基板602、上方的层间介电层608以及上方的金属层间介电层612等相邻膜层之间具有一不同蚀刻选择率的一介电材料所形成。于一实施例中，蚀刻停止层可由SiN、SiCN、SiCO、CN、其组合情形或相似物所形成，并借由化学气相沉积或等离子体加强型化学气相沉积方式而沉积形成。
可于最上层的金属层间介电层612的表面上形成由如聚亚酰胺、聚合物、氧化物或相似物的一介电材料的一保护层616，并图案化的以形成位于导电接垫614上的一开口并保护了下方膜层免于受到多样的环境污染。接着，于保护层616之上形成多个焊垫618并将其图案化。这些焊垫618于用于外部连接的一凸块底金属层结构形成之后形成了电性连接。这些焊垫618可由如为铜、钨、铝、银、其组合物或相似物的一适当导电材料所形成。
如图6所示，于这些导电接垫618之上形成如保护层620的一或多个保护层并将其图案化。保护层620可借由如一聚合物的一介电材料所形成，并借由如化学气相沉积法、物理气相沉积或相似方法的适当方法所形成。于一实施例中，保护层620具有约介于1～15微米的厚度。
本领域普通技术人员可以理解到在此的单一膜层的导电/焊垫与一保护层仅作为解说之用。如此，于其他实施例中可包括任何数量的导电层及/或保护层。另外，可以理解的是，一或多个导电层可作为一重分布层(redistributionlayer，RDL)，以形成期望的接脚或锡球布局情形。
图6内还显示了沉积于保护层620的表面上的一顺应晶种层622。晶种层622为导电材料的一薄膜层，借以于后续工艺步骤中帮助一较厚膜层的形成。于一实施例中，晶种层622可借由沉积如一薄膜层Ti、Cu、Ta、TiN、TaN、其组成物或相似物一薄导电层而形成，其可借由化学气相沉积与物理气相沉积技术所形成。
如图6所示，于一实施例中，接着于晶种层622上形成一图案化的掩模层624并将其图案化。图案化的掩模层624定义了凸块底金属层的形状。如此，图案化的掩模层624经过图案化以形成具有一中心部及如前述的一或多个形状的数个延伸部的一形状。图案化的掩模层624可为一图案化的光致抗蚀剂掩模、硬掩模、其组合或相似物。
可使用任何适当工艺，以形成前述的结构，于下文中不再详细描述其制作。本领域普通技术人员可以理解，以上描述提供了本实施例的特征以及其他可以表现的特征的一大体概念。举例来说，可形成有其他的电路、衬层、阻障层、凸块底金属层结构或相似物。前述描述仅提供了于此讨论的一种实施例形态，而并非用于限制本发明的揭示情形或本发明的专利保护范围的范畴。
图7显示了依据一实施例的凸块底金属层710的形成。凸块底金属层710可由包括Cu、Ni、Pt、Al、其组合物或相似物的一适当导电材料所形成，且其可借由包括物理气相沉积、化学气相沉积、电化学沉积(electrochemicaldeposition，ECD)、分子束外延(molecular beam epitaxy，MBE)、原子层沉积(atomic layer deposition，ALD)、电镀(electroplating)及相似技术的任何数量的适当技术所形成。可以理解的是，于部分实施例中，例如是于沉积一顺应膜层于晶片的整个表面(如物理气相沉积与化学气相沉积)的实施例中，可较佳地施行一蚀刻或平坦化工艺(如一化学机械研磨)以自图案化的掩模层624的表面处移除过量导电材料。于一实施例中，凸块底金属层710具有约为1-10微米的一厚度。
图8显示了依据一实施例中的图案化的掩模层624的移除(对应于凸块底金属层710的形状)以及一选择性的图案化的助焊剂(flux)810的形成。于图案化的掩模层624由阻剂材料所形成的实施例中，其阻剂材料可借由如乙酸乙酯(ethyl acetate)、甲氧苯(anisole)、醋酸戊酯(methyl butyl acetate)、乙酸戊酯(amyl acetate)、甲酚树脂(cresol novolak resin)与偶氮感光剂(diazo photoactivecompound，也称为SPR 9)的一化学溶液所去除，或借由其他去除工艺所去除。接着施行一洁净程序，例如为置于通称为DPP的具有具有磷酸与过氧化氢的一化学溶液中的湿式浸泡程序、或置于2％氢氟酸中或其他的洁净程序中，以自晶种层622的露出部以及自保护层620的表面去除任何的污染物。
如先前的图5a-图5d所示情形，可以理解的是较佳地可形成一图案化助焊剂，例如图案化助焊剂810以使得于后续程序中形成的导电凸块材料可自延伸部108a的一部而延伸(请参照图5a-图5d)。经图案化的助焊剂810可采用适当技术而形成，如采用利用一图案(如一模版)的模版印刷(stenciling)技术以控制于需要形成助焊剂的位置处形成助焊剂。
图9示出了导电凸块910的形成。于一实施例中，导电凸块910包括了SnPb、一高铅材料、一Sn基焊锡、一无铅焊锡或其他的适当导电材料。导电凸块可借由任一适当工艺而形成，例如为使用一图案化掩模与沉积技术的一挑放工艺(pick-and-place)或相似方法所形成。
接着，施行适用于特殊应用的一回焊(solder reflow)工艺以及导线后段(back-end-of-line，BEOL)工艺技术。于此回焊工艺中，特别地如前所述般使用经图案化的助焊剂时，这些导电凸块910可沿着部分的延伸部而向外延伸。另一导线后段工艺技术则可包括如形成一包覆物、施行一单一化工艺以形成单一裸片、晶片层级或芯片层级堆叠物或相似物等工艺。然而值得注意的是，上述的实施例可于不同情形下使用。例如可于裸片-裸片连接情形、裸片-晶片连接情形、晶片-晶片连接情形、芯片层级封装物以及晶片层级封装物或相似物等情形下使用。
虽然本发明已以优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作更动与润饰，因此本发明的保护范围当视所的权利要求所界定的范围为准。

Claims (11)

1.一种半导体结构，包括：
一基板，包括一第一焊垫；
一保护层，位于该基板与至少该第一焊垫的一部之上；
一第一凸块底金属层，设置于该第一焊垫之上并延伸通过该保护层至该第一焊垫，该第一凸块底金属层具有一中心部与自该中心部延伸于该保护层的一顶面上的多个延伸部；以及
一导电凸块，位于该第一凸块底金属层之上，使得所述多个延伸部的至少一部凸出于该导电凸块的一边缘。
2.如权利要求1所述的半导体结构，其中该基板还包括一第二焊垫及还包括设置于该第二焊垫之上且延伸穿过该保护层至该第二焊垫的一第二凸块底金属层，该第二凸块底金属层具有一中心部与自该中心部延伸至该保护层的该顶面之上的多个延伸部。
3.如权利要求2所述的半导体结构，其中该第一焊垫与该第二焊垫为相邻的焊垫，且其中相对于该第二凸块底金属层的所述多个延伸部，该第一凸块底金属层的所述多个延伸部经过旋转或对准于该第二凸块底金属层的所述多个延伸部。
4.一种半导体结构，包括：
一基板，具有多个焊垫；
一保护层，位于该基板上，该保护层具有分别位于所述多个焊垫上的一开口；以及
多个凸块底金属结构，所述多个凸块底金属结构分别位于对应的所述开口之一之上，所述多个凸块底金属结构的一具有一中心部与自该中心部突出的多个延伸部，所述多个延伸部位于该保护层之上。
5.如权利要求4所述的半导体结构，还包括一导电凸块，位于该凸块底金属层的该中心部上，使得所述多个延伸部的至少一部凸出于该导电凸块的一边缘。
6.如权利要求4所述的半导体结构，其中相邻的所述多个凸块底金属层的所述多个延伸部相对地经过旋转或大体相互对准。
7.一种半导体装置的形成方法，包括：
提供具有一第一焊垫的一第一基板；
形成一保护层于该第一基板与该第一焊垫之上；
形成一第一开口于该保护层内，露出该第一焊垫的至少一部；以及
形成一第一凸块底金属层于该第一开口内，该第一凸块底金属层具有一中心部以及自该中心部向外延伸的多个延伸部，至少所述多个延伸部的一部位于该保护层的一顶面上。
8.如权利要求7所述的半导体装置的形成方法，还包括：
形成一第二开口于该保护层内，露出位于该基板上的一第二焊垫的至少一部；以及
形成一第二凸块底金属层于设置于该第二焊垫上的该第二开口内并延伸通过该保护层至该第二焊垫，该第二凸块底金属层具有一中心部以及自该中心部延伸至该保护层的该顶面上的多个延伸部。
9.如权利要求8所述的半导体装置的形成方法，其中该第一凸块底金属层与该第二凸块底金属层为相邻，且其中该第一凸块底金属层的所述多个延伸部对准于该第二凸块底金属层的所述多个延伸部或相对于该第二凸块底金属层的所述多个延伸部为大体经过旋转。
10.如权利要求8所述的半导体装置的形成方法，其中该第一凸块底金属层的所述多个延伸部与该第二凸块底金属层具有约为介于该第一凸块底金属层与该第二凸块底金属层之间一间距0.11-0.15倍的一长度。
11.如权利要求7所述的半导体装置的形成方法，其中所述多个延伸物具有该中心部的一直径0.19-0.58倍的一宽度。
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