CN102194705B - 具有保护性中介层的嵌入式裸片 - Google Patents

具有保护性中介层的嵌入式裸片 Download PDF

Info

Publication number
CN102194705B
CN102194705B CN201110068207.9A CN201110068207A CN102194705B CN 102194705 B CN102194705 B CN 102194705B CN 201110068207 A CN201110068207 A CN 201110068207A CN 102194705 B CN102194705 B CN 102194705B
Authority
CN
China
Prior art keywords
nude film
lamination
die
substrate
intermediary layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201110068207.9A
Other languages
English (en)
Chinese (zh)
Other versions
CN102194705A (zh
Inventor
吴亚伯
吴嘉洛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kaiwei International Co
Marvell International Ltd
Marvell Asia Pte Ltd
Original Assignee
Mawier International Trade Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mawier International Trade Co Ltd filed Critical Mawier International Trade Co Ltd
Publication of CN102194705A publication Critical patent/CN102194705A/zh
Application granted granted Critical
Publication of CN102194705B publication Critical patent/CN102194705B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
CN201110068207.9A 2010-03-18 2011-03-18 具有保护性中介层的嵌入式裸片 Active CN102194705B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US31531910P 2010-03-18 2010-03-18
US61/315,319 2010-03-18

Publications (2)

Publication Number Publication Date
CN102194705A CN102194705A (zh) 2011-09-21
CN102194705B true CN102194705B (zh) 2014-07-23

Family

ID=44602547

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201110068207.9A Active CN102194705B (zh) 2010-03-18 2011-03-18 具有保护性中介层的嵌入式裸片

Country Status (4)

Country Link
US (1) US8338934B2 (enExample)
JP (1) JP5327654B2 (enExample)
CN (1) CN102194705B (enExample)
TW (1) TWI560824B (enExample)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5460388B2 (ja) * 2010-03-10 2014-04-02 新光電気工業株式会社 半導体装置及びその製造方法
US9721872B1 (en) * 2011-02-18 2017-08-01 Amkor Technology, Inc. Methods and structures for increasing the allowable die size in TMV packages
US9799592B2 (en) 2013-11-19 2017-10-24 Amkor Technology, Inc. Semicondutor device with through-silicon via-less deep wells
KR101366461B1 (ko) 2012-11-20 2014-02-26 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US8729714B1 (en) * 2012-12-31 2014-05-20 Intel Mobile Communications GmbH Flip-chip wafer level package and methods thereof
US9041207B2 (en) * 2013-06-28 2015-05-26 Intel Corporation Method to increase I/O density and reduce layer counts in BBUL packages
US9543373B2 (en) * 2013-10-23 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
KR101607981B1 (ko) 2013-11-04 2016-03-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지용 인터포저 및 이의 제조 방법, 제조된 인터포저를 이용한 반도체 패키지
US9852998B2 (en) 2014-05-30 2017-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Ring structures in device die
US9418965B1 (en) 2014-10-27 2016-08-16 Altera Corporation Embedded interposer with through-hole vias
US9633934B2 (en) 2014-11-26 2017-04-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semicondutor device and method of manufacture
US9515017B2 (en) * 2014-12-18 2016-12-06 Intel Corporation Ground via clustering for crosstalk mitigation
CN104485320A (zh) * 2014-12-30 2015-04-01 华天科技（西安）有限公司 一种有垂直通孔的埋入式传感芯片封装结构及其制备方法
CN105097726B (zh) * 2015-06-16 2019-03-12 合肥矽迈微电子科技有限公司 封装结构及封装方法
US9984998B2 (en) * 2016-01-06 2018-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Devices employing thermal and mechanical enhanced layers and methods of forming same
US9922895B2 (en) * 2016-05-05 2018-03-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package with tilted interface between device die and encapsulating material
CN105934095B (zh) * 2016-06-28 2019-02-05 Oppo广东移动通信有限公司 Pcb板及具有其的移动终端
JP2018018936A (ja) * 2016-07-27 2018-02-01 イビデン株式会社 配線基板
US9960328B2 (en) 2016-09-06 2018-05-01 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof
US20190181093A1 (en) * 2016-09-30 2019-06-13 Intel Corporation Active package substrate having embedded interposer
WO2018063383A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Active package substrate having anisotropic conductive layer
JP6822192B2 (ja) * 2017-02-13 2021-01-27 Tdk株式会社 電子部品内蔵基板
US10687419B2 (en) 2017-06-13 2020-06-16 Advanced Semiconductor Engineering, Inc. Semiconductor package device and method of manufacturing the same
DE102018108409B4 (de) 2017-06-30 2023-08-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrierte schaltkreis-packages und verfahren zu deren herstellung
US10872885B2 (en) * 2017-06-30 2020-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming same
CN109786362B (zh) * 2017-11-14 2021-01-05 旺宏电子股份有限公司 无焊垫外扇晶粒叠层结构及其制作方法
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
CN120413551A (zh) * 2018-06-13 2025-08-01 隔热半导体粘合技术公司 作为焊盘的tsv
CN111415908B (zh) * 2019-01-07 2022-02-22 台达电子企业管理（上海）有限公司 电源模块、芯片嵌入式封装模块及制备方法
US11239193B2 (en) * 2020-01-17 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package and method
US11450615B2 (en) * 2020-06-12 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
CN113838829B (zh) * 2020-06-23 2025-01-24 欣兴电子股份有限公司 封装载板及其制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1158006A (zh) * 1995-11-30 1997-08-27 洛克希德马汀公司 具有降低应力成模衬底部分的挠性层的高密度互连电路模件

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000223645A (ja) * 1999-02-01 2000-08-11 Mitsubishi Electric Corp 半導体装置
US7161239B2 (en) * 2000-12-22 2007-01-09 Broadcom Corporation Ball grid array package enhanced with a thermal and electrical connector
US7202556B2 (en) * 2001-12-20 2007-04-10 Micron Technology, Inc. Semiconductor package having substrate with multi-layer metal bumps
SG104293A1 (en) * 2002-01-09 2004-06-21 Micron Technology Inc Elimination of rdl using tape base flip chip on flex for die stacking
US6506633B1 (en) * 2002-02-15 2003-01-14 Unimicron Technology Corp. Method of fabricating a multi-chip module package
TWI334638B (en) * 2005-12-30 2010-12-11 Ind Tech Res Inst Structure and process of chip package
SG135074A1 (en) * 2006-02-28 2007-09-28 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
TWI341577B (en) * 2007-03-27 2011-05-01 Unimicron Technology Corp Semiconductor chip embedding structure
US7687899B1 (en) * 2007-08-07 2010-03-30 Amkor Technology, Inc. Dual laminate package structure with embedded elements
JP5101240B2 (ja) * 2007-10-25 2012-12-19 日本特殊陶業株式会社 板状部品内蔵配線基板
US8230589B2 (en) * 2008-03-25 2012-07-31 Intel Corporation Method of mounting an optical device
JP2009289802A (ja) * 2008-05-27 2009-12-10 Tdk Corp 電子部品内蔵モジュール及びその製造方法
FR2938976A1 (fr) 2008-11-24 2010-05-28 St Microelectronics Grenoble Dispositif semi-conducteur a composants empiles
US8900921B2 (en) * 2008-12-11 2014-12-02 Stats Chippac, Ltd. Semiconductor device and method of forming topside and bottom-side interconnect structures around core die with TSV

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1158006A (zh) * 1995-11-30 1997-08-27 洛克希德马汀公司 具有降低应力成模衬底部分的挠性层的高密度互连电路模件

Also Published As

Publication number Publication date
TWI560824B (en) 2016-12-01
CN102194705A (zh) 2011-09-21
TW201145478A (en) 2011-12-16
US8338934B2 (en) 2012-12-25
JP5327654B2 (ja) 2013-10-30
JP2011199288A (ja) 2011-10-06
US20110227223A1 (en) 2011-09-22

Similar Documents

Publication Publication Date Title
CN102194705B (zh) 具有保护性中介层的嵌入式裸片
CN103168358B (zh) 嵌入式结构及其制造方法
TWI303096B (enExample)
TWI754839B (zh) 封裝結構及其形成方法
US9985005B2 (en) Chip package-in-package
CN103378017B (zh) 高密度3d封装
TWI511263B (zh) 堆疊式晶粒嵌入晶片增層之系統及方法
US9929130B2 (en) Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate
US8624377B2 (en) Method of stacking flip-chip on wire-bonded chip
TW201828370A (zh) 形成堆疊式封裝結構的方法
TW201731054A (zh) 半導體封裝件及半導體封裝件之重工製程
CN103715166A (zh) 用于部件封装件的装置和方法
CN104900597A (zh) 半导体封装件及方法
TWI768874B (zh) 封裝結構及其製作方法
CN106684003A (zh) 扇出型封装结构及其制作方法
CN115692397A (zh) 半导体封装件及其制法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20200424

Address after: Singapore City

Patentee after: Marvell Asia Pte. Ltd.

Address before: Ford street, Grand Cayman, Cayman Islands

Patentee before: Kaiwei international Co.

Effective date of registration: 20200424

Address after: Ford street, Grand Cayman, Cayman Islands

Patentee after: Kaiwei international Co.

Address before: Hamilton, Bermuda

Patentee before: Marvell International Ltd.

Effective date of registration: 20200424

Address after: Hamilton, Bermuda

Patentee after: Marvell International Ltd.

Address before: Babado J San Mega Le

Patentee before: MARVELL WORLD TRADE Ltd.

TR01 Transfer of patent right