CN102163588B - 半导体装置与其制造方法 - Google Patents

半导体装置与其制造方法 Download PDF

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CN102163588B
CN102163588B CN2010102074783A CN201010207478A CN102163588B CN 102163588 B CN102163588 B CN 102163588B CN 2010102074783 A CN2010102074783 A CN 2010102074783A CN 201010207478 A CN201010207478 A CN 201010207478A CN 102163588 B CN102163588 B CN 102163588B
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semiconductor device
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CN102163588A (zh
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郭宏瑞
刘重希
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种在半导体基底上形成的半导体装置与其制造方法，该半导体基底具有第一表面与第二表面，包含多个元件在第一表面上，多个贯穿硅导通孔(TSVs)在半导体基底内，由第一表面延伸至第二表面，保护层覆盖位于半导体基底的第一表面上的所述多个元件，多个有源导电柱设置在保护层上，具有第一高度，每个有源导电柱与所述多个元件中的至少一个电性连接，多个伪导电柱设置在保护层上，具有第二高度，每个伪导电柱与所述多个元件电性隔绝，第一高度与第二高度大抵上相同。本发明结合了导电柱与贯穿硅导通孔的制造方法，以满足工艺的可靠度以及高度整合性的要求。

Description

半导体装置与其制造方法
技术领域
本发明涉及一种半导体凸块的工艺，特别涉及一种导电柱的结构及其形成方法。
背景技术
在半导体元件的封装技术中，倒装芯片封装技术扮演一种重要的角色，倒装芯片的微电子组件包含面朝下的电子元件，其使用焊锡凸块作为内连线，直接电性连接在例如为电路板的基板上。因为倒装芯片封装在尺寸、效能以及适应性上远较其他封装方式具有优势，倒装芯片封装的使用已经显著地成长。
近年来，导电柱技术已逐渐发展，利用铜柱取代焊锡凸块的使用而将电子元件连接至基底上。铜柱技术可达到较焊锡凸块架桥方式更微细的间距，降低电路的电容负载，并允许电子元件执行较高的频率。
最近，已经发展出贯穿硅导通孔(TSV)，以作为增加内连接电子元件密度的方法之一。贯穿硅导通孔借由在z轴形成内连线而达到较短的内连线，此内连线是经由例如为晶片的基底，由基底的正面形成导通孔延伸至背面而产生。贯穿硅导通孔对于在堆叠的晶片、堆叠的芯片和/或上述的组合形成内连线方面也是很有用的。
然而，导电柱技术与贯穿硅导通孔技术的结合存在许多挑战，在传统的工艺中，贯穿硅导通孔由基底的正面延伸至基底的一预定深度处而形成，导电柱在基底的正面上形成，贯穿硅导通孔借由化学机械研磨(CMP)法研磨基底的背面而暴露出来，施加在背面的压力经由这些柱体转移至正面，但是如果这些柱体没有均匀地分布在正面上，施加在背面的压力将不会均匀地分布，造成背面的研磨不均匀。不均匀的研磨会造成这些贯穿硅导通孔的长度改变，并且造成不均匀的背面，而不均匀的背面将会对于后续在背面上的微影工艺造成不利的影响。
因此，业界亟需一种结合导电柱与贯穿硅导通孔的制造方法，以满足工艺的可靠度以及高度整合性的要求。
发明内容
本发明的目的在于提供一种半导体装置与其制造方法，已改善前述的公知问题。
本发明所提供的各种实施例可用来减缓传统柱体工艺的缺点，例如，各种实施例可在化学机械研磨期间减薄基底时，使得背面深度达到一致性。
依据本发明的一实施例，提供一种第一半导体装置，包括：半导体基底，具有第一表面与第二表面，其中半导体基底包含多个元件位于第一表面上；多个贯穿硅导通孔(TSVs)，设置在半导体基底内，由第一表面延伸至第二表面；保护层覆盖在半导体基底的第一表面上的所述多个元件之上；多个有源导电柱设置在保护层上，具有第一高度，其中每个有源导电柱与所述多个元件中的至少一个电性连接；以及多个伪柱设置在保护层上，具有第二高度，其中每个伪柱与所述多个元件电性隔绝，其中第一高度与第二高度大抵相同。
依据本发明的另一实施例，提供一种在第一半导体装置形成多个导电柱的方法，包括：提供半导体基底，该基底具有第一表面与第二表面，其中半导体基底包含多个元件位于第一表面上；形成多个贯穿硅导通孔(TSVs)在半导体基底内，由第一表面延伸至第二表面；形成保护层在半导体基底的第一表面上；形成多个有源导电柱在保护层上，其中每个有源导电柱具有第一高度，且与所述多个元件中的至少一个电性连接；形成多个伪柱在保护层上，其中每个伪柱具有第二高度，且与所述多个元件电性隔绝，其中第一高度与第二高度大抵相同。
为了让本发明的上述目的、特征、及优点能更明显易懂，以下配合附图，作详细说明如下：
附图说明
图1显示第一半导体装置的基底的剖面示意图，其具有多个元件形成于第一表面上。
图2显示经由图1的基底所形成的贯穿硅导通孔。
图3显示贯穿硅导通孔内填充导电材料。
图4显示在贯穿硅导通孔之上形成的内连线层与保护层。
图5显示在保护层上形成的多个有源导电柱与多个伪柱。
图6显示有源导电柱与伪柱贴附至载体。
图7A显示不具有伪柱时，于第二表面上执行薄化工艺后的结果。
图7B显示具有伪柱时，于第二表面上执行薄化工艺后的结果。
图8显示第二装置接合至第一半导体装置。
图9至图11系显示形成于基底上的伪柱的各种可能排列方式的俯视图。
其中，附图标记说明如下：
100～基底；102～第一半导体装置；103～基底的第一表面；105～基底的第二表面；107～元件；109～绝缘层；111～接触插塞；113～贯穿硅导通孔；115～导电材料；117～内连线层；119～保护层；121～有源导电柱；123～伪柱；125～载体；128～空隙；129～新第二表面；130～第二装置；131～焊锡；140、150～芯片；142、144～芯片的边；145～三角形区域；146～芯片的角；147～禁区的另一区；148～禁区；156～电性熔线。
具体实施方式
在此所描述的“基底”一词一般可称为半导体基底，于其上形成各层与各种元件，基底为晶片的一部分，后续被分割成多个芯片，每个芯片含有单一的半导体装置。基底可包含硅或化合物半导体，例如GaAs、InP、Si/Ge或SiC，形成于其上的各层可包含介电层、掺杂层、金属层、多晶硅层以及导通孔插塞(via plug)，其可连接一层至一层或一层以上的其他层。
参阅图1，第一半导体装置102在基底100上形成，基底100具有第一表面103与第二表面105，多个元件107形成于第一表面103上，这些元件例如可包含晶体管、电阻器和/或电容器。绝缘层109在第一表面103之上形成，覆盖这些元件107，此绝缘层109例如可为氧化层或掺磷硅玻璃(phosphosilicate glass，简称
Figure BSA00000157101000031
PSG)。接点插塞(contact plug)111由绝缘层109的上表面延伸至元件107，作为与其上方层的内连线。
参阅图2，借由蚀刻工艺穿透绝缘层109，由第一表面103延伸并进入半导体基底100至一预定深度，以形成贯穿硅导通孔(TSV)113，此蚀刻工艺可以是使用电浆的干蚀刻工艺。此外，贯穿硅导通孔113可借由激光钻孔(laser drilling)工艺形成。
参阅图3，在贯穿硅导通孔113内填充导电材料115，导电材料115可包含铜或铜合金。然而，其他金属，例如铝、银、金以及前述的组合也可以使用。导电材料可能的形成方式包含无电电镀或其他常用的沉积方法，例如溅镀、印刷、电镀以及化学气相沉积法(CVD)。每个元件107与在基底100内的这些贯穿硅导通孔113中的至少一个连接。
参阅图4，在贯穿硅导通孔113的表面上形成内连线层117，内连线层117包含一层或一层以上的导电层(未绘出)设置在一层或一层以上的介电层(未绘出)内。内连线层117在元件107之上形成，使得这些元件与其上方层产生电性连接。保护层119在内连线层117之上形成，保护其下方的内连线层117。保护层119可包含介电材料，例如氧化物、氮化物或任何其他材料，其为本领域普通技术人员所熟悉的材料。
参阅图5，在保护层119上形成多个有源导电柱(active conductivepillars)121与多个伪柱(dummy pillars)123，在保护层119上形成图案化光致抗蚀剂层(未绘出)作为金属沉积工艺的模具，金属沉积工艺例如为铜电镀工艺，可用来形成有源导电柱121与伪柱123。在一实施例中，有源导电柱121与伪柱123在相同的工艺步骤中同时形成。另外，有源导电柱121与伪柱123可在不同的工艺步骤中形成。有源导电柱121与伪柱123可由铜制成，此外，具有良好热传导性的金属或合金，例如金(Au)、银(Ag)、铝(Al)、锡-银(Sn-Ag)合金、锡-铜(Sn-Cu)合金也可以使用。每个有源导电柱121与这些元件107中的至少一个电性连接，虽然这些伪柱123可由导电材料形成，但是他们与这些元件107电性隔绝。如后所述，这些伪柱123可在薄化工艺期间改善基底100的第二表面105的深度均匀性。在一实施例中，每个有源导电柱121具有第一高度H1，每个伪柱123具有第二高度H2，第一高度H1与第二高度H2大抵上相同。
参阅图6，有源导电柱121与伪柱123借由粘着剂贴附至载体125上，一般而言，载体125在后续的工艺步骤中提供暂时的机械与结构上的支撑。载体125的基础材料可包含玻璃、硅、氧化硅或其他材料。
图7A与图7B显示在基底100的第二表面105之上执行薄化工艺，以暴露出贯穿硅导通孔113。在图7A的第一半导体装置102中具有有源导电柱121，其以一连串的列与行的形式设置在基底100的保护层119上。由于图7A没有伪柱123填充在相邻的有源导电柱121之间的空隙128内，有源导电柱121在基底100上的分布不均匀。于薄化工艺期间，施加在第二表面105以迫使第二表面105对抗研磨垫的压力，会经由第一表面103上的有源导电柱121而转移，如果在第一表面103上的有源导电柱121分布不均匀，施加在第二表面105的压力也会分布不均匀，导致更多的力施加在其第一表面103上具有较少的有源导电柱121的第二表面105处，此不均匀的力会造成研磨过的新的第二表面129不均匀，此不均匀的背面对于后续在背面上的微影工艺产生不利的影响。
参阅图7B，在一实施例中，于图7A的空隙128中插入多个伪柱123，空隙128中不包含有源导电柱121。这些伪柱123有效地促使所有有源导电柱121的中的压力均等分布，使用伪柱123改善了新第二表面129的均匀度，新第二表面129借由在第二表面105上均匀分布的压力而平面化，使得基底100的新第二表面129得到平滑的表面。均匀的新第二表面129可提升在新第二表面129上的后续微影工艺的能力。
然后，可进行湿式或干式蚀刻工艺，在新第二表面129上形成凹陷，让贯穿硅导通孔113从基底100的新第二表面129突出。贯穿硅导通孔113提供第一半导体装置102至其他装置的电性连接。
参阅图8，使用焊锡131将第一半导体装置102与第二装置130接合。在一实施例中，第二装置130可以是半导体芯片、载体基底、电路板或为本领域普通技术人员所熟悉的任何合适的装置。第一半导体装置102与第二装置130可经由有源导电柱121电性连接，然而，伪柱123不会与第二装置130有物理上或电性上的接触。连接第一半导体装置与第二装置的接合方法包含铜对铜的接合、焊锡接合或本领域普通技术人员所熟悉的任何合适的方法。
图9至图11显示依据各实施例，在基底100上形成伪柱123的各种示范性的排列方式的俯视图，图9显示第一半导体装置102布局的一实施例的俯视图，其中伪柱123插入如图7A中所示的在导电柱121之间的空隙128中。伪柱123的剖面可以是各种形状，例如为圆形、正方形或长方形。在此实施例中，有源导电柱121排列成具有空隙128的列与行的图案，每个圆形的有源导电柱121具有第一宽度W1，且每个圆形的伪柱123具有第二宽度W2。第一宽度W1与第二宽度W2的比值约为0.9至1.1。任一有源导电柱121与任一伪柱123之间的距离D1大于或等于第一宽度W1。
图10显示第一半导体装置102布局的另一实施例的俯视图，第一半导体装置102设置在一矩形的芯片140上，芯片140具有两个边142、144从每个角146延伸出来，角146由芯片140的一直角形成。在基底100内的禁区(forbidden area)148不含有任何有源导电柱121与任何伪柱123，禁区148包含在芯片140的每个角146附近的三角形区域145，以及邻接芯片140的每个边的区域147。从角146沿着两个边142、144延伸一长度B定义出三角形区域145，长度B大于或等于第一宽度W1的1.8倍。邻接边的区域147在距离芯片140的每个边142、144一预定距离D2的范围内。当芯片尺寸大于15mm2时，预定距离D2大于或等于第一宽度W1的0.7倍；当芯片尺寸小于15mm2时，预定距离D2大于或等于第一宽度W1的0.5倍。
图11显示设置在芯片105上的第一半导体装置102布局的另一实施例的俯视图，芯片150包含在保护层119上的有源导电柱121、伪柱123以及电性熔线(electrical fuse)156。电性熔线156为电流遮断元件，其保护元件107，避免元件107对过量电流反应而受损。任一有源导电柱121和任一伪柱123与其邻近的电性熔线156之间的距离D3大于或等于第一宽度W1的0.65倍。
虽然本发明已揭示优选实施例如上，然而其并非用以限定本发明，本领域普通技术人员当可了解，在不脱离本发明的精神和范围内，当可做些许更动与润饰。因此，本发明的保护范围当视随附的权利要求所界定的范围为准。

Claims (11)

1.一种半导体装置，包括：
一第一半导体装置，包括：
一半导体基底，具有一第一表面与一第二表面，其中该半导体基底包含多个元件设置于该第一表面上；
多个贯穿硅导通孔，设置在该半导体基底内，由该第一表面延伸至该第二表面；
一保护层，覆盖在该半导体基底的该第一表面上的所述多个元件之上；
多个有源导电柱，设置在该保护层上，具有一第一高度，其中每个有源导电柱与所述多个元件中的至少一个电性连接；以及
多个伪柱，设置在该保护层上，具有一第二高度，其中每个伪柱与所述多个元件电性隔绝，
其中该第一高度与该第二高度相同。
2.如权利要求1所述的半导体装置，其中每个有源导电柱具有一第一宽度，每个伪柱具有一第二宽度，该第一宽度与该第二宽度的比值为0.9至1.1。
3.如权利要求2所述的半导体装置，其中任一有源导电柱与任一伪柱之间的距离大于或等于该第一宽度。
4.如权利要求2所述的半导体装置，其中该基底包括多个矩形的芯片，且每个芯片的一禁区不包含任何有源导电柱及任何伪柱，其中该禁区包括：
一三角形区域，由该芯片一角的直角所形成的一直角三角形所定义，具有从该角沿着该芯片的边缘延伸一长度B的两个边，该长度B大于或等于该第一宽度的1.8倍；以及
一区域，该区域在与该芯片的边缘相隔一预定距离的范围内。
5.如权利要求4所述的半导体装置，其中当一芯片尺寸大于15mm2时，该预定距离大于或等于该第一宽度的0.7倍。
6.如权利要求4所述的半导体装置，其中当一芯片尺寸小于15mm2时，该预定距离大于或等于该第一宽度的0.5倍。
7.如权利要求1所述的半导体装置，更包括一第二半导体装置，经由所述多个有源导电柱，与该第一半导体装置上的所述多个元件电性连接，其中所述多个伪柱不与该第二半导体装置接触。
8.一种在第一半导体装置形成多个导电柱的方法，包括：
提供一半导体基底，该基底具有一第一表面与一第二表面，其中该半导体基底包含多个元件设置于该第一表面上；
形成多个贯穿硅导通孔在该半导体基底内，由该第一表面延伸至该第二表面；
形成一保护层在该半导体基底的该第一表面上；
形成多个有源导电柱在该保护层上，其中每个有源导电柱具有一第一高度，且与所述多个元件中的至少一个电性连接；
形成多个伪柱在该保护层上，其中每个伪柱具有一第二高度，且与所述多个元件电性隔绝，
其中该第一高度与该第二高度相同。
9.如权利要求8所述的在第一半导体装置形成多个导电柱的方法，其中每个有源导电柱具有一第一宽度，每个伪柱具有一第二宽度，该第一宽度与该第二宽度的比值为0.9至1.1，且其中任一有源导电柱与任一伪柱之间的距离大于或等于该第一宽度。
10.如权利要求8所述的在第一半导体装置形成多个导电柱的方法，更包括提供一第二装置，经由所述多个有源导电柱，与该第一半导体装置上的所述多个元件电性连接，其中所述多个伪柱不与该第二装置接触。
11.如权利要求9所述的在第一半导体装置形成多个导电柱的方法，其中该基底包括多个矩形的芯片，且每个芯片内的一禁区不包含任何有源导电柱或任何伪柱，其中该禁区包括：
一三角形区域，由每个芯片的一角的直角所形成的一直角三角形所定义，具有从该角沿着该芯片的边缘延伸一长度B的两个边，该长度B大于或等于该第一宽度的1.8倍；以及
一区域，该区域在与每个芯片的边缘的一相隔一预定距离的范围内。
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