CN102074497B - 半导体芯片和晶片堆叠封装件的制造方法 - Google Patents

半导体芯片和晶片堆叠封装件的制造方法 Download PDF

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CN102074497B
CN102074497B CN201010525017.0A CN201010525017A CN102074497B CN 102074497 B CN102074497 B CN 102074497B CN 201010525017 A CN201010525017 A CN 201010525017A CN 102074497 B CN102074497 B CN 102074497B
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conductive plug
substrate
hole
photoresist pattern
photoresist
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CN102074497A (zh
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黄善宽
李仁荣
李镐珍
张东铉
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

本发明公开了一种半导体芯片和晶片堆叠封装件的制造方法，所述半导体芯片的制造方法包括以下步骤：在基底的前表面中形成第一通孔；利用第一导电材料在第一通孔中形成第一导电塞，第一导电塞包括在基底中的第一部分和从基底突出的第二部分；利用第二导电材料在第一导电塞的上表面上形成第二导电塞，第二导电塞的横截面面积小于第一导电塞；对基底的后表面进行背部减薄；在基底的经过背部减薄的后表面中形成第二通孔，第二通孔与第一通孔对准。

Description

半导体芯片和晶片堆叠封装件的制造方法
技术领域
示例实施例涉及一种半导体芯片和晶片堆叠封装件的制造方法。
背景技术
随着电子产品向着小型化和多功能化发展的趋势，半导体芯片也变得更高度地集成和多功能化。由于这种趋势，已经开发了将多个半导体芯片封装为一个半导体芯片的多芯片封装(MCP)技术，具体地说，晶片堆叠封装(WSP)技术。
发明内容
本发明提供一种提高结合可靠性和电学性能的半导体芯片和晶片堆叠封装件的方法。
示例实施例涉及一种制造半导体芯片的方法。该方法包括以下步骤：在基底的前表面中形成第一通孔；利用第一导电材料在第一通孔中形成第一导电塞，第一导电塞包括在基底中的第一部分和从基底突出的第二部分；利用第二导电材料在第一导电塞的上表面上形成第二导电塞，第二导电塞的横截面面积小于第一导电塞的横截面面积；对基底的后表面进行背部减薄；在基底的经过背部减薄的后表面中形成第二通孔，第二通孔与第一通孔对准。
在示例实施例中，形成第一通孔的步骤可包括：在基底的前表面上形成第一光致抗蚀剂图案，第一光致抗蚀剂图案具有暴露基底的一部分的开口；利用第一光致抗蚀剂图案作为蚀刻掩模通过激光打孔法或干蚀刻法去除基底的暴露部分。可通过电镀或非电镀覆中的至少一种来形成第一导电塞。
在示例实施例中，形成第一导电塞的步骤可包括：在包括第一通孔的基底的整个前表面上形成种子层，种子层包括铜(Cu)、钨(W)、金(Au)和银(Ag)中的至少一种；在包括种子层的基底的整个表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，形成具有在第一通孔中的开口的第二光致抗蚀剂图案；利用种子层在基底上执行镀覆第一导电材料的电镀和非电镀覆中的至少一种；去除第二光致抗蚀剂图案。
在示例实施例中，可通过电镀和非电镀覆中的至少一种利用第一导电塞作为种子层形成第二导电塞。形成第二导电塞的步骤可包括：在包括第一导电塞的基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，形成具有比第一通孔的横截面面积小的横截面面积的开口的第三光致抗蚀剂图案；利用第一导电塞作为种子层在基底上执行镀覆第二导电材料的电镀和非电镀覆中的至少一种；去除第三光致抗蚀剂图案。
在示例实施例中，可利用锡铅合金(SnPb)通过焊接形成第二导电塞。第一导电塞和第二导电塞可由相同的导电材料形成，第一导电材料和第二导电材料可包括铜(Cu)。第一导电塞和第二导电塞可由不同的导电材料形成，第一导电塞包括铜(Cu)，第二导电塞包括从铝(Al)、钨(W)、金(Au)、银(Ag)和锡铅合金(SnPb)中选择的一种。
在示例实施例中，形成第二通孔的步骤可包括：在经过背部减薄的基底的后表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有暴露基底的一部分并与第一通孔对应的开口的第四光致抗蚀剂图案；利用第四光致抗蚀剂图案作为蚀刻掩模通过激光打孔法或干蚀刻法去除经过背部减薄的基底的暴露部分。
示例实施例涉及一种制造晶片堆叠封装件的方法。该方法包括以下步骤：形成部分地暴露基底的前表面的第一光致抗蚀剂图案，基底包括输入/输出焊盘；利用第一光致抗蚀剂图案作为蚀刻掩模蚀刻基底的前表面以形成第一通孔；去除第一光致抗蚀剂图案；在包括第一通孔的基底的整个表面上形成金属种子层；在包括金属种子层的基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有在第一通孔中的第二光致抗蚀剂图案；利用金属种子层对基底执行电镀和非电镀覆中的至少一种，以形成第一导电塞，第一导电塞包括在第一通孔中的第一部分和从基底的上表面突出的第二部分；去除第二光致抗蚀剂图案；在基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有比第一通孔的横截面面积小的横截面面积的开口的第三光致抗蚀剂图案；利用第一导电塞作为种子层执行电镀和非电镀覆中的至少一种，以在第一导电塞上形成第二导电塞，第二导电塞具有比第一导电塞的横截面面积小的横截面面积；去除第三光致抗蚀剂图案；对基底的后表面进行背部减薄；在经过背部减薄的基底的后表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有与第一通孔对应并暴露基底的一部分的开口的第四光致抗蚀剂图案；利用第四光致抗蚀剂图案作为蚀刻掩模通过蚀刻经背部减薄的基底的后表面来形成第二通孔，第二通孔与第一通孔对准。
在示例实施例中，该方法还可包括以下步骤：利用切割工艺将基底切割为单独的半导体芯片；堆叠所述单独的半导体芯片。
示例实施例涉及一种半导体芯片。所述半导体芯片包括：基底，包括前表面和后表面，基底具有形成在前表面中的第一通孔和形成在后表面中的第二通孔；第一导电塞，形成在基底上，第一导电塞包括形成在第一通孔中的第一部分和从基底的前表面突出的第二部分；第二导电塞，形成在第一导电塞上，第二导电塞的横截面积比第一导电塞的横截面面积小。
在示例实施例中，第一导电塞的第一部分的高度与第二导电塞的高度之和可等于第二通孔的深度。
示例实施例涉及一种半导体芯片。所述半导体芯片包括：基底，包括形成在基底中的通孔；第一导电塞，形成在通孔的上端部中；第二导电塞，形成在通孔的下端部中；第三导电塞，在通孔中形成在第一导电塞和第二导电塞之间。
在示例实施例中，第一导电塞和第二导电塞的高度可以相等，并且关于水平轴对称。
另一示例实施例涉及一种晶片堆叠封装件。所述晶片堆叠封装件包括：下基底，包括形成在下基底的前表面中的第一通孔；上基底，包括形成在上基底的后表面中的第二通孔，第二通孔与第一通孔对准；通孔塞，形成在第一通孔和第二通孔中，以使下基底和上基底电连接。
在示例实施例中，通孔塞至少可包括：第一导电塞，包括形成在第一通孔中的第一部分和从下基底的前表面突出的第二部分；第二导电塞，形成在第一导电塞上，第二导电塞的横截面面积比第一导电塞的横截面面积小。
在示例实施例中，第二导电塞和第一导电塞的第二部分在上基底的第二通孔中，使得下基底中的另一第一导电塞与上基底的第二导电塞电连接。
另一示例实施例涉及一种半导体模块，所述半导体模块包括在模块基底上的多个半导体芯片和与所述多个半导体芯片连接的多个模块接触端子，其中，所述多个半导体芯片中的至少一个包括：基底，包括前表面和后表面，基底具有形成在前表面中的第一通孔和形成在后表面中的第二通孔；第一导电塞，形成在基底上，第一导电塞包括形成在第一通孔中的第一部分和从基底的前表面突出的第二部分；第二导电塞，形成在第一导电塞上，第二导电塞的横截面面积比第一导电塞的横截面面积小。
附图说明
下面参照附图更具体地描述示例实施例。应该理解的是，为了清楚起见，可夸大附图的许多方面。
图1是示出根据本发明构思的示例实施例的晶片堆叠封装件的构造的纵向剖视图。
图2A至图2O是示出半导体芯片的构造来解释图1的晶片堆叠封装件的制造工艺的纵向剖视图。
图3是根据本发明构思的示例实施例的包括晶片堆叠封装件的半导体模块的示意性平面图。
图4是根据本发明构思的示例实施例的包括晶片堆叠封装件的电路板的示意性框图。
图5是根据本发明构思的示例实施例的包括晶片堆叠封装件的电子系统的示意性框图。
具体实施方式
现在将参照附图更充分地描述各种示例实施例，在附图中示出了一些示例实施例。在附图中，为了清楚起见，可夸大层和区域的厚度。
在此公开了详细说明的实施例。然而，仅仅出于描述示例实施例的目的来提供这里详细公开的特定结构和功能。然而，本发明构思可以以许多可选形式来实施，而不应理解为仅局限于这里阐述的示例实施例。
因此，虽然示例实施例能够具有多种修改和可选形式，但是这些示例实施例以示例的方式在附图中示出并将在此详细描述这些实施例。然而，应该理解的是，不意图将示例实施例局限于公开的具体形式，而是相反，示例实施例将覆盖落入本发明构思的范围内的全部修改、等同物和替换物。在整个附图的描述中，相同的标号表示相同的元件。
应该理解的是，尽管在这里可使用术语第一、第二等来描述不同的元件，但是这些元件不应该受这些术语的限制。这些术语仅是用来将一个元件与另一个元件区分开来。例如，在不脱离示例实施例的范围的情况下，第一元件可被命名为第二元件，相似地，第二元件可被命名为第一元件。如在这里使用的，术语“和/或”包括一个或多个相关所列项的任意组合和所有组合。
应该理解的是，当元件被称作“连接到”或“结合到”另一元件时，该元件可直接连接到或结合到另一元件，或者可存在中间元件。相反，当元件被称作“直接连接到”或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其它术语也应以相似的方式解释(例如，“在...之间”与“直接在...之间”，“相邻”与“直接相邻”等)。
这里使用的术语仅为了描述特定实施例的目的，而不意图限制示例实施例。如这里所使用的，除非上下文另外明确指出，否则单数形式也意图包括复数形式。还应理解的是，当在本说明书中使用术语“包含”和/或“包括”时，说明存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或附加一个或多个其它特征、整体、步骤、操作、元件、组件和/或它们的组。为了方便描述，在这里可使用空间相对术语，如“在...之下”、“在...下方”、“下面的”、“在...上方”、“上面的”等，用来描述在图中所示的一个元件或特征与其它元件或特征的关系。应该理解的是，空间相对术语意在包含除了在附图中描述的方位之外的装置在使用或操作中的不同方位。例如，如果在附图中的装置被翻转，则描述为“在”其它元件或特征“下方”或“之下”的元件随后将被定位为“在”其它元件或特征“上方”。因而，例如，术语“在...下方”可包括“在...上方”和“在...下方”两种方位。所述装置可被另外定位(旋转90度或者在其它方位被观察或参照)，并对在这里使用的空间相对描述符做出相应的解释。
在此参照作为示例实施例的理想实施例(和中间结构)的示意图的剖视图来描述示例实施例。这样，预计会出现例如由制造技术和/或公差引起的图示的形状的变化。因此，示例实施例不应该被理解为局限于在此示出的区域的特定形状，而将包括例如由制造导致的形状偏差。例如，示出为矩形的注入区域在其边缘将通常具有圆形或弯曲的特征和/或(例如，注入浓度的)梯度，而不是从注入区域到非注入区域的突然变化。同样，通过注入形成的埋区会导致在埋区和通过其发生注入的表面之间的区域中的一些注入。因此，在图中示出的区域本质上是示意性的，它们的形状并不意图示出装置的区域的实际形状，也不意图限制示例实施例的范围。
还应注意的是，在一些替代实施方式中，所提到的功能/动作可以不按照附图中提到的顺序发生。例如，根据所包含的功能/动作，两幅连续示出的附图实际上可以基本同时地执行，或者有时可以按照相反的顺序执行。
为了更具体地描述示例实施例，将参照附图详细描述各个方面。然而，本发明构思不限于描述的示例实施例。
示例实施例涉及一种半导体芯片和利用该半导体芯片的晶片堆叠封装件。图1是示出根据示例实施例的晶片堆叠封装件的构造的剖视图。
参照图1，根据示例实施例的晶片堆叠封装件100可包括：通孔120，穿过半导体基底110；通孔塞150，形成在通孔120中，使多个半导体芯片100a、100b和100c结合并电连接。
通孔120可包括形成在半导体基底110的前表面F中的第一通孔120a和形成在半导体基底110的后表面R中第二通孔120b。换言之，第一通孔120a和第二通孔120b可形成在半导体基底110的前表面F和后表面R中，并且可对齐以形成通孔120。通孔120可与输入焊盘和输出焊盘112对准，输入焊盘和输出焊盘112中的每个用作外部端子。
这里，术语“前表面”、“后表面”、“上表面”或“下表面”全都是相对术语，它们仅用于简单地确定附图中示出的元件之间的相对位置。应该理解的是，这些相对术语不意图限制元件的位置和方向。
通孔塞150包括形成在半导体基底110的前表面F中的第一导电塞150a和形成在第一导电塞150a上的第二导电塞150b。第一导电塞150a的下部P可位于第一通孔120a中，另一部分Q(即，上部)可从半导体基底110的前表面F突出。第二导电塞150b的横截面面积可被形成为等于或小于第一导电塞150a的横截面面积。
当第二导电塞150b的横截面面积被形成为小于第一导电塞150a的横截面面积时，在竖直地堆叠半导体芯片100a、100b和100c时更容易将第二导电塞150b插入到第二通孔120b中，并且在第二导电塞150b附近形成空间，从而即使在沿竖直方向对第二导电塞150b施加压力时，也为第二导电塞150b沿水平方向的膨胀留有空间。
第一导电塞150a的下部P的高度可与第一通孔120a的深度精确地相等。然而，第一导电塞150a的上部Q的高度与第二导电塞150b的高度之和可与第二通孔120b的深度相等或比第二通孔120b的深度略大。
第一导电塞150a和第二导电塞150b可由具有导电性的不同材料或相同材料形成。例如，第一导电塞150a和第二导电塞150b可均由铜(Cu)形成。第一导电塞150a可由Cu形成，第二导电塞150b可由锡铅合金(SnPb)形成。
当半导体基底110被切分为单独的半导体芯片100a、100b和100c，并且半导体芯片100a、100b和100c被堆叠为晶片堆叠封装件100时，设置在下面的半导体芯片100c或100b的前表面F以及第一导电塞150a的上部Q上的整个第二导电塞150b插入到形成在上面的半导体芯片100b或100a的后表面R中的第二通孔120b中。
例如，在晶片堆叠封装件100中参照通孔120考虑通孔塞150，第二导电塞150b可插入到第一导电塞150a的分别位于通孔120上端的部分P和位于通孔120下端的部分Q之间，并可以以将第二导电塞150b限制在通孔120中的结构来形成。当第一导电塞150a的下部P具有与第一导电塞150a的上部Q相同的高度时，通孔塞150可以以关于水平轴对称的结构形成。相反，当第一导电塞150a的下部P比第一导电塞150a的上部Q高或低时，通孔塞150可以以关于水平轴不对称的结构形成。
在下文中，将参照附图详细描述具有上述构造的半导体芯片的制造方法以及利用该半导体芯片的晶片堆叠封装件的制造方法。
图2A至图2O是用于解释制造半导体芯片和堆叠制造的半导体芯片来制造晶片堆叠封装件的工艺的剖视图。
参照图2A，半导体基底110可被加工为与将要制造的半导体芯片具有相同的特性。该晶片制造工艺是公知的，因此将在这里省略对它的详细描述。
例如，除了传统的硅(Si)基底之外，半导体基底110可包括绝缘体上硅(SOI)基底、砷化镓(GaAs)基底、锗(Ge)基底等。根据半导体芯片的特性，半导体基底110可包括各种安装在其上的有源元件或无源元件。这里，半导体基底110将是完成了芯片形成工艺的Si基底。
作为示例，半导体芯片可包括例如动态随机访问存储器(DRAM)或闪存存储器的存储器件以及例如逻辑芯片或CPU芯片的非存储器件。在存储器件的情况下，可包括仅有同种类存储器件(homogeneous memory device)的组合以及不同种类的存储器件(heterogeneous memory device)的组合。输入/输出焊盘112可形成在半导体基底110上。输入/输出焊盘112可由铝(Al)、钨(W)或其合金形成。
参照图2B，将光致抗蚀剂涂覆在半导体基底110的前表面F上，并使光致抗蚀剂经受曝光工艺和显影工艺。从而，使输入/输出焊盘112的上表面部分地暴露，以形成第一开口O1。因此，形成了具有第一开口O1的第一光致抗蚀剂图案118。
参照图2C，在半导体基底110中形成第一通孔120a。对于形成通孔120a的方法，可使用激光打孔法、湿蚀刻法或干蚀刻法。在本示例实施例中，可使用干蚀刻法。该干蚀刻法可包括反应离子蚀刻(RIE)、磁增强反应离子蚀刻(MERLE)、化学顺流蚀刻(chemical downstream etching，CDE)、电子回旋共振(ECR)、变压器偶合等离子体(TCP)等。
再参照图2C，利用第一光致抗蚀剂图案118作为蚀刻掩模来蚀刻输入/输出焊盘112和半导体基底110。从而形成第一通孔120a。
参照图2D，去除第一光致抗蚀剂图案118。第一通孔120a与将在下面描述的第二通孔120b一起形成穿过半导体基底110的通孔120。第一通孔120a的深度可比半导体基底110的深度小。
如在附图中示出的，第一通孔120a可直接形成在输入/输出焊盘112的中心，然而示例实施例不限于此。例如，第一通孔120a可与输入/输出焊盘112分隔开预定的或给定的距离，可通过再金属化(re-metallization)来使通孔塞(未示出)与输入/输出焊盘112连接。
第一通孔120a可部分地填充有诸如铜(Cu)、铝(Al)或钨(W)的第一导电材料，从而形成第一导电塞150a(见图2F)。在第一导电材料中，可使用具有更低的比电阻的铜(Cu)。可通过沉积来填充钨，可通过电镀来填充Cu。
参照图2E，再次将光致抗蚀剂涂覆到具有第一通孔120a的半导体基底110的前表面F，并使光致抗蚀剂经受曝光和显影工艺。因此，形成具有第二开口O2的第二光致抗蚀剂图案128。第二光致抗蚀剂图案128被用作电镀和非电镀覆中的至少一种的镀覆掩模，而不是蚀刻掩模。
再参照图2E，在涂覆光致抗蚀剂之前，可通过例如物理气相沉积(PVD)在第一通孔120a的内表面上形成种子层130，其中，诸如Cu、W、Au或Ag的金属被沉积在具有第一通孔120a的整个半导体基底110上。通过使用种子层130，可在半导体基底110上形成Cu，并会难以将种子层130的材料与Cu或其它第一导电材料区分开。然而，当利用例如PVD将例如Cu的金属沉积在整个半导体基底110上时，种子层130可至少在第一通孔120a的侧壁和底部被形成得相对薄。
虽然未示出，但是为了防止或减少Cu扩散到半导体基底110中，可在形成种子层130之前利用钛或氮化钛层、钽或氮化钽层等在第一通孔120a的侧壁上形成阻挡层。在下文中，由于难以将种子层130与第一导电塞150a区分开，所以在附图中未示出种子层130。
参照图2F，通过适当地设置镀覆停止时间，第一导电塞150a在第一通孔120a中形成为期望的高度。用于在镀覆工艺中选择和检测镀覆处理时间的技术是公知的，因此将在这里省略对它的详细描述。
然而，第一导电塞150a的上部Q的水平可至少比半导体基底110的上表面的水平高。从半导体基底110的上表面突出的第一导电塞150a的上部Q插入到将要堆叠在半导体基底110上的另一个半导体基底110的通孔120中。
当从半导体基底110的上表面突出的第一导电塞150a的上部Q与嵌入在第一通孔120a中的第一导电塞150a的下部P具有相同的高度时，在各个半导体基底中上下形成的一对第一导电塞150a的高度彼此相同，并因此可关于水平轴对称。相反，当从半导体基底110的上表面突出的第一导电塞150a的上部Q的高度比形成在第一通孔120a中的第一导电塞150a的下部P的高度高时，位于通孔120的下部中的一个第一导电塞150a比另一个第一导电塞150a相对更长，因此可关于水平轴不对称。
参照图2G，可去除第二光致抗蚀剂图案128。这时，可利用湿蚀刻法容易地去除在第一导电塞150a之外的种子层130。
参照图2H，在具有第一导电塞150a的半导体基底110的前表面F上涂覆光致抗蚀剂，然后使光致抗蚀剂经受曝光和显影工艺。从而形成具有第三开口O3的光致抗蚀剂图案138。这里，在尺寸方面，第三光致抗蚀剂图案138的第三开口O3必须等于或小于第二光致抗蚀剂图案128的第二开口O2。
参照图2I，利用第三光致抗蚀剂图案138作为镀覆掩模执行电镀或非电镀覆中的至少一种。从而，可形成第二导电塞150b。然而，由于可利用第一导电塞150a作为种子来镀覆第二导电塞150b，所以可不形成单独的种子层。按这种方式，利用包括铝(Al)、钨(W)、金(Au)、银(Ag)和SnPb中的一种的第二导电材料来填充第三开口O3。从而，可形成第二导电塞150b。
具体地说，除了电镀工艺之外，可通过焊接工艺来焊接SnPb。可以按照通过喷墨或挤压方法来覆盖导体的方式来执行焊接工艺。
参照图2J，可去除第三光致抗蚀剂图案138。当去除第三光致抗蚀剂图案138时，获得了第二导电塞150b堆叠在第一导电塞150a上的结构。
参照图2K，利用背部减薄工艺(back-lapping process)将半导体基底110的后表面R处理为均匀的厚度。为了将半导体基底110形成为适于封装的厚度，将半导体基底110的后表面R(即，非活性表面)进行打磨。这里，虽然未示出，但是为了保护半导体基底110的活性表面并防止或减少半导体基底翘曲，可在半导体基底110的前表面F上形成保护层，并在背部减薄工艺之后去除该保护层。
参照图2L，将光致抗蚀剂涂覆到半导体基底110的后表面R同时使半导体基底110倒置，并使光致抗蚀剂经受曝光和显影工艺。从而形成具有第四开口O4的第四光致抗蚀剂图案148。第四光致抗蚀剂图案148的第四开口O4可具有与图3B的第一开口O1相同的尺寸。与第一通孔120a相似，可利用激光打孔法、湿蚀刻法或干蚀刻法等来形成第二通孔120b。在这些方法中，可使用RIE干蚀刻法。
参照图2M，利用RIE干蚀刻法蚀刻半导体基底110的后表面R。第一导电塞150a用作蚀刻停止层，并且蚀刻在第一导电塞150a的后表面R上停止。可形成与第一通孔120a连通的第二通孔120b。
参照图2N，可去除第四光致抗蚀剂图案148。第一导电塞150a和第二导电塞150b被形成为通孔塞150。按照这种方式，第一导电塞150a和第二导电塞150b用于将如图2O所示的单独的半导体芯片100a、100b和100c沿竖直方向电连接，并且第一导电塞150a和第二导电塞150b可形成在半导体基底110中。
如图2O所示，利用切割工艺(dicing process)将半导体基底110切割为单独的半导体芯片100a、100b和100c。单独的半导体芯片100a、100b和100c可竖直地堆叠以形成晶片堆叠封装件100。例如，从半导体芯片100a、100b和100c中的一个半导体芯片100c的前表面F突出的第二导电塞150b被安装在形成在另一半导体芯片100b的后表面R中的第二通孔120b中，并与另一半导体芯片100b的第一导电塞150a接触。按照这种方式，这些半导体芯片100a、100b和100c可竖直地堆叠并电连接。
此外，可以通过在晶片水平堆叠晶片并切割堆叠的晶片来形成晶片堆叠封装件100。在另一种方法中，可通过利用切割工艺将晶片切割为半导体芯片并堆叠半导体芯片来形成晶片堆叠封装件100。
图3是根据本发明构思的示例实施例的具有半导体芯片的半导体模块的示意性平面图。参照图3，根据本发明构思的示例实施例的半导体模块300包括：模块基底310；多个半导体芯片320，设置在模块基底310上；多个模块接触端子330，在模块基底310的边缘上平行地形成并与半导体芯片320电连接。
模块基底310可以是印刷电路板(PCB)。可使用模块基底310的两面。在图3中，在模块基底310的前面设置8个半导体芯片320，然而这种设置仅仅是说明性的。通常，一个半导体模块包括8个半导体芯片，或者还可包括单独的半导体芯片或用于控制半导体芯片320的封装件。
根据本发明构思的一个示例实施例，半导体芯片320中的至少一个可用作半导体芯片100a、100b和100c或者晶片堆叠封装件100中的至少一个。
图4是根据本发明构思的示例实施例的电路板的示意性框图。参照图4，根据本发明构思的示例实施例的电路板400包括：微处理器420，设置在电路板410上；主存储电路430和辅助存储电路440，与微处理器420通信；输入信号处理电路450，将指令发送至微处理器420；输出信号处理电路460，从微处理器420接收指令；通信信号处理电路470，从另一电路板接收电信号并将电信号发送至另一电路板。每个箭头表示电信号能够通过其传输的通路。
电路板410、微处理器420、主存储电路430、辅助存储电路440、输入信号处理电路450、输出信号处理电路460和/或通信信号处理电路470可包括根据本发明构思的示例实施例半导体芯片100a、100b和100c、晶片堆叠封装件100或者半导体模块300中的至少一个。
图5是根据本发明构思的示例实施例的电子系统的示意性框图。参照图5，根据本发明构思的示例实施例的电子系统500包括：控制单元510，控制整个电子系统500的全部单元；输入单元520，将电指令信号发送到控制单元510；输出单元530，从控制单元510接收电指令信号并输出由电子系统500处理的结果；存储单元540，临时地或永久地存储将被控制单元510处理或已经被控制单元510处理的电信号。此外，电子系统还可包括通信单元550和/或操作单元560，其中，通信单元550从控制单元510接收电指令信号并将电信号发送至另一电子系统或从另一电子系统接收电信号，操作单元560根据控制单元510的指令执行物理或机械操作。
控制单元510、输入单元520、输出单元530、存储单元540、通信单元550和/或操作单元560可包括根据本发明构思的示例实施例的半导体芯片100a、100b和100c、晶片堆叠封装件100或者半导体模块300中的至少一个。
根据本发明构思的示例实施例的电子系统可以是从计算机、网络服务器、网络打印机或扫描仪、无线控制器、移动通信终端、交换系统和/或执行经编程的操作的电子装置中选择的一种。
如上所述，根据示例实施例，可提高半导体芯片的电学性能，并且可提高半导体芯片的结合可靠性。
上面是对示例实施例的说明，而不应理解为对示例实施例的限制。虽然已经描述了一些示例实施例，但是本领域技术人员容易理解，在本质上不脱离该新型教导和优点的情况下，能够对示例实施例进行许多变型。因此，所有这些变型均意图被包括在如权利要求限定的本发明总体构思的范围内。在权利要求书中，功能性限定意图覆盖这里描述的执行所述功能的结构，并且不仅覆盖结构等同物，还覆盖等同结构。因此，应该理解的是，上面是对各种示例实施例的说明，而不应理解为局限于公开的特定实施例，并且对公开的实施例的变型以及其它实施例均意图被包括在权利要求书的范围内。

Claims (10)

1.一种制造半导体芯片的方法，所述方法包括以下步骤：
在基底的前表面中形成第一通孔；
利用第一导电材料在第一通孔中形成第一导电塞，第一导电塞包括在基底中的第一部分和从基底突出的第二部分；
利用第二导电材料在第一导电塞的上表面上形成第二导电塞，第二导电塞的横截面面积小于第一导电塞的横截面面积；
对基底的后表面进行背部减薄；
在基底的经过背部减薄的后表面中形成第二通孔，第二通孔与第一通孔对准并连通。
2.如权利要求1所述的方法，其中，形成第一通孔的步骤包括：
在基底的前表面上形成第一光致抗蚀剂图案，第一光致抗蚀剂图案具有暴露基底的一部分的开口；
利用第一光致抗蚀剂图案作为蚀刻掩模通过激光打孔法或干蚀刻法去除基底的暴露部分。
3.如权利要求1所述的方法，其中，通过电镀或非电镀覆中的至少一种来形成第一导电塞。
4.如权利要求3所述的方法，其中，形成第一导电塞的步骤包括：
在包括第一通孔的基底的整个前表面上形成种子层，种子层包括铜、钨、金和银中的至少一种；
在包括种子层的基底的整个表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，形成具有在第一通孔中的开口的第二光致抗蚀剂图案；
利用种子层在基底上执行镀覆第一导电材料的电镀和非电镀覆中的至少一种；
去除第二光致抗蚀剂图案。
5.如权利要求1所述的方法，其中，通过电镀和非电镀覆中的至少一种利用第一导电塞作为种子层形成第二导电塞。
6.如权利要求5所述的方法，其中，形成第二导电塞的步骤包括：
在包括第一导电塞的基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，形成具有比第一通孔的横截面面积小的横截面面积的开口的第三光致抗蚀剂图案；
利用第一导电塞作为种子层在基底上执行镀覆第二导电材料的电镀和非电镀覆中的至少一种；
去除第三光致抗蚀剂图案。
7.如权利要求1所述的方法，其中，利用锡铅合金通过焊接形成第二导电塞。
8.如权利要求1所述的方法，其中，第一导电塞和第二导电塞由不同的导电材料形成，
第一导电塞包括铜，第二导电塞包括从铝、钨、金、银和锡铅合金中选择的一种。
9.如权利要求1所述的方法，其中，形成第二通孔的步骤包括：
在经过背部减薄的基底的后表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有暴露经过背部减薄的基底的一部分并与第一通孔对应的开口的第四光致抗蚀剂图案；
利用第四光致抗蚀剂图案作为蚀刻掩模通过激光打孔法或干蚀刻法去除经过背部减薄的基底的暴露部分。
10.一种制造晶片堆叠封装件的方法，所述方法包括以下步骤：
形成部分地暴露基底的前表面的第一光致抗蚀剂图案，所述基底包括输入/输出焊盘；
利用第一光致抗蚀剂图案作为蚀刻掩模形成第一通孔；
去除第一光致抗蚀剂图案；
在包括第一通孔的基底的整个表面上形成金属种子层；
在包括金属种子层的基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有在第一通孔中并暴露金属种子层的一部分的开口的第二光致抗蚀剂图案；
利用金属种子层对基底执行电镀和非电镀覆中的至少一种，以形成第一导电塞，第一导电塞包括在第一通孔中的第一部分和从基底的前表面突出的第二部分；
去除第二光致抗蚀剂图案；
在基底的前表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有比第一通孔的横截面面积小的横截面面积并暴露第一导电塞的一部分的开口的第三光致抗蚀剂图案；
利用第一导电塞作为种子层执行电镀和非电镀覆中的至少一种，以在第一导电塞上形成第二导电塞，第二导电塞具有比第一导电塞的横截面面积小的横截面面积；
去除第三光致抗蚀剂图案；
对基底的后表面进行背部减薄；
在经过背部减薄的基底的后表面上涂覆光致抗蚀剂，并对光致抗蚀剂进行曝光和显影，以形成具有与第一通孔对应并暴露基底的一部分的开口的第四光致抗蚀剂图案；
利用第四光致抗蚀剂图案作为蚀刻掩模在基底中形成第二通孔，第二通孔与第一通孔对准并连通。
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