CN102113114A - 互补型逻辑门器件 - Google Patents
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Abstract
本发明提供一种用于打破半导体集成逻辑电路，尤其是以硅CMOS(互补型金属氧化膜半导体)逻辑电路为代表的互补型逻辑门器件构成的超高集成、超低功耗型集成逻辑电路的速度性能极限的互补型逻辑门器件。不使用N沟道FET和P沟道FET，只利用由石墨烯33形成电子运行层，具有双极特性，且门限值不同的第一FET 1和第二FET 2的两个FET。将第一FET 1的栅极11和第二FET 2的栅极21短路连接作为输入端，将第一FET 1的源极12设为低电位；将第一FET 1的漏极13和第二FET 2的漏极22连接作为输出端，将第二FET 2的漏极23设为高电位。
Description
技术领域
本发明涉及一种互补型逻辑门器件，该互补型逻辑门器件用于打破半导体集成逻辑电路，尤其是以硅CMOS(互补型金属氧化膜半导体)逻辑电路为代表的互补型逻辑门器件构成的超高集成、超低功耗型集成逻辑电路的速度性能极限。
背景技术
由于硅CMOS逻辑门器件兼具超高集成性和超低功耗性能，所以成为当今半导体集成电路技术的核心。如图6所示的现有技术的逻辑门器件的结构例，CMOS逻辑门具有下述特征，如图7所示的工作电流、输出电压特性，通过将N沟道MOSFET(金属氧化物半导体场效应管)和P沟道MOSFET组合起来互补性工作，使输入输出逻辑电平在低电平及高电平时，工作电流不流动，仅在逻辑电平迁移期间，工作电流流动，由此得到超低功耗性能。通常，MOSFET利用所谓的沟道掺杂技术掺杂施主或受主杂质，形成N型半导体及P型半导体。
迄今为止，通过利用元件的微型化来缩短电子空穴在电极间移动的距离和时间，提高晶体管FET进而提高逻辑门器件的速度。但是，在FET(场效应管)的特征尺寸逼近引起量子力学隧道效应的10nm的今天，已经难以通过元件的微型化来实现高速化。为此，与当前所利用的以硅为代表的半导体材料相比，导入可高速传输电子空穴的载荷传输特性优异的材料，已逐渐成为提高速度的有效方法。
在这样的背景下，由于构成六环结构的碳的单层薄膜：石墨烯与现有的所有半导体相比，电子传输特性非常优异，所以作为可飞跃式提高微型化极限所面临的晶体管性能的速度性能的新型半导体材料而备受关注。石墨烯是价电子带的最高点在K点，与传导带的最低点相接。即，不存在带间隙。同时，由于在K点附近，传导带、价电子带均具有对称的线性分散特性，因此电子/空穴均不存在有效质量，所以，电子迁移率与以往的半导体材料相比提高了一个位数以上，而且空穴迁移率也是如此，具有以往半导体材料不能实现的优异的载荷传输特性(例如，参考非专利文献1、2、3)。
但是，由于下述2点，石墨烯不能直接置换MOSFET来实现与CMOS等效的逻辑工作。第1，杂质的掺杂极其困难，仅具有所谓的本征半导体特性，很难实现具有充分载荷浓度的N型或P型半导体特性(例如，参考非专利文献1、4、5)。第2，由于石墨烯不存在带间隙，而电子空穴同样存在，所以FET工作具有所谓的双极特性(单极双向特性)，即：兼具在栅极偏置高于栅极门限值电位时，以电子模式工作的区域与在栅极偏置低于栅极门限值电位时，以空穴模式工作的区域。因此，即使栅极值偏置低于门限值，FET也不会成为截止状态(例如，参考非专利文献6、7、8、9)。基于上述理由，将石墨烯材料用作电子运行层(沟道)的FET至今不能实现由P沟道FET和N沟道FET所构成的CMOS逻辑门结构，因此，也不能构成与现在的可实现超低功耗、超大规模集成的CMOS互换的互补型门电路。
现有技术文献
【非专利文献】
【非专利文献1】K.S.Novoselov，et al.，“Two-dimensional gas ofmassless Dirac fermions in graphene”，Nature，10 November 2005，Vol.438，p.197-200
【非专利文献2】Mikhail I.Katsnelson，“Graphene：carbon in twodimensions”，Materials today，January 2007，Vol.10，No.1-2，p.20-27
【非专利文献3】安藤恒也，“石墨稀的特异物理”，表面科学，2008，Vol.29，No.5，p.296-303
【非专利文献4】M.I.Katsnelson，et al.，“Chiral tunnelling and theKlein paradox in graphene”，Nature Physics，September 2006，Vol.2，p.620-625
【非专利文献5】Yu-Ming Lin，et al.，“Chemical Doping ofGraphene Nanoribbon Field-Effect Devices”，66th Device ResearchConference Digest，Santa Barbara，CA，June 2008，p.27-28
【非专利文献6】Barbaros Ozyilmaz，et al.，“Electronic transport inlocally gated graphene nanoconstrictions”，Physical Review Letters，2007，Vol.98，Iss.206805
【非专利文献7】Max C.Lemme，et al.，“A Graphene Field-EffectDevice”，IEEE Electron Device Letters，April 2007，Vol.28，No.4，p.282-284
【非专利文献8】Walt A.de Heer，et al.，“Pionics：the EmergingScience and Technology of Graphene-based Nanoelectronics”，International Electron Device Meeting(IEDM)Technical Digest，Washington DC.，Dec.2007，p.199-202
【非专利文献9】Zhihong Chen and Phaedon Avouris，“Semiconducting Graphene Ribbon Transistor”，65th Device ResearchConference Digest，Notre Dome，June 2007，p.265-266
发明内容
(一)发明目的
本发明的目的在于，解决现有问题，提供一种用于打破半导体集成逻辑电路，尤其是以硅CMOS(互补型金属氧化膜半导体)逻辑电路为代表的互补型逻辑门器件构成的超高集成、超低功耗型集成逻辑电路的速度性能极限的互补型逻辑门器件。
(二)技术方案
为了实现上述目的，本发明所涉及的互补型逻辑门器件，其特征在于，利用石墨烯材料形成电子运行层，具有双极特性，且具有门限值不同的第一FET和第二FET，将上述第一FET的栅极和上述第二FET的栅极短路连接，作为输入端，将上述第一FET的源极设成低电位，将上述第一FET的漏极和上述第二FET的源极连接，作为输出端，将上述第二FET的漏极设成高电位。
本发明所涉及的互补型逻辑门器件优选不使用N沟道FET和P沟道FET，仅使用具有双极特性(单极双向特性)且门限值不同的2个FET，将2个FET的栅极短路连接作为输入端，将第一FET的源极设成低电位，将上述第一FET的漏极和第二FET的源极连接作为输出端，将上述第二FET的漏极设成高电位。另外，上述第一FET及上述第二FET优选为仅由以石墨烯为原材料的本征状态的半导体形成电子运行层。
本发明所涉及的互补型逻辑门器件优选为将上述第一FET的门限值设成第一电平，将上述第二FET的门限值设成第二电平，且第二电平高于上述第一电平，使输入信号的逻辑低电平及逻辑高电平分别与上述第一电平及上述第二电平一致。
本发明所涉及的互补型逻辑门器件，上述第一FET及上述第二FET分别是上述电子运行层被夹在一对绝缘层之间，在一绝缘层的表面形成第一栅极，在另一绝缘层的表面形成第二栅极，利用施加给上述第一栅极的电压，可控制上述的门限值电压，利用施加给上述第二栅极的电压来控制上述电子运行层内的电流。
本发明所涉及的互补型逻辑门器件中，上述第一FET及上述第二FET分别是把电子运行层夹在绝缘性薄层之间，在半导体绝缘层的反面形成第一栅极，在另一绝缘层的反面形成第二栅极，利用施加给上述第一栅极的电压，控制各个门限值电压，利用施加给上述第二栅极的电压，控制电子运行层内的电流。
(三)有益效果
本发明不使用N型、P型半导体，以及P沟道FET和N沟道FET，而是将石墨烯导入到FET的电子运行层(将其称为石墨烯沟道FET)，有效利用石墨烯材料所具有的双极特性(以电子模式和空穴模式进行工作的单极双向特性)，用门限值不同的2个石墨烯沟道FET，置换现有的CMOS逻辑门的P沟道FET和N沟道FET，从而实现与CMOS等效的互补逻辑工作。
附图说明
图1表示本发明的第一实施例互补型逻辑门器件的电路图。
图2表示图1所示的互补型逻辑门器件第一及第二FET电流电压特性的图。
图3表示通过对图1所示的互补型逻辑门器件的数值分析所得出的工作电流输出电压特性的图。
图4表示通过对图1所示的互补型逻辑门器件的数值分析所得出的输入输出电压特性的图。
图5表示本发明的第二实施例互补型逻辑门器件的第一及第二FET结构的截面图。
图6表示利用现有的硅CMOS构成的互补型逻辑门器件的电路图。
图7表示利用现有的硅CMOS构成的互补型逻辑门器件的工作电流输出电压特性的图。
图标说明：
1：第一FET 11：栅极
12：源极 13：漏极
2：第二FET 21：栅极
22：源极 23：漏极
31：半导体基板 32：绝缘膜
33：石墨稀 34：绝缘层
具体实施方式
下面结合附图就本发明互补型逻辑门器件的实施例进行说明。
图1表示本发明第一种实施例的互补型逻辑门器件的结构例。例如：预备像利用石墨烯形成电子运行层那样的、具有双极特性(单极双向特性)，且门限值不同的第一FET1及第二FET2的2个FET。如果将第一FET1及第二FET2的门限值电压分别设成Vth1，Vth2，则第一FET1及第二FET2的漏极电流-漏极电压特性具有所谓的单极双向特性，即如图2所示的本发明的第一实施例的互补型逻辑门器件的FET电流电压特性，兼具分别以Vth1、Vth2为边界，在区域Vds＞Vth1，2上为电子传输的FET特性，在区域Vds＜Vth1，2上为空穴传输的FET特性。
如图1所示连接上述第一FET1及第二FET2，构成互补反相器逻辑门。即，将第一FET1的栅极11和第二FET2的栅极21短路作为输入端，将第一FET1的源极12设成低电位，将第一FET1的漏极13和第二FET2的源极22连接作为输出端，将第二FET2的漏极23设成高电位。在与一般CMOS逻辑门同样的电源条件下，即第一FET1的源极12接地，对第二FET2的漏极23施加电源电压Vdd的情况进行说明。在此情况下，分别将Vth1设定为第一FET1的源极电位0V，将Vth2设定为第二FET2的漏极电压Vdd。另外，第一FET1及第二FET2的沟道电阻在导通状态下理想为零，在截止状态下理想为无限大。
图3表示将Vdd＝2.5V时的在漏极偏置为0V(＝Vth1)至Vdd(＝Vth2)的范围，第一FET1的电子模式的电流电压特性(从横轴0V至向右上方的扫帚状特性)和第二FET2的空穴模式的电流电压特性(从横轴Vdd至向左上方的扫帚状特性)勾画在一起。横轴读成第一FET1的漏/源极电位，即输出电位Vout。需要注意的是，由于该逻辑门的输入电位及输出电位同时满足图3所示的第一FET1及第二FET2的任何一个FET的电流电压特性，所以第一FET1及第二FET2的电流电压特性的交点则成为工作点。
当输入端施加电位为0V时，第一FET1由于其栅极电位与Vth1相等，所以为截止状态，第二FET2由于其栅极电位一直比Vth2(仅Vdd)低，所以为空穴模式的导通状态。因此，此时的工作点是图3中的1(圆圈数字)，输出电位与处于导通状态的第二FET2的漏极电位Vdd相等。由于第一FET1为截止状态，所以漏极电流(即，逻辑门的工作电流)不流动。
将输入电位从0V逐渐升高，则第一FET1栅极电位从Vth1逐渐升高，所以呈电子模式的导通状态，漏电流变大。第二FET2栅极电位逐渐接近Vth2，所以空穴模式的导通状态渐渐转向截止状态，漏极电流变小。由于满足上述两个条件，第一FET1的漏电流变得与第二FET2的漏电流相等，所以如图3所示，经2(圆圈数字)～5(圆圈数字)所示的工作点，输出电位从Vdd逐渐降低。
输入电位达到Vdd时，由于第一FET1成为导通状态，第二FET2成为截止状态，所以工作点为图3中的6(圆圈数字)，输出电位与第一FET1的源极电位相同为0V。此时，逻辑门的工作电流不流动。
图4表示假定图3所示的电流电压特性，对该逻辑门器件的输入输出电压特性进行数值分析的结果。在本器件中，如果将逻辑低电平输入赋予第一FET1的门限值Vth1(＝0V)，将逻辑高电平输入赋予第二FET2的门限值Vth2(＝Vdd)，则可得到逻辑反相输出，即可得到逻辑高电平输出Vth2(＝Vdd)，逻辑低电平输出Vth1(＝0V)，而且，可以实现与CMOS反相器逻辑门完全等效的互补逻辑工作，即逻辑电平为高/低电平时，工作电流不流动，仅在逻辑电平迁移期间，工作电流流动。
作为实现上述的逻辑门器件的方法，正如图5所示的本发明的第二实施例中的第一FET1及第二FET2的结构例那样，可形成具有单极双向特性，并且利用背栅电位可控制门限值的FET结构。在半绝缘性的半导体基板31上作为绝缘膜32例如生成SiC，在其上面的晶体管形成区域内作为电子运行层形成石墨烯33。石墨烯33的两端形成源极12、22，漏极13、23。在晶体管形成部的SiC的下面形成导电性的第一栅极11a、21a。这是一般被称作背栅的栅极。另一方面，在石墨烯33的上面介于绝缘层34形成第二栅极11b、21b。这是一般被称作顶栅的栅极。第一栅(背栅)极11a、21a用于控制门限值，第二栅(顶栅)极11b、21b作为普通的栅极用于控制漏电流。下面对其进行说明。
首先，由石墨烯33形成第一FET1及第二FET2的电子运行层，因石墨烯固有的特性可以实现单极双向特性。其次，通过施加给第一栅(背栅)极11a、21a的电位，可以调制电子运行层内的电子/空穴浓度，如果不在第二栅(顶栅)极11b、21b上施加仅抵消因向第一栅(背栅)极11a、21a施加电位而在电子运行层内诱发产生的电子或空穴电荷的电位，就不能实现电子运行层内的载荷中性条件。即，这意味着门限值仅偏移了施加在第一栅(背栅)11a、21a极的电位部分。因此，通过施加给第一栅(背栅)11a、21a的偏置电位，可以控制第一FET1及第二FET2的门限值。而且，石墨烯材料显示出电子/空穴完全对称的传输特性，在理想情况下有效质量消失，从而实现电子/空穴均与一般的硅半导体相比，具有2位数以上，与化合物半导体相比，具有1位数以上的高迁移率，这个已经从理论、实验两方面得到了验证。因此，在可以实现如现有的硅CMOS逻辑集成电路那样，超高集成和超低功耗的同时，同时还可实现大幅度提高现有的硅CMOS逻辑集成电路的工作速度的、极其优良的超高速性能。
另外，作为FET门限值的控制方法，除了上述之外，通过适用一般公知的绝缘膜厚度控制，选择工作函数不同的门金属材料等技术，当然也可以实现。
根据本发明，既可享有石墨烯材料所具有的超高速特性，又可同时实现现有的CMOS集成电路所具有的超低功耗、超高集成特性。本发明是解决当前半导体技术路线图面临的技术饱合的突破点的、极其有力的发明。
Claims (3)
1.一种互补型逻辑门器件，其特征在于：
具有利用石墨烯材料形成电子运行层，有双极特性，且门限值不同的第一FET和第二FET，将上述第一FET的栅极和上述第二FET的栅极短路连接作为输入端，将上述第一FET的源极设为低电位；将上述第一FET的漏极和上述第二FET的源极连接作为输出端，将上述第二FET的漏极设为高电位。
2.如权利要求1所述的互补型逻辑门器件，其特征在于：
将上述第一FET门限值设为第一电平，将上述第二FET的门限值设为高于上述第一电平的第二电平，使输入信号的逻辑低电平及逻辑高电平分别与上述第一电平及上述第二电平一致。
3.如权利要求1或2所述的互补型逻辑门器件，其特征在于：
上述第一FET及上述第二FET，分别是上述电子运行层被夹在一对绝缘层之间，在一绝缘层的表面形成第一栅极，在另一绝缘层的表面形成第二栅极，利用施加给上述第一栅极的电压，可控制上述门限值电压，利用施加给上述第二栅极的电压来控制上述电子运行层内的电流。
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| US20110156007A1 (en) | 2011-06-30 |
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| KR20110050621A (ko) | 2011-05-16 |
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