CN105679821B - 一种超薄沟道凹槽隧穿场效应晶体管 - Google Patents
一种超薄沟道凹槽隧穿场效应晶体管 Download PDFInfo
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Abstract
本发明公开了一种超薄沟道凹槽隧穿场效应晶体管,由栅极、源区、漏区、第一沟道区、第二沟道区、栅介质层、第一隔离层、第二隔离层以及埋氧层；其中，所述栅极与栅介质层位于沟道区之上位置，栅极两侧为隔离层。该新结构具有一个超薄的沟道这样可以增强栅极和沟道的耦合，从而增强栅极的控制能力进而增加器件的隧穿电流。该结构的另一个特征就是将沟道的本征区(低掺杂区)延伸到了漏极区。总之，该结构器件相对于传统的隧穿晶体管在亚阈值摆幅、开关电流比等电学特性以及稳定性方面都有较明显改善。
Description
技术领域
本发明涉及半导体集成电路用器件,主要是一种超薄沟道凹槽场效应晶体管。
背景技术
随着集成电路的发展，要求电路集成度也要随着不断地提高，进而要求半导体器件的特征尺寸要不断地缩小。然而器件在小尺寸下将面临一些严重的问题，例如MOSFET，它是构成集成电路最基本的器件之一，在较小特征尺寸下将会出现短沟道效应，漏致势垒降低效应等不良现象，这些效应会增加器件的功耗甚至会使器件不能有效的开关即失效。目前降低功耗的常用的方法是在保证驱动电流的情况下减小工作电压，这就意味着减小器件的阈值电压。然而，当MOSFET在其特征尺寸小于45纳米时，由于受到短沟道效应和亚阈值摆幅自身极限的影响，减小器件的工作电压将不能够有效的降低器件的功耗。为了解决集成电路功耗问题，研究人员提出了一种基于量子隧穿效应工作的全新的半导体器件，称它为隧穿场效应晶体管(TFET)。TFET器件具有较低的泄漏电流和较小的亚阈值摆幅，可以有效地解决功耗问题。
在特征尺寸较大的TFET器件中，尽管栅工程和沟道工程被用来提高器件的开态电流、降低器件的亚阈值摆幅和消除双极电流。但是当TFET器件的特征尺寸减小到亚20纳米后，载流子在漏极电压的作用下由源极区直接隧穿到达漏极区，导致较大的泄漏电流即器件中出现短沟道效应。在较大的特征尺寸的TFET器件中增强栅控能力可以比较有效的抑制短沟道效应。当特征尺寸减小亚10纳米后，单纯的通过增加栅控能力已经很难有效的降低短沟道效应。要使TFET器件能够作为理想的开关器件应用在未来的低功耗集成电路中，必须缩小其特征尺寸来满足未来硅基CMOS技术节点的要求，所以较小特征尺寸的TFET器件尤其是亚10纳米器件的研究非常必要。
发明内容
本发明针对现有技术的不足，提出了一种新的器件结构，这里我们称该结构为超薄沟道凹槽隧穿场效应晶体管，该结构具有一个超薄的沟道这样可以增强栅极和沟道的耦合，从而增强栅极的控制能力进而增加器件的隧穿电流。该结构的另一个特征就是将沟道的本征区(低掺杂区)延伸到了漏极区。当器件处于关态时可以减小隧穿结处的电场并且增大了隧穿势垒宽度，因此能够有效的减小器件的关态泄漏电流。通过仿真验证了超薄沟道凹槽隧穿晶体管在较小特征尺寸时通过调整漏极区本征层的厚度可以有效的抑制短沟道效应。总之，该新结构相对于传统的隧穿晶体管在亚阈值摆幅、开关电流比等电学特性以及稳定性方面都有所改善。
实现本发明目的技术方案：
本发明一种超薄沟道凹槽隧穿场效应晶体管，特征在于：包括栅极、源区、漏区、第一沟道区、第二沟道区、栅介质层、第一隔离层以及埋氧层；所述的栅极下方设有栅介质层，栅极与栅介质层位于第一沟道区上，第一隔离层将栅极与源区隔离开，第二隔离层将栅极与漏区隔离开；第一隔离层和第二隔离层的厚度不小于栅介质层的厚度；第二沟道区设置在漏区的下方，源区、第一沟道区、第二沟道区设置在埋氧层上；其中第二沟道区的厚度不小于第一沟道区且不大于源区的厚度。
所述的源区2掺杂浓度为1×1020cm-3。
所述的漏区3掺杂浓度为5×1018—1×1020cm-3。
所述的沟道区4a与沟道区4b的掺杂浓度是一致的，浓度不大于1×1017cm-3。
所述的隔离层6是由空气或者是其它的绝缘介质层构成的。
本发明希望利用超薄的沟道来增强栅极和沟道的耦合，从而增强栅极的控制能力进而增加器件的隧穿电流。同时将沟道的本征区即低掺杂区，延伸到了漏极区，当器件处于关态时可以减小隧穿结处的电场并且增大了隧穿势垒宽度，因此能够有效的减小器件的关态泄漏电流。利用以上作用在较小特征尺寸时可以有效地抑制短沟道效应和增大开关电流比。
附图说明
图1是超薄沟道凹槽隧穿场效应晶体管结构示意图。
图2是超薄沟道凹槽隧穿场效应晶体管与传统隧穿器件转移特性曲线图。
图3是超薄沟道凹槽隧穿场效应晶体管，
图4是传统隧穿器件在不同栅长的转移特性曲线图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚，以下结合附图对本发明进行具体阐述。
如图1所示，一种超薄沟道凹槽隧穿场效应晶体管，特征在于：包括栅极1、源区2、漏区3、第一沟道区4a、第二沟道区4b、栅介质层5、第一隔离层6以及埋氧层7；所述的栅极1下方设有栅介质层5，栅极1与栅介质层5位于第一沟道区4a上，第一隔离层6将栅极1与源区2隔离开，第二隔离层8将栅极1与漏区3隔离开；第一隔离层6和第二隔离层8的厚度不小于栅介质层5的厚度；第二沟道区4b设置在漏区3的下方，源区2、第一沟道区4a、第二沟道区4b设置在埋氧层7上；其中第二沟道区4b的厚度不小于第一沟道区4a且不大于源区2的厚度。
所述的源区2掺杂浓度为1×1020cm-3；所述的漏区3掺杂浓度为5×1018—1×1020cm-3；所述的沟道区4a与沟道区4b的掺杂浓度是一致的，浓度不大于1×1017cm-3；所述的隔离层6是由空气或者是其它的绝缘介质层构成的。
如图2所示，给出了栅长为30纳米时超薄沟道凹槽隧穿场效应晶体管(TSG-TFET)与传统隧穿器件(CSG-TFET)的转移特性曲线，沟道区(4a)和沟道区(4b)厚度相等均为5纳米。通过软件仿真得到：当偏压VGS＝0V且VDS＝0.4V时，器件处于关态，TSG-TFET和CSG-TFET的关态电流分别为3.0×10-17A/μm和3.4×10-17A/μm；当偏压VGS＝0.8V且VDS＝0.4V时，器件处于开态时，TSG-TFET和CSG-TFET的开态电流ION分别为5.8×10-6A/μm和7.6×10-7A/μm，由此可以看出TSG-TFET的开态电流比CSG-TFET提高了将近一个数量级；通过计算我们得到TSG-TFET和CSG-TFET的开态电流与关态电流比ION/IOFF分别为1.9×1011和1.3×1010。TSG-TFET和CSG-TFET的点亚阈值摆幅分别为21.8mV/decade和30.4mV/decade，平均亚阈值摆幅分别为46.2mV/decade和64.8mV/decade，由此可以看出新结构器件比传统结构拥有更加陡峭的亚阈值摆幅。通过以上数据我们可以看出新结构TSG-TFET比CSG-TFET有更大的ION、更高ION/IOFF和更小的亚阈值摆幅，因此TSG-TFET比CSG-TFET在电学特性方面有很大的改善。
如图3、图4所示，给出了不同栅长时超薄沟道凹槽隧穿场效应晶体管与传统隧穿器件的转移特性曲线。由于隧穿晶体管关态时的隧穿势垒宽度主要受器件沟道长度影响，并且随着隧穿晶体管栅长的不断缩小，隧穿势垒宽度会受到漏极电压的影响导致器件的关态泄漏电流和亚阈值摆幅严重退化，因而当隧穿晶体管的特征尺度缩小到亚15纳米时器件的短沟道效应会变得非常明显。随着器件栅长的不断减小超薄沟道凹槽隧穿场效应晶体管相对于传统隧穿器件在栅控方面的优势变得愈加明显，尤其当器件的栅长小于15nm时。当器件栅长为30纳米时超薄沟道凹槽隧穿场效应晶体管和传统隧穿器件都表现出非常好的开关特性，然而器件栅长缩小到10纳米时传统隧穿器件关态泄漏电流迅速增大，而超薄沟道凹槽隧穿场效应晶体管并未出现类似的现象；这主要是由于超薄沟道凹槽隧穿场效应晶体管的有效沟道比传统隧穿器件要大很多所以超薄沟道凹槽隧穿场效应晶体管在抑制短沟道效应方面有着显著的优势。
以上所述仅为本发明的较佳实施例，凡依本发明权利要求范围所做的均等变化与修饰，皆应属本发明权利要求的涵盖范围。
Claims (5)
1.一种超薄沟道凹槽隧穿场效应晶体管，特征在于：包括栅极(1)、源区(2)、漏区(3)、第一沟道区(4a)、第二沟道区(4b)、栅介质层(5)、第一隔离层(6)以及埋氧层(7)；所述的栅极(1)下方设有栅介质层(5)，栅极(1)与栅介质层(5)位于第一沟道区(4a)上，第一隔离层(6)将栅极(1)与源区(2)隔离开，第二隔离层(8)将栅极(1)与漏区(3)隔离开；第一隔离层(6)和第二隔离层(8)的厚度不小于栅介质层(5)的厚度；第二沟道区(4b)设置在漏区(3)的下方，源区(2)、第一沟道区(4a)、第二沟道区(4b)设置在埋氧层(7)上；其中第二沟道区(4b)的厚度不小于第一沟道区(4a)且不大于源区(2)的厚度。
2.根据权利要求1所述一种超薄沟道凹槽隧穿场效应晶体管，特征在于：源区(2)掺杂浓度为1×1020cm-3。
3.根据权利要求1所述一种超薄沟道凹槽隧穿场效应晶体管，特征在于：漏区(3)掺杂浓度为5×1018—1×1020cm-3。
4.根据权利要求1所述一种超薄沟道凹槽隧穿场效应晶体管，特征在于：第一沟道区(4a)与第二沟道区(4b)的掺杂浓度是一致的，浓度不大于1×1017cm-3。
5.根据权利要求1所述一种超薄沟道凹槽隧穿场效应晶体管，特征在于：隔离层(6)是绝缘介质层构成的。
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| US5869847A (en) * | 1995-07-19 | 1999-02-09 | The Hong Kong University Of Science & Technology | Thin film transistor |
| US6617643B1 (en) * | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
| CN104576721A (zh) * | 2014-12-23 | 2015-04-29 | 电子科技大学 | 一种具有电场集中效果增强开态电流的隧穿场效应晶体管 |
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| JP2006147805A (ja) * | 2004-11-18 | 2006-06-08 | Matsushita Electric Ind Co Ltd | 半導体装置 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5869847A (en) * | 1995-07-19 | 1999-02-09 | The Hong Kong University Of Science & Technology | Thin film transistor |
| US6617643B1 (en) * | 2002-06-28 | 2003-09-09 | Mcnc | Low power tunneling metal-oxide-semiconductor (MOS) device |
| CN104576721A (zh) * | 2014-12-23 | 2015-04-29 | 电子科技大学 | 一种具有电场集中效果增强开态电流的隧穿场效应晶体管 |
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