JPWO2010010944A1 - 相補型論理ゲート装置 - Google Patents
相補型論理ゲート装置 Download PDFInfo
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- JPWO2010010944A1 JPWO2010010944A1 JP2010521747A JP2010521747A JPWO2010010944A1 JP WO2010010944 A1 JPWO2010010944 A1 JP WO2010010944A1 JP 2010521747 A JP2010521747 A JP 2010521747A JP 2010521747 A JP2010521747 A JP 2010521747A JP WO2010010944 A1 JPWO2010010944 A1 JP WO2010010944A1
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- 230000000295 complement effect Effects 0.000 title claims abstract description 31
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 32
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 30
- 239000000463 material Substances 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 abstract description 22
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 10
- 229910052710 silicon Inorganic materials 0.000 abstract description 10
- 239000010703 silicon Substances 0.000 abstract description 10
- 239000010410 layer Substances 0.000 description 23
- 238000005516 engineering process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 101100484930 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) VPS41 gene Proteins 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000005513 bias potential Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005525 hole transport Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8228—Complementary devices, e.g. complementary transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/8213—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using SiC technology
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/734—Fullerenes, i.e. graphene-based structures, such as nanohorns, nanococoons, nanoscrolls or fullerene-like structures, e.g. WS2 or MoS2 chalcogenide nanotubes, planar C3N4, etc.
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
図1に、本発明の第1の実施形態を示す相補型論理ゲート装置の構成例を示す。例えば、グラフェンを電子走行層で形成して成るような、アンバイポーラ特性(単極双方特性)を有し、かつしきい値の異なる第1のFET1および第2のFET2の2個のFETを用意する。第1のFET1および第2のFET2のしきい値電圧をそれぞれVth1,Vth2とすると、第1のFET1および第2のFET2のドレイン電流−ドレイン電圧特性は、図2に示す本発明の第1の実施形態を示す相補型論理ゲート装置のFET電流電圧特性のように、それぞれ、Vth1,Vth2を境に、領域:Vds>Vth1,2の電子輸送によるFET特性と、領域:Vds<Vth1,2のホール輸送によるFET特性とを併せ持つ、いわゆる単極双方特性を有している。
= Vdd)、論理ローレベル出力:Vth1( = 0V)が得られることになり、しかも、CMOSインバータ論理ゲートと全く等価な、論理レベルがハイ・ローレベルのときには動作電流が流れず、論理レベルが遷移している間にのみ電流が流れるという、相補型論理動作が実現できる。
11 ゲート電極
12 ソース電極
13 ドレイン電極
2 第2のFET
21 ゲート電極
22 ソース電極
23 ドレイン電極
31 半導体基板
32 絶縁膜
33 グラフェン
34 絶縁層
Claims (3)
- グラフェン材料で電子走行層が形成され、アンバイポーラ特性を有し、かつしきい値の異なる第1のFETと第2のFETとを有し、前記第1のFETのゲート電極と前記第2のFETのゲート電極とを短絡して入力端子とし、前記第1のFETのソース電極を低電位とし、前記第1のFETのドレイン電極と前記第2のFETのソース電極とを接続して出力端子とし、前記第2のFETのドレイン電極を高電位として構成されていることを、特徴とする相補型論理ゲート装置。
- 前記第1のFETのしきい値を第一レベルとし、前記第2のFETのしきい値を前記第一レベルよりも高い第二レベルとし、入力信号の論理ローレベルおよび論理ハイレベルをそれぞれ前記第一レベルおよび前記第二レベルに合致させたことを、特徴とする請求項1記載の相補型論理ゲート装置。
- 前記第1のFETおよび前記第2のFETは、各々、前記電子走行層が1対の絶縁層でサンドイッチされ、一方の絶縁層の表面に第一のゲート電極が形成され、他方の絶縁層の表面に第二のゲート電極が形成され、前記第一のゲート電極に印加する電圧で、前記しきい値の電圧を制御可能であり、前記第二のゲート電極に印加する電圧で、前記電子走行層内の電流を制御可能に構成されていることを、特徴とする請求項1または2記載の相補型論理ゲート装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010521747A JP5424274B2 (ja) | 2008-07-25 | 2009-07-24 | 相補型論理ゲート装置 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008192162 | 2008-07-25 | ||
JP2008192162 | 2008-07-25 | ||
PCT/JP2009/063264 WO2010010944A1 (ja) | 2008-07-25 | 2009-07-24 | 相補型論理ゲート装置 |
JP2010521747A JP5424274B2 (ja) | 2008-07-25 | 2009-07-24 | 相補型論理ゲート装置 |
Publications (2)
Publication Number | Publication Date |
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JPWO2010010944A1 true JPWO2010010944A1 (ja) | 2012-01-05 |
JP5424274B2 JP5424274B2 (ja) | 2014-02-26 |
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Application Number | Title | Priority Date | Filing Date |
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JP2010521747A Expired - Fee Related JP5424274B2 (ja) | 2008-07-25 | 2009-07-24 | 相補型論理ゲート装置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8227794B2 (ja) |
EP (1) | EP2320456A4 (ja) |
JP (1) | JP5424274B2 (ja) |
KR (1) | KR101549286B1 (ja) |
CN (1) | CN102113114B (ja) |
WO (1) | WO2010010944A1 (ja) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5513955B2 (ja) * | 2010-03-31 | 2014-06-04 | 株式会社東芝 | 半導体装置およびその製造方法 |
GB2506558B (en) | 2011-07-22 | 2015-09-02 | Ibm | Tunnel field-effect transistor |
KR101813181B1 (ko) | 2011-08-26 | 2017-12-29 | 삼성전자주식회사 | 튜너블 배리어를 포함하는 그래핀 전계효과 트랜지스터를 구비한 인버터 논리소자 |
KR101878745B1 (ko) | 2011-11-02 | 2018-08-20 | 삼성전자주식회사 | 에어갭을 구비한 그래핀 트랜지스터, 그를 구비한 하이브리드 트랜지스터 및 그 제조방법 |
KR101532311B1 (ko) | 2012-04-27 | 2015-06-29 | 삼성전자주식회사 | 그래핀을 이용한 광검출기와 그 제조방법 |
KR102059131B1 (ko) | 2013-04-05 | 2019-12-24 | 삼성전자주식회사 | 그래핀 소자 및 이의 제조 방법 |
KR102210325B1 (ko) | 2013-09-06 | 2021-02-01 | 삼성전자주식회사 | Cmos 소자 및 그 제조 방법 |
KR102163725B1 (ko) * | 2013-12-03 | 2020-10-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조방법 |
US9431353B2 (en) * | 2014-04-09 | 2016-08-30 | Infineon Technologies Ag | Method for manufacturing a digital circuit and digital circuit |
KR102266615B1 (ko) * | 2014-11-17 | 2021-06-21 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법 |
KR101849360B1 (ko) * | 2016-01-29 | 2018-04-16 | 한화테크윈 주식회사 | 그래핀 기반 적층체 및 이의 제조방법 |
US20220052284A1 (en) * | 2018-12-17 | 2022-02-17 | Sharp Kabushiki Kaisha | Electroluminescence element and display device |
DE102019123555B4 (de) | 2019-09-03 | 2022-12-01 | Infineon Technologies Ag | Physisch obfuskierter schaltkreis |
CN111584484B (zh) * | 2019-12-24 | 2023-09-29 | 苏州大学 | 一种低压、低功率互补电路、一种反相器和一种nand器件 |
CN113472343A (zh) * | 2021-07-14 | 2021-10-01 | 山东大学 | 一种逻辑门的构建方法 |
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JP3379050B2 (ja) * | 1993-11-15 | 2003-02-17 | 富士通株式会社 | 半導体装置 |
JP3420168B2 (ja) * | 2000-04-07 | 2003-06-23 | 株式会社東芝 | 電界効果トランジスタ及びこれを用いた集積化論理回路 |
US20040144972A1 (en) * | 2002-10-04 | 2004-07-29 | Hongjie Dai | Carbon nanotube circuits with high-kappa dielectrics |
JP4501339B2 (ja) * | 2002-11-29 | 2010-07-14 | ソニー株式会社 | pn接合素子の製造方法 |
US7005711B2 (en) | 2002-12-20 | 2006-02-28 | Progressant Technologies, Inc. | N-channel pull-up element and logic circuit |
JP4810650B2 (ja) * | 2004-05-11 | 2011-11-09 | 国立大学法人名古屋大学 | カーボンナノチューブfet |
JP2008135415A (ja) * | 2005-03-17 | 2008-06-12 | Univ Of Tokushima | 電子装置及びその製造方法 |
JP2008135414A (ja) * | 2005-03-17 | 2008-06-12 | Univ Of Tokushima | 電子装置及びその製造方法 |
JP2008135413A (ja) * | 2005-03-17 | 2008-06-12 | Univ Of Tokushima | 半導体装置及びその製造方法 |
JP2007123657A (ja) * | 2005-10-31 | 2007-05-17 | Nec Corp | 半導体装置及びその製造方法 |
US7492015B2 (en) | 2005-11-10 | 2009-02-17 | International Business Machines Corporation | Complementary carbon nanotube triple gate technology |
US7619257B2 (en) * | 2006-02-16 | 2009-11-17 | Alcatel-Lucent Usa Inc. | Devices including graphene layers epitaxially grown on single crystal substrates |
JP5167479B2 (ja) * | 2006-06-13 | 2013-03-21 | 国立大学法人北海道大学 | グラフェン集積回路の製造方法 |
JP4669957B2 (ja) * | 2007-03-02 | 2011-04-13 | 日本電気株式会社 | グラフェンを用いる半導体装置及びその製造方法 |
KR101443215B1 (ko) * | 2007-06-13 | 2014-09-24 | 삼성전자주식회사 | 앰비폴라 물질을 이용한 전계효과 트랜지스터 및 논리회로 |
-
2009
- 2009-07-24 KR KR1020117001072A patent/KR101549286B1/ko not_active IP Right Cessation
- 2009-07-24 EP EP09800458.3A patent/EP2320456A4/en not_active Withdrawn
- 2009-07-24 US US13/054,706 patent/US8227794B2/en not_active Expired - Fee Related
- 2009-07-24 JP JP2010521747A patent/JP5424274B2/ja not_active Expired - Fee Related
- 2009-07-24 WO PCT/JP2009/063264 patent/WO2010010944A1/ja active Application Filing
- 2009-07-24 CN CN200980128161.6A patent/CN102113114B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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EP2320456A1 (en) | 2011-05-11 |
CN102113114A (zh) | 2011-06-29 |
JP5424274B2 (ja) | 2014-02-26 |
US20110156007A1 (en) | 2011-06-30 |
KR101549286B1 (ko) | 2015-09-01 |
US8227794B2 (en) | 2012-07-24 |
EP2320456A4 (en) | 2014-08-06 |
CN102113114B (zh) | 2013-08-28 |
WO2010010944A1 (ja) | 2010-01-28 |
KR20110050621A (ko) | 2011-05-16 |
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