CN102106194B - 具有凹嵌的器件的陶瓷封装衬底 - Google Patents

具有凹嵌的器件的陶瓷封装衬底 Download PDF

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CN102106194B
CN102106194B CN2007800463410A CN200780046341A CN102106194B CN 102106194 B CN102106194 B CN 102106194B CN 2007800463410 A CN2007800463410 A CN 2007800463410A CN 200780046341 A CN200780046341 A CN 200780046341A CN 102106194 B CN102106194 B CN 102106194B
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package substrate
array capacitor
face
integrated circuit
electrically connected
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CN102106194A (zh
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C·帕兰杜茨
D·巴赫
T·利特
L·宾德
K·拉哈克里什南
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Intel Corp
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Abstract

陶瓷封装衬底具有凹槽。这允许那个凹槽中的器件靠近与衬底顶侧附连的管芯，以便获得更好的性能。器件可以是阵列电容器、硅内电压调节器或者其它器件。

Description

具有凹嵌的器件的陶瓷封装衬底
技术领域
背景技术
电容器和其它器件与封装衬底配合使用，以便改进去耦电容、阻抗下垂(droop)和其它性能参数。
发明内容
附图说明
图1是示出根据本发明的一个实施例的管芯(die)封装的截面侧视图。
图2是示出当封装衬底安装到印刷电路板时的管芯封装的截面侧视图。
图3是更详细地示出形成衬底的多层的截面侧视图。
图4是示出层和孔的顶视图。
图5是示出堆叠在一起以形成衬底的层的截面侧视图。
图6是示出层进行了堆叠和煅烧之后的成品衬底的截面侧视图。
图7是示出具有处于凹槽内的两个电器件的管芯封装的截面侧视图。
图8是示出其中两个管芯与封装衬底连接并且两个电器件处于凹槽中的管芯封装的另一实施例的截面侧视图。
图9是示出其中两个管芯与封装衬底连接并且两个器件处于凹槽中的管芯封装的另一实施例的截面侧视图。
图10是示出其中两个管芯与封装衬底连接并且单个器件处于凹槽中的管芯封装的另一实施例的截面侧视图。
图11是示出其中凹槽和器件是在封装衬底的顶部而不是底部的管芯封装的又一实施例的截面侧视图。
具体实施方式
在各种实施例中，描述与下侧具有凹槽以及那个凹槽中具有器件的陶瓷封装衬底相关的设备和方法。以下描述中将描述各种实施例。但是，相关领域的技术人员会知道，可在没有这些具体细节的一种或多种的情况下或者可采用其它替代和/或附加方法、材料或组件来实施各种实施例。在其它情况下，没有详细示出或描述众所周知的结构、材料或操作，以免混淆本发明的各种实施例的若干方面。类似地，为了便于说明，提出了具体数量、材料和配置，以便透彻地理解本发明。然而，即使没有这些具体细节也可实施本发明。此外要理解，附图所示的各个实施例是说明性表示，而不一定按比例绘制。
本说明书中提到“一个实施例”或“实施例”表示结合该实施例所述的具体特征、结构、材料或特性包含在本发明的至少一个实施例中，而不是表示它们存在于每一个实施例中。因此，词组“在一个实施例中”或“在实施例中”在本说明书的各个位置中的出现不一定表示本发明的同一个实施例。此外，具体特征、结构、材料或特性可通过任何适当方式结合在一个或多个实施例中。可包含各种附加层和/或结构，和/或所述特征在其它实施例中可被省略。
各种操作将以最有助于理解本发明的方式依次描述为多个分立操作。但是，描述的顺序不应当被理解为表示这些操作一定是顺序相关的。具体来说，这些操作不需要按照陈述的顺序来执行。所述的操作可按照与所述实施例不同的顺序、连续或并行地执行。可执行各种附加操作，和/或所述操作在附加实施例中可被省略。
图1是示出根据本发明的一个实施例的管芯封装100的截面侧视图。管芯封装100包括管芯102。管芯102可以是微处理器管芯或者另一种类型的集成电路管芯。管芯102与陶瓷封装衬底104连接。任何类型的导电连接器可用于将管芯102与陶瓷封装衬底104连接，包括焊球、触点(land)栅格阵列、金属与金属接合等等。陶瓷封装衬底104包括多层陶瓷基质(matrix)材料，其中设置了导电通孔和迹线。这些通孔和迹线提供管芯102与可连接到封装衬底104的其它组件之间的电通信。
封装衬底104在其底面具有凹槽(recess)150，又称作腔室(cavity)150。凹槽150通过从衬底104的底面向上延伸的凹槽侧壁110和凹面112来限定，凹面112为凹槽150的顶面112。凹槽150可具有任何预期深度和体积。
凹槽150中存在电器件106。在所示实施例中，器件106是阵列电容器，但在其它实施例中，器件106可以是标准电容器、硅内电压调节器、另一种类型的集成电压调节器或者其它器件。
器件106与陶瓷封装衬底104电连接。电连接可通过任何适当的方法来进行。器件106在其顶面上具有导体(连接焊盘(land pad)或者任何其它适当导体)。凹槽150的顶面112中可存在连接焊盘或其它连接点。器件106可通过焊盘或者任何其它方法与凹槽150的顶面112连接。在一个实施例中，这些连接是表面安装——焊球将器件106连接到凹槽150的顶面112的连接盘(land)。
封装衬底104的迹线和通孔将器件106与管芯102电连接。由于器件106处于凹槽150中，所以电信号在器件106与管芯102之间必须传播的距离与器件106的其它布置相比可缩短。与器件106设置成远离管芯102的情况相比，这种缩短的距离可提供更好的性能。例如，陶瓷封装衬底104具有厚度114。在所示实施例中，器件106与管芯102之间的距离116小于衬底104的厚度114。如果器件106处于没有凹槽150的衬底104的底侧，或者设置于衬底104之外(例如当器件106设置在母板时)，则器件106与管芯102之间的电距离会更长，可能降低管芯封装100的性能。
在所示实施例中，凹槽150和凹槽150中的器件106实质上直接在管芯102的下面。凹槽150和器件106的中心实质上直接在管芯102的中心的下面。这可帮助减小电信号在器件106与管芯102之间传播的通路的电长度。在其它实施例中，凹槽150和器件106可以直接在管芯102的下面，但中心不对准。在又一些实施例中，凹槽150和器件106可以不是直接在管芯102的下面；除了缩短电通路距离之外的考虑可产生这些其它布置。
图2是根据本发明的一个实施例示出当封装衬底104安装到印刷电路板(PCB)108时的管芯封装100的截面侧视图。例如，在一个实施例中，PCB 108是计算机系统中的母板，但并不局限于此。封装衬底104通过例如触点栅格阵列、焊球或其它电导体等的任何适当方法与母板连接。因此，管芯102通过封装衬底104与PCB 108电连接。
在所示实施例中，器件106通过器件106的底侧上的连接器直接与PCB 108连接。这些连接器可以是任何适当类型的连接器，例如触点栅格阵列、焊球或其它电导体。器件106可包括过孔，所述过孔从器件106的底面延伸以便允许从器件106的顶面处或附近的电容器、电压调节器或其它电器件到器件106的底面的电连接。
在其它实施例中，在器件106的底面可以没有连接器。器件106而是只可与封装衬底104连接。在这些实施例中，到管芯102和/或PCB 108的任何电连接均通过封装衬底104来进行。
与分布于衬底104的顶面或底面或者设置在例如PCB 108上的其它位置的器件相比，凹槽150中的阵列电容器106或其它器件106的使用可节省空间。衬底104的底面的常规器件要占据空间，并且使该空间不再可由封装衬底104与PCB 108之间的连接使用。PCB 108本身也具有有限的空间。
图3是根据本发明的一个实施例更详细示出形成衬底104的多层的截面侧视图。封装衬底104由多层形成。图3中示出三层302、304和306，但在其它实施例中可使用更多或更少的层。各层302、304、306包括陶瓷基质材料、如氧化铝。各层302、304、306可以实质上没有有机或聚合物材料。在层302中看到，层包括导电迹线310和通孔312，以便允许封装衬底104在管芯102、PCB 108和凹槽105中的器件106之间传递电信号。任何适当的方法可用于对陶瓷层302、304、306形成图案，并且形成导电迹线310和通孔312。例如，可在绿色陶瓷板中冲压孔和凹陷(depression)，以便形成层302、304、306。然后可用导电材料填充迹线310和通孔312的孔和凹陷。
层306包括孔308。一层或多层306中的孔308形成凹槽150。通过与对于通孔312和迹线310的孔和凹痕相同的方式来产生这个孔308。在另一个实施例中，例如层306的层中的孔308可通过与对于通孔312和迹线310的孔和凹痕不同的方式来形成。图4是示出层306和孔308的顶视图。虽然在所示实施例中，孔308为矩形，但它在其它实施例中可具有不同的形状。
在形成层302、304、306之后，将它们堆叠和煅烧，以便形成衬底104。图5是示出堆叠在一起以形成衬底104的层302、304、306的截面侧视图。堆叠的302、304、306层经过煅烧以将其硬化，并且产生最终的封装衬底104。具有孔308的多层306可经过对齐和堆叠，使得孔308共同限定凹槽150。也可使用其它方法来形成衬底104和凹槽150。
图6是根据本发明的一个实施例示出已经堆叠和煅烧层302、304、306之后的成品衬底104的截面侧视图。如图所示，成品衬底104在其顶面具有将衬底104与管芯102电连接的接触盘602，在凹槽150的顶面具有将衬底104与凹槽150中的器件106电连接的接触盘604，并且在衬底104的底面具有将衬底104与PCB 108电连接的接触盘606。在其它实施例中，可使用与盘不同的连接、如引脚或其它适当导体，并且可不同地设置连接。
图7是示出具有处于凹槽内的两个电器件702、704而不是如图1和图2中仅一个器件106的管芯封装100的截面侧视图。一个以上的电器件702、704可垂直堆叠在凹槽150中。例如，在所示实施例中，顶部电器件702是阵列电容器，而底部电器件704是硅内电压调节器。在其它实施例中，器件702、704可以不同。顶部器件702可具有过孔，以便在底部器件704可与其耦合的底面上提供电连接。在一些实施例中，底部器件704可直接与顶部器件702和PCB 108电连接。在其它实施例中，底部器件704可以仅直接与顶部器件702连接，其中与PCB 108的电通信通过顶部器件702和封装衬底104来实现。在其它实施例中，其它连接布置也可以是可能的。虽然所示实施例示出垂直堆叠的器件702、704，但是它们也均可处于凹槽150内，但彼此横向相邻而不是垂直堆叠。
图8是示出其中两个管芯102与封装衬底104连接并且两个电器件106、如两个阵列电容器106处于凹槽150内的管芯封装100的另一个实施例的截面侧视图。在这种实施例中，各器件106可与管芯102对齐，并且为那个管芯102提供电容。虽然示为处于同一凹槽150内，但是各器件106可处于不同凹槽150内。
图9是示出其中两个管芯102与封装衬底104连接并且两个器件106、120处于凹槽150内的管芯封装100的另一个实施例的截面侧视图。在这个实施例中，器件106是阵列电容器，而器件120是硅内电压调节器。在其它实施例中，器件106、120可以不同。不是为各管芯102提供单独的阵列电容器106，而是为两个管芯102提供单个阵列电容器106。类似地，不是为各管芯102提供单独的硅内电压调节器120，而是为两个管芯102提供单个硅内电压调节器120。虽然示为处于同一凹槽150内，但是各器件106、120可处于不同凹槽150内。虽然所示实施例示出彼此相邻地水平设置的器件106、120，但是它们也均可处于凹槽150内，但相互垂直堆叠。
图10是示出其中两个管芯102与封装衬底104连接并且单个器件106处于凹槽150内的管芯封装100的另一个实施例的截面侧视图。在所示实施例中，器件是阵列电容器106，但在其它实施例中，它可以是不同类型的电器件。不是为各管芯102提供单独的阵列电容器106，而是为两个管芯102提供单个阵列电容器106。
图11是示出其中凹槽105和器件106是在封装衬底104的顶部而不是底部的管芯封装100的又一个实施例的截面侧视图。在这个实施例中，器件106直接与封装衬底105和管芯102连接。管芯102直接与封装衬底104和器件106电连接。在其它实施例中可存在其它连接布置。一个或多个管芯102、一个或多个凹槽150和一个或多个器件106的各种布置都是可能的。
如图所示以及如上所述，存在许多不同的方式，不同类型的电器件106可用这些方式设置在陶瓷封装衬底104的凹槽150中。存在支持单个管芯102所提供的多个器件106、单个器件106所支持的多个管芯102。器件106可垂直堆叠或者彼此分离地横向设置。器件106可处于单个凹槽150或者多个凹槽150中。器件106可直接与PCB 108或管芯102连接或者经由封装衬底104连接。凹槽150可处于封装衬底104的底部、封装衬底104的顶部或者处于封装衬底104的顶部和底部。
为了便于说明和描述，提供了本发明的实施例的以上描述。不旨在穷举或限制本发明于所公开的准确形式。本描述和随附权利要求书包括例如左、右、顶部、底部、之上、之下、上、下、第一、第二等的术语，这些术语仅用于进行描述而不是要理解为限制。例如，表示相对垂直位置的术语指的是衬底或集成电路的器件侧(或者活性表面)在那个衬底的“顶”面的情况；衬底实际上可处于任何取向，使得衬底的“顶”侧在标准地面参考框架中可低于“底”侧，但仍然落入术语“顶部”的含义之内。本文(包括权利要求书)所使用的术语“之上”不是要指明第二层“上”的第一层直接处于第二层之上并且与其直接接触，除非另加说明；在第一层与第一层上的第二层之间可存在第三层或其它结构。本文所述的器件或产品的实施例可通过多个位置和取向来制造、使用或装运。相关领域的操作人员可理解，根据上述教导，许多修改和变更是可能的。本领域的技术人员将领会附图所示的各个组件的各种等效组合和替代。因此，本发明的范围不是由本详细描述来限制，而是由所附权利要求书来限制。

Claims (14)

1.一种半导体装置，包括：
第一集成电路管芯；
封装衬底，所述封装衬底包括：
与所述第一集成电路管芯耦合的顶面；
底面；
包含陶瓷材料的多个基质层；
从所述封装衬底的所述底面向上延伸的凹槽侧壁以及凹面，所述凹槽侧壁和凹面限定所述封装衬底底部的腔室；以及
通过所述基质层的导电迹线和通孔，提供从所述顶面到所述腔室中的凹面的导电通路；以及
所述腔室中的硅内电压调节器和阵列电容器，所述阵列电容器通过所述导电迹线和通孔的至少一些导电迹线和通孔与所述第一集成电路管芯电连接。
2.如权利要求1所述的装置，其中，所述腔室具有中心，所述第一集成电路管芯具有中心，且所述腔室的中心直接在所述第一集成电路管芯的中心的下面。
3.如权利要求1所述的装置，还包括：印刷电路板，与所述封装衬底的所述底面相邻，并且与所述封装衬底和所述腔室中的所述阵列电容器或所述硅内电压调节器中之一电连接。
4.如权利要求1所述的装置，其中，所述阵列电容器处于所述硅内电压调节器与所述凹面之间。
5.如权利要求4所述的装置，其中，所述阵列电容器通过与所述凹面上的导体相连接的所述阵列电容器的顶面上的导体与所述第一集成电路管芯电连接，且所述阵列电容器通过所述阵列电容器的底面上的导体以及所述硅内电压调节器的顶面上的导体与所述硅内电压调节器电连接。
6.如权利要求1所述的装置，还包括：与所述封装衬底的所述顶面耦合的第二集成电路管芯。
7.如权利要求6所述的装置，其中，所述第一和第二集成电路管芯各为微处理器管芯。
8.一种半导体装置，包括：
封装衬底，包括陶瓷材料和在所述陶瓷材料中的导电迹线，所述封装衬底具有最大厚度；
第一集成电路管芯，与所述封装衬底的顶面电连接；以及
所述封装衬底底部中的凹槽中的硅内电压调节器和阵列电容器，所述凹槽由侧壁和顶面来限定，所述凹槽的所述顶面与所述封装衬底的所述顶面之间的厚度小于所述封装衬底的所述最大厚度。
9.如权利要求8所述的装置，还包括：与所述封装衬底的底面相邻的印刷电路板、将所述封装衬底与所述印刷电路板电连接的第一组导电连接器以及将所述阵列电容器与所述印刷电路板电连接的第二组导电连接器。
10.如权利要求9所述的装置，其中，所述印刷电路板是计算机系统中的母板。
11.如权利要求10所述的装置，其中，封装衬底和阵列电容器通过触点栅格阵列插座与所述印刷电路板连接。
12.如权利要求8所述的装置，其中，所述阵列电容器直接在所述第一集成电路管芯的下面。
13.如权利要求8所述的装置，还包括：第二集成电路管芯，与所述封装衬底的所述顶面电连接，其中，所述第一和第二集成电路管芯均为微处理器管芯。
14.如权利要求8所述的装置，其中，所述阵列电容器通过与所述封装衬底上的导体相连接的所述阵列电容器的顶面上的导体与所述第一集成电路管芯电连接，且所述阵列电容器通过所述阵列电容器的底面上的导体以及所述硅内电压调节器的顶面上的导体与所述硅内电压调节器电连接。
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US8264846B2 (en) 2012-09-11
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