CN102347282A - 包括无源组件电容器的半导体器件及制造方法 - Google Patents

包括无源组件电容器的半导体器件及制造方法 Download PDF

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CN102347282A
CN102347282A CN201110212024XA CN201110212024A CN102347282A CN 102347282 A CN102347282 A CN 102347282A CN 201110212024X A CN201110212024X A CN 201110212024XA CN 201110212024 A CN201110212024 A CN 201110212024A CN 102347282 A CN102347282 A CN 102347282A
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conductive plate
chip
electrical connection
wafer
material layer
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CN102347282B (zh
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洛朗·马雷夏尔
伊冯·因布斯
罗曼·科菲
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STMicroelectronics Grenoble 2 SAS
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Abstract

本发明涉及包括无源组件电容器的半导体器件及制造方法。一种半导体器件，包括具有正面和背面的晶圆。晶圆由具有与晶圆正面共面的电连接正面和与晶圆背面共面的背面的至少一个集成电路芯片形成。包括至少一个导电板和介电板的无源组件与集成电路芯片相邻布置。封装块嵌入有集成电路芯片和无源组件，该块具有与晶圆正面共面的正面和与晶圆背面共面的背面。在电连接正面与无源组件之间制作电连接。该电连接包括布置在晶圆正面和晶圆背面上的连接线。电连接进一步包括穿过封装块的至少一个通孔。

Description

包括无源组件电容器的半导体器件及制造方法
优先权要求
本申请要求2010年7月27日递交的法国专利申请No.1056159的优先权，因此通过引用将该申请的公开内容合并于此。
技术领域
本发明涉及半导体器件领域。
背景技术
制作在多个位置包括嵌入封装材料中的集成电路芯片的重构晶圆并对这些晶圆进行划片以形成单独半导体器件是已知的。
然而，尤其是由于诸如当前所使用的电容器的形状和电连接装置，目前还不可能将这些电容器集成到晶圆中的芯片附近。
发明内容
提供一种用于制造半导体器件的方法。
该方法包括：在载体的接纳表面的至少一个位置中布置至少一个集成电路芯片的电连接正面和包括由形成电容器的介电板分开的导电板的无源组件的正面；在所述接纳表面上形成封装材料层，以便在所述位置中获得包括封装块的晶圆，所述芯片和所述无源组件嵌入所述封装块中，并且所述封装层具有包括所述芯片的正面和所述无源组件的正面的正面；然后选择性地将所述导电板中的至少一些导电板连接至所述芯片，使得所述电容器中的至少一些电容器连接至所述芯片。
因此，可以预先制造具有简单结构的无源组件，以将其集成到封装块中，然后当制作到芯片的电连接时，根据需要形成一个或多个电容器。
该方法可以包括：在所述晶圆的正面上形成至少一个前电连接走线。
该方法可以包括：在所述晶圆的背面上形成至少一个后电连接走线，并且形成通过所述晶圆的电连接通孔，并在所述晶圆的正面上形成前电连接走线，所述后走线和所述前走线通过所述电连接通孔连接。
该方法可以包括：将所述无源组件布置为使得所述板垂直于所述接纳表面延伸，然后选择性地将所述导电板的至少一些平台连接至所述芯片。
该方法可以包括：将所述无源组件布置为使得所述板平行于所述接纳表面延伸。
该方法可以包括：在所述接纳表面上布置具有介电板的无源组件，然后在该介电板的正面形成至少一个附加导电板，以便形成包括由该第一介电板分开的该导电板和相邻导电板的所述电容器。
还提供一种半导体器件，包括：晶圆，具有正面，且包括具有电连接正面的至少一个集成电路芯片、具有正面且包括由用于形成电容器的介电板分开的导电板的至少一个无源组件、以及封装块，所述集成电路芯片和所述无源组件被嵌入所述封装块中，所述封装块的正面、所述集成电路芯片的正面和所述无源组件的正面形成所述晶圆的正面；以及电连接装置，连接所述导电板中的至少一些导电板和所述集成电路芯片，这些电连接装置形成在所述晶圆的正面上和/或所述晶圆的背面上，穿过所述封装块并且位于所述晶圆的正面上。
所述无源组件可以包括垂直于所述晶圆的正面延伸的板，所述电连接装置可以连接至所述导电板的平台。
所述板可以延伸至所述晶圆的厚度。
所述无源组件可以包括平行于所述晶圆的正面延伸的板。
所述无源组件可以包括与所述晶圆的正面相邻的介电板，至少一个导电板形成在该介电板的正面上。
附图说明
现在将以附图中所示非限制性示例的形式描述半导体器件，附图中：
图1示出半导体器件的截面图；
图2示出没有表面层时图1的半导体器件的正视图；
图3示出图1中半导体器件的无源组件的透视图；
图4示出根据一个制造步骤的图1中的半导体器件；
图5示出根据另一制造步骤的图1中的半导体器件；
图6示出根据又一制造步骤的图1中的半导体器件；
图7示出根据再一制造步骤的图1中的半导体器件；
图8示出另一半导体器件的截面图；
图9示出没有表面层时图8的半导体器件的正视图；
图10示出图8中半导体器件的无源组件的透视图；
图11示出根据一个制造步骤的图8中的半导体器件；
图12示出根据另一制造步骤的图8中的半导体器件；
图13示出根据又一制造步骤的图8中的半导体器件；并且
图14示出根据再一制造步骤的图8中的半导体器件。
具体实施方式
图1至图3所示的半导体器件1包括具有平行的正面3和背面4的晶圆2。
晶圆2包括其中嵌入有预先制造的集成电路芯片6和预先制造的无源组件7的介电封装材料块5，集成电路芯片6和无源组件7被布置为使得芯片6中形成有集成电路并且具有电连接焊盘的正面8、无源组件7的正面9和封装块5的正面10在形成晶圆2的正面3的同一平面上，无源组件7被布置在距芯片6的侧面一定距离处。因此，芯片6的正面8和无源组件7的正面9未被封装块5覆盖。
无源组件7包括与晶圆2的正面3平行布置的多个叠置的板。根据所示的示例，无源组件7在晶圆2的厚度方向上依次包括具有前述的面9的介电板11、导电板12、介电板13和导电板14，导电板12和14例如是金属。板12完全覆盖板11，板13不完全覆盖板12，并且板14完全覆盖板13，在所示的示例中，导电板14远离晶圆2的背面4。
在晶圆2的正面3上形成两个导电前板15和16，导电前板15和16通过前电连接走线17和18连接至芯片6正面8上的电连接焊盘，导电板15和16位于介电板11的正面9上，并且彼此远离。导电前板15和16与前电连接走线17和18具有相同的厚度。
在板12和14后面，和这些板12和14与晶圆2的背面4之间，在封装块5中提供孔19和20，孔19和20被导电材料填充，以形成电连接通孔21和22。
根据一个变体，无源组件7可以具有与晶圆2相同的厚度。在这种情况下，可以省略电连接通孔22。
在芯片6和无源组件7的侧面，和晶圆2的正面3与背面4之间，在封装块5中提供孔23和24，孔23和24被导电材料填充，以形成电连接通孔25和26。
在晶圆2的正面3上形成分别将通孔25和26连接至芯片6正面8上的电连接焊盘的前电连接走线27和28，并且在晶圆2的背面4上形成分别将通孔21和22连接至通孔25和26的后电连接走线29和30。
因此，无源组件7定义连接至芯片6的三个电容器，即包括由介电板11分开的导电板12和导电板15的第一电容器C1、包括由介电板11分开的导电板12和导电板16的第二电容器C2以及由介电板13分开的导电板12和14的第三电容器C3。
在晶圆2的正面3上提供介电层31，其覆盖导电板15和16以及电连接走线17、18、27和28，并且合并有允许芯片6正面8上的电连接焊盘和布置在层31正面上的外部电连接突起33进行选择性连接的电连接网络32。
在晶圆2的背面4上提供保护介电层34，其覆盖电连接走线29和30。
半导体器件1可以通过适当地采用微电子领域所使用的装置以下列方式制作。
如图4所示，在载体37的接纳表面36中的相邻例如方形位置35中布置芯片6和无源组件7，它们的正面8和9面对接纳表面36而布置，接纳表面36例如是自粘合的。
如图5所示，在载体37的接纳表面36上形成封装层38，其中嵌入有芯片6和无源组件7，然后该层38被平坦化(level)或减薄到例如芯片6的背面，以便获得分别在位置35中形成支撑芯片6和无源组件7的封装块5的大重构晶圆39。
接着，如图6所示，分别在位置35中在封装层38中制作孔19、20、23和24，并且孔分别被导电材料填充，以便在封装块5中分别形成通孔21、22、25和26。
然后，如图7中部分所示以及图1更充分示出的，在晶圆2的正面3上制作层31，分别在位置35中并且在相同的金属化层面上在层31中合并导电板15和16、前电连接走线17、18、27和28以及电连接网络32。可以在晶圆2的正面上直接形成中间介电层，然后，在该中间介电层上制作导电板15和16、前电连接走线17、18、27和28以及电连接网络32，并且在需要进行电连接的地方穿过中间介电层。此外，电连接网络32还可以包括若干个金属层面。
然后，在晶圆2的背面4上制作层34，分别在位置35中并且在相同的金属化层面上在层34中合并后电连接走线39和30。
然后，在前层31上布置电连接突起33。
最后，例如通过划片沿位置35的边缘将所获得的大晶圆39分为单个，以便获得多个半导体器件1。
紧随以上所述的是，在与前电连接走线17和18同时制作导电前板15和16时，尤其是通过选择这些板15和16的面积，定义了电容器C1和C2的电容。当然，可以通过与用于电连接到芯片6的一条或多条走线同时在正面3上形成一个或多个导电板，来制作一个或多个电容器。
另外，虽然提供了包括若干个电容器的预先制造的无源组件，但是根据所使用的芯片6以及与芯片6的操作和应用相关的需要的功能，仅会连接某些电容器。
图8至图10所示的另一半导体器件50包括具有平行的正面52和背面53的晶圆51。
晶圆51包括其中嵌入有预先制造的集成电路芯片55和预先制造的无源组件56的封装材料块54，集成电路芯片55和无源组件56被布置为使得芯片55的电连接正面57、无源组件56的正面58和封装块5的正面59在由晶圆51的正面52形成的同一平面上，无源组件56被布置在距芯片55的侧面一定距离处。
无源组件56包括与晶圆51的正面52垂直放置的多个叠置的板。根据所示的示例，无源组件56包括由三个介电板64、65和66分开的四个平行的例如金属的导电板60、61、62和63，以便形成三个电容器C10、C11和C12。
导电板60-63和介电板64-66被布置为具有形成无源组件56在晶圆51正面57的平面中的面58的前平台，以及位于晶圆51的背面53的平面中的对面背平台，因此导电板60-63和介电板64-66在这些面对的平台之间具有与晶圆51的厚度相对应的宽度。
以示例方式，电容器C10-C12可以以下列方式连接至芯片55。
例如，前电连接走线67、68和69可以形成在晶圆51的正面52上，以便通过延伸到导电板60、61和62的前平台和芯片55的前焊盘将导电板60、61和62的前平台连接至芯片55的前焊盘，使得电容器C10和C11分别通过前走线67和68以及前走线68和69连接至芯片55。
此外，封装块54可以具有被形成电连接通孔71的材料填充的透孔70，前电连接走线72可能形成在晶圆51的正面52上，以便通过延伸到通孔71和芯片55的前焊盘上而连接通孔71和芯片55的前焊盘，并且后电连接走线73可能形成在晶圆51的背面53上，以便通过延伸到通孔71和导电板63的后平台而连接通孔71和导电板63的后平台，从而使得电容器C12通过通孔71、前电连接走线72和后电连接走线73连接至芯片55。
在晶圆51的正面52上提供覆盖无源组件56的正面以及前电连接线67-69和72的介电层74，介电层74合并有允许芯片55正面57上的电连接焊盘和布置在层74正面上的外部电连接突起76进行选择性连接的电连接网络75。
保护介电层77提供在晶圆51的背面53上，其覆盖无源组件56的背面和后电连接走线73。
半导体器件50可以以下列方式制作。
如图11所示，在载体80的接纳表面79中的相邻例如方形位置78中布置芯片55和无源组件56，它们的正面57和58面对接纳表面79而布置，接纳表面79例如是自粘合的。
如图12所示，在载体80的接纳表面79上形成封装层81，其中嵌入有芯片55和无源组件56，然后该层81被平坦化或减薄，直到暴露无源组件56的背面，以便获得分别在位置78中形成支撑芯片55和无源组件56的封装块54的大重构晶圆82。
接着，如图13所示，分别在位置78中在封装层81中制作孔70，并且该孔70填充有导电材料，以便分别在封装块54中形成通孔71。
然后，如在图14中部分地示出且在图8中关于器件1更充分示出的，并且以与以上所述等同的方式，参考图1和图7，一方面，分别在位置78在介电前层74中制作前电连接走线67、68、69和72和网络75，另一方面，在介电后层77中制作后电连接走线73。
然后，在每个位置78中布置突起76。
最后，例如通过划片沿位置78的边缘将所获得的大晶圆82分为单个，以便获得多个半导体器件50。
在刚刚描述的两个示例中，虽然提供了包括若干个电容器的预先制造的无源组件，但是根据所使用的芯片55以及与芯片55的操作和应用相关的需要的功能，仅会连接某些电容器。
根据变体实施例，半导体器件可以包括无源组件，其中的某些电容器会串联或并联连接，以便创建连接至芯片的最终电容器。
根据变体实施例，半导体器件可以包括无源组件，其中的电容器中至少之一会直接连接至外部电连接突起之一。
根据变体实施例，半导体器件可以包括无源组件，其中的电容器中至少之一会直接连接至例如堆叠在背面的另一半导体器件。
本发明不限于以上所述的示例。可以在不超出所附权利要求所限定的范围的情况下得到多种其它变体实施例。

Claims (27)

1.一种用于制造半导体器件的方法，包括：
在载体的接纳表面上的至少一个位置中布置至少一个集成电路芯片的电连接正面和包括用于形成电容器的至少一个导电板和介电板的至少一个无源组件的正面；
在所述接纳表面上形成封装材料层，以便在所述位置中获得包括封装块的晶圆，所述芯片和所述无源组件被嵌入所述封装块中，并且所述封装块具有包括所述芯片的正面和所述无源组件的正面的正面；
然后选择性地将所述至少一个导电板连接至所述芯片，使得所述电容器连接至所述芯片。
2.根据权利要求1所述的方法，包括：在所述晶圆的正面上形成至少一条前电连接走线。
3.根据权利要求2所述的方法，包括：在所述晶圆的背面上形成至少一条后电连接走线，并且形成穿过所述晶圆的电连接通孔，并在所述晶圆的正面上形成前电连接走线，所述后走线和所述前走线通过所述电连接通孔连接。
4.根据权利要求1所述的方法，包括：将所述无源组件布置为使得所述至少一个导电板垂直于所述接纳表面而延伸，然后选择性地将所述至少一个导电板的边缘连接至所述芯片。
5.根据权利要求1所述的方法，包括：将所述无源组件布置为使得所述至少一个板平行于所述接纳表面而延伸。
6.根据权利要求5所述的方法，包括：在所述接纳表面上布置具有介电板的所述无源组件，然后在该介电板的正面上形成至少一个附加导电板，以便形成包括由所述第一介电板分开的所述附加导电板和所述至少一个导电板的所述电容器。
7.一种半导体器件，包括：
晶圆，具有正面，且包括具有电连接正面的至少一个集成电路芯片、具有正面且包括用于形成电容器的介电板和至少一个导电板的至少一个无源组件，所述晶圆包括封装块，所述集成电路芯片和所述无源组件被嵌入到所述封装块中，所述封装块的正面、所述集成电路芯片的正面和所述无源组件的正面形成所述晶圆的正面；以及
电连接，被配置为连接所述导电板中的至少一些导电板和所述集成电路芯片，这些电连接形成在所述晶圆的正面上和/或所述晶圆的背面上，穿过所述封装块并且位于所述晶圆的正面上。
8.根据权利要求7所述的器件，其中所述无源组件包括垂直于所述晶圆的正面延伸的所述至少一个导电板，所述电连接连接至所述导电板的边缘。
9.根据权利要求8所述的器件，其中所述至少一个导电板延伸至所述晶圆的厚度。
10.根据权利要求7所述的器件，其中所述无源组件包括平行于所述晶圆的正面延伸的所述至少一个导电板。
11.根据权利要求10所述的器件，其中所述无源组件包括与所述晶圆的正面(3)相邻的介电板，并且进一步包括形成在该介电板的正面上的附加导电板。
12.一种方法，包括：
在载体的接纳表面上布置集成电路芯片的电连接正面；
在所述载体的所述接纳表面上与所述集成电路芯片相邻地布置包括至少一个导电板和至少一个介电板的电容结构；
提供围绕所述集成电路芯片和所述电容结构的封装材料层，所述封装材料层具有与所述集成电路芯片的背面共面的背面；
在所述集成电路芯片的电连接正面与所述电容结构的至少一个导电板之间形成电连接，所述电连接包括穿过所述封装材料层的通孔和形成在所述封装材料层的背面上的连接线。
13.根据权利要求12所述的方法，其中布置电容结构包括使所述至少一个导电板平行朝向所述载体的所述接纳表面。
14.根据权利要求13所述的方法，其中形成电连接进一步包括在形成于所述封装材料层的背面上的所述连接线与所述至少一个导电板之间穿过所述封装材料层的另一通孔。
15.根据权利要求14所述的方法，进一步包括：
移除所述载体，所述集成电路芯片的电连接正面与所述封装材料层的正面共面；
在所述集成电路芯片的电连接正面与所述另一导电板之间形成另一导电板和另一电连接，所述另一电连接包括形成在所述封装材料层的正面上的连接线。
16.根据权利要求12所述的方法，其中布置电容结构包括使所述至少一个导电板垂直朝向所述载体的所述接纳表面。
17.根据权利要求16所述的方法，其中形成电连接进一步包括在形成于所述封装材料层的背面上的所述连接线与所述至少一个导电板的边缘之间制作电连接。
18.根据权利要求17所述的方法，其中所述电容结构包括垂直朝向所述载体的所述接纳表面的另一导电板，进一步包括：
移除所述载体，所述集成电路芯片的电连接正面与所述封装材料层的正面共面；
在所述集成电路芯片的电连接正面与所述另一导电板之间形成另一电连接，所述另一电连接包括形成在所述封装材料层的正面上的连接线。
19.根据权利要求18所述的方法，其中形成另一电连接进一步包括在形成于所述封装材料层的正面上的所述连接线与所述至少一个导电板的边缘之间制作电连接。
20.一种半导体器件，包括：
具有电连接正面以及背面的集成电路芯片；
包括至少一个导电板和至少一个介电板的电容结构；
围绕所述集成电路芯片和所述电容结构的封装材料层，所述封装材料层具有与所述集成电路芯片的电连接正面共面的正面和与所述集成电路芯片的背面共面的背面；以及
位于所述集成电路芯片的电连接正面与所述电容结构的至少一个导电板之间的电连接，所述电连接包括穿过所述封装材料层的通孔和形成在所述封装材料层的背面上的连接线。
21.根据权利要求20所述的器件，其中所述至少一个导电板平行朝向所述封装材料层的正面和背面。
22.根据权利要求21所述的器件，其中所述集成电路芯片的电连接正面与所述电容结构的至少一个导电板之间的所述电连接包括：在形成于所述封装材料层的背面上的连接线与所述至少一个导电板之间穿过所述封装材料层的另一通孔。
23.根据权利要求22所述的器件，其中所述电容结构进一步包括另一导电板，进一步包括在所述集成电路芯片的电连接正面与所述另一导电板之间的另一电连接，所述另一电连接包括形成在所述封装材料层的正面上的连接线。
24.根据权利要求20所述的器件，其中所述至少一个导电板平行朝向所述封装材料层的正面和背面。
25.根据权利要求24所述的器件，其中形成在所述封装材料层的背面上的连接线连接至所述至少一个导电板的边缘。
26.根据权利要求25所述的器件，其中所述电容结构包括垂直朝向所述载体的所述接纳表面的另一导电板，进一步包括：
在所述集成电路芯片的电连接正面与所述另一导电板之间的另一电连接，所述另一电连接包括形成在所述封装材料层的正面上的连接线。
27.根据权利要求26所述的器件，其中形成在所述封装材料层的正面上的连接线连接至所述另一导电板的边缘。
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