CN110416192A - 一种具有电容组件的集成电路封装结构及其封装方法 - Google Patents
一种具有电容组件的集成电路封装结构及其封装方法 Download PDFInfo
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Abstract
本发明提供了一种具有电容组件的集成电路封装结构及其封装方法,本发明利用单独的电容组件模块进行集成封装,不但可以减小封装的尺寸,同时提高了封装的灵活性,降低了成本;同时,封装时,使得衬底垂直于再分布层结构,可以减小两者不同的热膨胀系数而导致的应力翘曲,同时也能够保护第一芯片。
Description
技术领域
本发明涉及半导体器件封装领域,具体为一种具有电容组件的集成电路封装结构及其封装方法。
背景技术
随着集成度的不断提高,集成电路封装采用封装上封装模式,即POP结构。该种封装是一种三维立体封装,可以灵活控制芯片的堆叠或横向布置,以满足小尺寸的需求。对于一些具有特定功能的集成电路封装,往往需要集成电容器件,现有技术中,往往是是将电容器作为一个独立芯片进行组合封装,或者在布线层中形成内嵌的电容器结构,该两种封装虽然解决了集成电路的特定功能,但是对于其尺寸的减小是不利的,并且也会导致封装体受到应力而翘曲。
发明内容
基于解决上述问题,本发明提供了一种具有电容组件的集成电路封装结构,其包括:
第一再分布层,具有相对的第一表面和第二表面;
第一芯片,固定并电连接于所述第一再分布层上;
多个通孔,设置于所述第一芯片的周围,且其一端电连接于所述第一再分布层上;
多个电容组件,设置于所述第一芯片的周围,且其电连接于所述第一再分布层上;
第一塑封材料层,密封所述第一芯片、多个通孔和多个电容组件;
第二再分布层,形成于所述第一塑封材料层上,且电连接于所述第一芯片、多个通孔和多个电容组件;
第二芯片,通过焊球固定并电连接于所述第二再分布层上;
第二塑封材料层,密封所述第二芯片;
其特征在于,所述多个电容组件的每一个包括衬底、衬底上的介电材料层、介电材料层中的相对设置的两个电极板和电连接所述两个电极板的两个通孔,其中所述衬底垂直于所述第一表面,而所述电极板平行于所述第一表面,所述电容组件通过所述两个通孔分别电连接于所述第一再分布层和第二再分布层。
其中,所述第一塑封材料中还具有多个盲孔,所述多个盲孔分别物理连接于所述两个通孔中的一者。
其中,所述电容组件是一个独立的功能块,且优选为长方体结构,所述长方体结构包括顶面、底面以及在顶面和底面之间的四个侧面,所述长方体结构的底面即为所述衬底的底面,并且所述两个通孔分别连接两个电极板,所述两个电极板垂直于所述底面,且所述底面垂直于所述第一表面。
其中,所述介电材料层为高K材料。
其中,所述两个电极板之间的介电材料层以及所述两个电极板构成MIM电容器结构。
本发明还提供了一种具有电容组件的集成电路封装方法,其用于上述的具有电容组件的集成电路封装结构,其包括以下步骤:
1)在临时载体上形成第一再分布层,并在所述第一再分布层上固定并电连接第一芯片和多个电容组件;
2)利用塑封材料塑封所述第一芯片和所述多个电容组件以形成第一塑封材料层,然后进行平坦化,并在所述塑封材料中形成导电的多个通孔,其中所述多个通孔的一端电连接所述第一再分布层;
3)所述第一塑封材料层上形成第二再分布层,所述第二再分布层电连接所述多个通孔的第二端;在所述第二再分布层上电连接并固定第二芯片,并用塑封材料将所述第二芯片塑封以形成第二塑封材料层;
4)移除临时载体,使得所述第一再分布层的第二表面露出,在所述第二表面上形成外部连接端子。
本发明的优点如下:利用单独的电容组件模块进行集成封装,不但可以减小封装的尺寸,同时提高了封装的灵活性,降低了成本;同时,封装时,使得衬底垂直于再分布层结构,可以减小两者不同的热膨胀系数而导致的应力翘曲,同时也能够保护第一芯片。
附图说明
图1为本发明第一实施例的电容组件的剖视图;
图2为本发明第一实施例的电容组件的立体图;
图3-7为本发明第一实施例的电容组件的制造示意图;
图8是本发明第一实施例的具有电容组件的集成电路封装结构;
图9-12为本发明第一实施例的具有电容组件的集成电路封装结构的制造示意图;
图13为本发明第二实施例的电容组件的剖视图;
图14为本发明第二实施例的电容组件的立体图;
图15是本发明第二实施例的具有电容组件的集成电路封装结构。
具体实施方式
第一实施例
参见图1和2,本发明提供了一种电容组件10,该电容组件10包括衬底1及其在衬底1上的电容器、通孔5、6和介电层2,所述电容器具体包括相对的两个金属电极板3、4以及两个金属电极板3、4之间的介电材料7。其中,所述电容组件10为长方体形状,所述电容组件10包括顶面、底面以及在顶面和底面之间的四个侧面,所述衬底1的底面即为所述电容组件10的底面,并且所述通孔5、6分别连接两个金属电极板3、4,所述两个金属电极板3、4垂直于所述电容组件10和衬底1的底面。所述介电层2覆盖所述两个金属电极板3、4,且所述通孔5、6在所述介电层2中,并在所述电容组件10的两个相对的侧面露出。
该电容组件的制造方法是极为简单的,首先参见图3,在衬底1,上沉积第一介电层100,该衬底1为陶瓷材料或者硅材料,该第一介电层100为氧化硅或者氮化硅。参见图4,在所述第一介电层100中形成通孔5、6,然后沉积第二介电层102覆盖所述第一介电层100和通孔5、6,在所述第一介电层100和第二介电层102中形成两个沟槽103,所述沟槽103露出所述通孔5、6,在所述沟槽103中填充金属材料,形成两个金属电极板3、4,所述电解板3、4之间的第一介电层100和第二介电层102构成介电材料7,而第一介电层100和第二介电层102为介电层2。其中,所述通孔5、6与所述衬底1平行。优选的,所述介电材料7和介电层2为高K材料。
在集成电路封装中,该电容组件是利于封装的。具体参见图8,该封装体包括具有第一表面和第二表面的第一再分布层11,在所述第一再分布层11上设置有第一芯片13和至少一个上述的电容组件10,所述第一芯片13和所述电容组件10电连接至所述第一再分布层11,并且在所述第一芯片13的周围设置有通孔14,该通孔14与所述第一再分布层11电连接。塑封材料12密封所述第一芯片13、电容组件10和通孔14,所述第一芯片13、电容组件10完全嵌入所述塑封材料12中,所述通孔14从所述塑封材料12的顶部露出。第二再分布层16形成于所述塑封材料12上,并通过盲孔15与所述电容组件10的通孔5或6电连接,且所述第二再分布层16还电连接所述通孔14。在所述第二再分布层16上通过焊球18电连接第二芯片17,并利用塑封材料19密封所述第二芯片17。参见图8,本实施例中,所述电容组件10中的衬底1垂直于所述第一表面和第二表面,其中,所述两个金属电极板3、4平行于所述第一表面和第二表面,电容组件10的两个通孔5、6中的一者电连接于所述第一再分布层11,另一者电连接于第二再分布层16。此外,在所述第二表面还具有电连接所述第一再分布层11的外连接端子,例如焊球等。
上述封装体的制造方法参见图9-12,首先如图9所示,在临时载体110上形成第一再分布层11,并在所述再分布层11上固定并电连接第一芯片13和至少一个电容组件10。
参见图10,利用塑封材料12塑封所述第一芯片13和所述至少一个电容组件10,然后进行平坦化,并在所述塑封材料12中形成通孔111和盲孔112,所述盲孔112露出所述电容组件10的通孔5或6,而所述通孔111露出所述第一再分布层11的电路图案。
参见图11,在所述通孔111和盲孔112中填充导电材料形成通孔14和盲孔15,并在所述塑封材料12上形成第二再分布层16,所述第二再分布层16电连接所述通孔14和盲孔15。然后在所述第二再分布层16上电连接并固定第二芯片17,最后用塑封材料19将所述第二芯片17塑封。
参见图12,移除载体110,使得所述第一再分布层11的第二表面露出,在所述第二表面上形成外部连接端子20。
第二实施例
参见图13和14,本发明提供了另一种电容组件30,该电容组件30包括衬底1及其在衬底1上的电容器、通孔5、6和介电层2,所述电容器具体包括相对的两个金属电极板3、4以及两个金属电极板3、4之间的介电材料7。其中,所述电容组件10为长方体形状,所述电容组件10包括顶面、底面以及在顶面和底面之间的四个侧面,所述衬底1的底面即为所述电容组件10的底面,并且所述通孔5、6分别连接两个金属电极板3、4,所述两个金属电极板3、4垂直于所述电容组件10和衬底1的底面。所述介电层2覆盖所述两个金属电极板3、4,且所述通孔5、6在所述介电层2中,并在所述电容组件10的两个相对的侧面露出。以上与本申请的第一实施例相同或相似。在所述电容器上海设置有通孔结构,该通孔结构包括在所述介电层2和介电材料7上的低K介电层31以及在所述低K介电层31内的通孔32,其中通孔32在所述两个相对的侧面露出。
在集成电路封装中,该电容组件是利于封装的。具体参见图15,该封装体不需要额外的在塑封材料中形成通孔14,而是通过电容组件30内的通孔32来替代,以实现封装的简单化和标准化生产,也可以实现上下互联的稳定性。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (7)
1.一种具有电容组件的集成电路封装结构,其包括:
第一再分布层,具有相对的第一表面和第二表面;
第一芯片,固定并电连接于所述第一再分布层上;
多个通孔,设置于所述第一芯片的周围,且其一端电连接于所述第一再分布层上;
多个电容组件,设置于所述第一芯片的周围,且其电连接于所述第一再分布层上;
第一塑封材料层,密封所述第一芯片、多个通孔和多个电容组件;
第二再分布层,形成于所述第一塑封材料层上,且电连接于所述第一芯片、多个通孔和多个电容组件;
第二芯片,通过焊球固定并电连接于所述第二再分布层上;
第二塑封材料层,密封所述第二芯片;
其特征在于,所述多个电容组件的每一个包括衬底、衬底上的介电材料层、介电材料层中的相对设置的两个电极板和电连接所述两个电极板的两个通孔,其中所述衬底垂直于所述第一表面,而所述电极板平行于所述第一表面,所述电容组件通过所述两个通孔分别电连接于所述第一再分布层和第二再分布层。
2.根据权利要求1所述的具有电容组件的集成电路封装结构,其特征在于:所述第一塑封材料中还具有多个盲孔,所述多个盲孔分别物理连接于所述两个通孔中的一者。
3.根据权利要求1所述的具有电容组件的集成电路封装结构,其特征在于:所述电容组件是一个独立的功能块,且优选为长方体结构,所述长方体结构包括顶面、底面以及在顶面和底面之间的四个侧面,所述长方体结构的底面即为所述衬底的底面,并且所述两个通孔分别连接两个电极板,所述两个电极板垂直于所述底面,且所述底面垂直于所述第一表面。
4.根据权利要求1所述的具有电容组件的集成电路封装结构,其特征在于:所述介电材料层为高K材料。
5.根据权利要求4所述的具有电容组件的集成电路封装结构,其特征在于:所述两个电极板之间的介电材料层以及所述两个电极板构成MIM电容器结构。
6.一种具有电容组件的集成电路封装方法,其用于制造权利要求1所述的具有电容组件的集成电路封装结构,其包括以下步骤:
1)在临时载体上形成第一再分布层,并在所述第一再分布层上固定并电连接第一芯片和多个电容组件;
2)利用塑封材料塑封所述第一芯片和所述多个电容组件以形成第一塑封材料层,然后进行平坦化,并在所述塑封材料中形成导电的多个通孔,其中所述多个通孔的一端电连接所述第一再分布层;
3)所述第一塑封材料层上形成第二再分布层,所述第二再分布层电连接所述多个通孔的第二端;在所述第二再分布层上电连接并固定第二芯片,并用塑封材料将所述第二芯片塑封以形成第二塑封材料层;
4)移除临时载体,使得所述第一再分布层的第二表面露出,在所述第二表面上形成外部连接端子。
7.一种具有电容组件的集成电路封装结构,其包括:
第一再分布层,具有相对的第一表面和第二表面;
第一芯片,固定并电连接于所述第一再分布层上;
多个电容组件,设置于所述第一芯片的周围,且其电连接于所述第一再分布层上;
第一塑封材料层,密封所述第一芯片和多个电容组件;
第二再分布层,形成于所述第一塑封材料层上,且电连接于所述第一芯片和多个电容组件;
第二芯片,通过焊球固定并电连接于所述第二再分布层上;
第二塑封材料层,密封所述第二芯片;
其特征在于,所述多个电容组件的每一个包括衬底、衬底上的介电材料层、介电材料层中的相对设置的两个电极板和电连接所述两个电极板的两个通孔,并且,在所述介电材料层上还具有低K材料层,所述低K材料层中设置有通孔;其中所述衬底垂直于所述第一表面,而所述电极板平行于所述第一表面,所述电容组件通过所述两个通孔分别电连接于所述第一再分布层和第二再分布层;所述通孔电连接所述第一再分布层和第二再分布层。
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