CN110416190A - 一种半导体叠层封装结构 - Google Patents
一种半导体叠层封装结构 Download PDFInfo
- Publication number
- CN110416190A CN110416190A CN201910610837.0A CN201910610837A CN110416190A CN 110416190 A CN110416190 A CN 110416190A CN 201910610837 A CN201910610837 A CN 201910610837A CN 110416190 A CN110416190 A CN 110416190A
- Authority
- CN
- China
- Prior art keywords
- hole
- layer
- substrate
- semiconductor laminated
- capacitance component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本发明提供了一种半导体叠层封装结构,其包括电容组件,所述多个电容组件的每一个包括衬底及其在所述衬底上的电容器结构和通孔结构,所述电容器结构和通孔结构均电连接于所述第一和第二再分布层。所述电容器结构包括第一上通孔、介电层、导电层和第一下通孔,所述通孔结构包括第二上通孔、所述导电层和第二下通孔,其中,所述第一和第二下通孔设置于所述衬底中。
Description
技术领域
本发明涉及半导体器件封装领域,具体为一种半导体叠层封装结构。
背景技术
随着集成度的不断提高,集成电路封装采用封装上封装模式,即POP结构。该种封装是一种三维立体封装,可以灵活控制芯片的堆叠或横向布置,以满足小尺寸的需求。对于一些具有特定功能的集成电路封装,往往需要集成电容器件,现有技术中,往往是是将电容器作为一个独立芯片进行组合封装,或者在布线层中形成内嵌的电容器结构,该两种封装虽然解决了集成电路的特定功能,但是对于其尺寸的减小是不利的,并且也会导致封装体受到应力而翘曲。
发明内容
基于解决上述问题,本发明提供了一种半导体叠层封装结构,其包括:
第一再分布层,具有相对的第一表面和第二表面;
第一芯片,固定并电连接于所述第一再分布层上;
多个电容组件,设置于所述第一芯片的周围,且其电连接于所述第一再分布层上;
第一塑封材料层,密封所述第一芯片和多个电容组件;
第二再分布层,形成于所述第一塑封材料层上,且电连接于所述多个电容组件;
第二芯片,通过焊球固定并电连接于所述第二再分布层上;
第二塑封材料层,密封所述第二芯片;
其特征在于,所述多个电容组件的每一个包括衬底及其在所述衬底上的电容器结构和通孔结构,所述电容器结构和通孔结构均电连接于所述第一和第二再分布层。
根据本发明的实施例,所述电容器结构包括第一上通孔、介电层、导电层和第一下通孔,所述通孔结构包括第二上通孔、所述导电层和第二下通孔,其中,所述第一和第二下通孔设置于所述衬底中。
根据本发明的实施例,所述导电层沉积于所述衬底上,且具有多个分立的导电图案,该多个分立的导电图案分别与所述第一和第二下通孔对应并物理连接;所述介电层覆盖所述衬底和导电层,且仅仅在所述第二上通孔的底部具有开口,该开口露出所述导电层。
根据本发明的实施例,还包括低K材料层,其形成于所述介电层上,且所述第一和第二上通孔形成于所述低K材料层中,所述第一上通孔的底部物理接触所述介电层,所述第二上通孔的底部物理接触所述导电层。
根据本发明的实施例,其中,该衬底为硅衬底。
根据本发明的实施例,该低K材料层为氧化硅或者氮化硅。
根据本发明的实施例,所述介电层为高K材料,例如ZrO2,Al2O3,Si3N4,HfO2,Y2O3,SiO2,Ta2O5,La2O3,TiO2。
根据本发明的实施例,所述导电层为铝、铜、钛、氮化钛、钽、氮化钽中的任意一种或多种组合。
本发明的优点如下:利用单独的电容组件模块进行集成封装,不但可以减小封装的尺寸,同时提高了封装的灵活性,降低了成本;该电容组件既包括电容结构,也包括通孔结构,且制备工艺简单,可以利用导电层形成两种结构,只是刻蚀的深度不同,导致上通孔的电连接位置不同。
附图说明
图1为本发明的电容组件的剖视图;
图2为本发明的半导体叠层封装结构。
具体实施方式
参见图1,本发明提供了一种电容组件100,该电容组件100包括衬底10及其在衬底10上的电容器结构和通孔结构。电容器结构包括第一上通孔17、介电层12、导电层11和第一下通孔19,所述通孔结构包括第二上通孔18、导电层11和第二下通孔20,其中,所述第一和第二下通孔19、20设置于所述衬底10中,且通过相同的工艺在相同的步骤中形成。所述导电层11沉积于所述衬底10上,且具有多个分立的导电图案,该多个分立的导电图案分别与所述第一和第二下通孔19、20对应并物理连接。所述介电层12覆盖所述衬底10和导电层11,且仅仅在所述第二上通孔18的底部具有开口,该开口露出所述导电层11。低K材料层13形成于所述介电层12上,且所述第一和第二上通孔17、18形成于所述低K材料层13,所述第一上通孔17的底部物理接触所述介电层12,所述第二上通孔18的底部物理接触所述导电层11。所述第一上通孔17作为电容器结构的上极板,而所述第一下通孔19与所述导电层12作为电容器结构的下极板。
其中,该衬底10为硅衬底,该低K材料层13为氧化硅或者氮化硅。所述介电层12为高K材料,例如ZrO2,Al2O3,Si3N4,HfO2,Y2O3,SiO2,Ta2O5,La2O3,TiO2。所述导电层11为铝、铜、钛、氮化钛、钽、氮化钽中的任意一种或多种组合。
在集成电路封装中,该电容组件是利于封装的。具体参见图2,该封装体包括具有第一表面和第二表面的第一再分布层28,在所述第一再分布层28上设置有第一芯片22和至少一个上述的电容组件100,所述第一芯片22和所述电容组件100的第一和第二下通孔19、20电连接至所述第一再分布层28。塑封材料23密封所述第一芯片22、电容组件100,所述电容组件100的顶面从所述塑封材料23的顶面齐平,且所述第一个和第二上通孔17、18从所述塑封材料23的顶部露出。第二再分布层24形成于所述塑封材料23上,所述第一个和第二上通孔17、18电连接于所述第二再分布层24。在所述第二再分布层24上通过焊球26电连接第二芯片25,并利用塑封材料27密封所述第二芯片25。此外,在所述第二表面还具有电连接所述第一再分布层28的外连接端子29,例如焊球等。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (8)
1.一种半导体叠层封装结构,其包括:
第一再分布层,具有相对的第一表面和第二表面;
第一芯片,固定并电连接于所述第一再分布层上;
多个电容组件,设置于所述第一芯片的周围,且其电连接于所述第一再分布层上;
第一塑封材料层,密封所述第一芯片和多个电容组件;
第二再分布层,形成于所述第一塑封材料层上,且电连接于所述多个电容组件;
第二芯片,通过焊球固定并电连接于所述第二再分布层上;
第二塑封材料层,密封所述第二芯片;
其特征在于,所述多个电容组件的每一个包括衬底及其在所述衬底上的电容器结构和通孔结构,所述电容器结构和通孔结构均电连接于所述第一和第二再分布层。
2.根据权利要求1所述的半导体叠层封装结构,其特征在于:所述电容器结构包括第一上通孔、介电层、导电层和第一下通孔,所述通孔结构包括第二上通孔、所述导电层和第二下通孔,其中,所述第一和第二下通孔设置于所述衬底中。
3.根据权利要求2所述的具有电容组件的半导体叠层封装结构,其特征在于:所述导电层沉积于所述衬底上,且具有多个分立的导电图案,该多个分立的导电图案分别与所述第一和第二下通孔对应并物理连接;所述介电层覆盖所述衬底和导电层,且仅仅在所述第二上通孔的底部具有开口,该开口露出所述导电层。
4.根据权利要求3所述的具有电容组件的半导体叠层封装结构,其特征在于:还包括低K材料层,其形成于所述介电层上,且所述第一和第二上通孔形成于所述低K材料层中,所述第一上通孔的底部物理接触所述介电层,所述第二上通孔的底部物理接触所述导电层。
5.根据权利要求4所述的具有电容组件的半导体叠层封装结构,其特征在于:其中,该衬底为硅衬底。
6.根据权利要求4所述的具有电容组件的半导体叠层封装结构,其特征在于:该低K材料层为氧化硅或者氮化硅。
7.根据权利要求4所述的具有电容组件的半导体叠层封装结构,其特征在于:所述介电层为高K材料,例如ZrO2,Al2O3,Si3N4,HfO2,Y2O3,SiO2,Ta2O5,La2O3,TiO2。
8.根据权利要求4所述的具有电容组件的半导体叠层封装结构,其特征在于:所述导电层为铝、铜、钛、氮化钛、钽、氮化钽中的任意一种或多种组合。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910610837.0A CN110416190A (zh) | 2019-07-08 | 2019-07-08 | 一种半导体叠层封装结构 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201910610837.0A CN110416190A (zh) | 2019-07-08 | 2019-07-08 | 一种半导体叠层封装结构 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN110416190A true CN110416190A (zh) | 2019-11-05 |
Family
ID=68360664
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201910610837.0A Withdrawn CN110416190A (zh) | 2019-07-08 | 2019-07-08 | 一种半导体叠层封装结构 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN110416190A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022228369A1 (zh) * | 2021-04-29 | 2022-11-03 | 华为技术有限公司 | 一种集成电路 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1367936A (zh) * | 1999-06-08 | 2002-09-04 | 因芬尼昂技术股份公司 | 具有存储单元、逻辑区域和填充结构的半导体存储元件 |
US20130039113A1 (en) * | 2010-01-21 | 2013-02-14 | Stmicroelectronics (Crolles 2) Sas | Integrated dram memory device |
CN108109957A (zh) * | 2017-12-15 | 2018-06-01 | 西安科锐盛创新科技有限公司 | 系统级封装抗静电转接板 |
CN108389823A (zh) * | 2018-01-31 | 2018-08-10 | 浙江卓晶科技有限公司 | 用于多芯片晶圆级扇出型三维立体封装结构及其封装工艺 |
-
2019
- 2019-07-08 CN CN201910610837.0A patent/CN110416190A/zh not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1367936A (zh) * | 1999-06-08 | 2002-09-04 | 因芬尼昂技术股份公司 | 具有存储单元、逻辑区域和填充结构的半导体存储元件 |
US20130039113A1 (en) * | 2010-01-21 | 2013-02-14 | Stmicroelectronics (Crolles 2) Sas | Integrated dram memory device |
CN108109957A (zh) * | 2017-12-15 | 2018-06-01 | 西安科锐盛创新科技有限公司 | 系统级封装抗静电转接板 |
CN108389823A (zh) * | 2018-01-31 | 2018-08-10 | 浙江卓晶科技有限公司 | 用于多芯片晶圆级扇出型三维立体封装结构及其封装工艺 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2022228369A1 (zh) * | 2021-04-29 | 2022-11-03 | 华为技术有限公司 | 一种集成电路 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20200328191A1 (en) | Stacked package structure and stacked packaging method for chip | |
KR100480437B1 (ko) | 반도체 칩 패키지 적층 모듈 | |
JP5042591B2 (ja) | 半導体パッケージおよび積層型半導体パッケージ | |
US5834832A (en) | Packing structure of semiconductor packages | |
US9847299B2 (en) | Semiconductor package and mounting structure thereof | |
US10930619B2 (en) | Multi-wafer bonding structure and bonding method | |
US10950533B2 (en) | Through electrode substrate and semiconductor device | |
CN105514093B (zh) | 基于硅通孔技术的半导体电容器及其制造方法、封装结构 | |
US6320757B1 (en) | Electronic package | |
KR20090043896A (ko) | 칩 적층 패키지 | |
US10354936B2 (en) | Electronic component having a heat dissipation member formed on a sealing member | |
US10651150B2 (en) | Multichip module including surface mounting part embedded therein | |
WO2016162938A1 (ja) | 半導体装置 | |
US6340839B1 (en) | Hybrid integrated circuit | |
CN104733398A (zh) | 一种晶圆三维集成引线工艺 | |
CN110416190A (zh) | 一种半导体叠层封装结构 | |
KR101450761B1 (ko) | 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법 | |
CN110459483A (zh) | 一种电容组件的制造方法和半导体叠层封装方法 | |
CN104681523B (zh) | 指纹锁识别模组封装结构 | |
JP3247544B2 (ja) | 半導体装置 | |
KR20060044670A (ko) | 반도체 장치 | |
CN106952886A (zh) | 一种射频芯片封装结构 | |
US7262508B2 (en) | Integrated circuit incorporating flip chip and wire bonding | |
CN209947823U (zh) | 芯片封装结构 | |
CN213401191U (zh) | 封装结构 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WW01 | Invention patent application withdrawn after publication | ||
WW01 | Invention patent application withdrawn after publication |
Application publication date: 20191105 |