CN109411371A - 叠层集成电路封装结构的封装方法 - Google Patents
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Abstract
本发明提供了一种叠层集成电路封装结构的封装方法,其包括:提供长宽尺寸相同的多个陶瓷片,将所述多个陶瓷片中的除最底层的其他陶瓷片开窗形成框型槽,并在除最顶层的其他陶瓷片的表面上形成线路层;叠置并烧结所述多个陶瓷片形成一体化陶瓷叠层;在陶瓷叠层内设置集成芯片;在陶瓷叠层的侧面形成点阵式焊盘,以电连接所有的线路层的端部;将陶瓷叠层接合至散热基板上,并根据实际需要在陶瓷叠层的侧面形成重分布线电连接所述焊盘和所述点阵式焊盘。本发明减小了封装体积,增强了封装的灵活性。
Description
技术领域
本发明涉及集成电路封装领域,具体涉及一种叠层集成电路封装结构。
背景技术
在集成电路封装中,多采用打线或布线的方式进行电连接各集成电路芯片的引脚,以达到既定的封装体功能模块,叠置的芯片封装可以减小封装体积,是目前采用较广的发展方式。但是叠置封装容易造成打线间交叉短路或布线太乱不易更改的问题,这样得到的封装体往往体积较大且封装极为不灵便,布线也不能随意调整和更改。
发明内容
基于解决上述封装中的问题,本发明提供了一种叠层集成电路封装结构的封装方法,其包括以下步骤:
(1)提供一散热基板,并在该散热基板上形成多个焊盘;
(2)提供长宽尺寸相同的多个陶瓷片,将所述多个陶瓷片中的除最底层的其他陶瓷片开窗形成框型槽,并在除最顶层的其他陶瓷片的表面上形成线路层,所述线路层在相应的陶瓷片边缘露出端部;
(3)叠置并烧结所述多个陶瓷片形成一体化陶瓷叠层;
(4)在陶瓷叠层内设置集成芯片;
(5)在陶瓷叠层的侧面形成点阵式焊盘,以电连接所有的所述端部;
(6)将陶瓷叠层接合至所述散热基板上,并根据实际需要在陶瓷叠层的侧面形成重分布线电连接所述焊盘和所述点阵式焊盘。
其中,焊盘只是被封装层覆盖一半。
其中,所述线路的水平高度和所述点阵式焊盘每层的高度相同,呈对应关系。
其中,焊盘与点阵式焊盘列向对齐。
其中,重分布线跨越不同的侧表面。
其中,所述陶瓷叠层内的集成芯片包括多个,陶瓷叠层的每一层的厚度根据每层所封装的集成芯片的厚度不同而不同。
所述陶瓷叠层的每一层中可包括多个集成芯片,其中除最厚的芯片外其余芯片上方均设置有刚性构件。
其中,所述刚性构件的厚度等于最厚的芯片的厚度减去对应的较薄的芯片的厚度。
本发明的优点如下:
(1)利用叠层封装,减小封装体积,增强封装的灵活性;
(2)利用封装体侧表面的点阵式焊盘进行线路再分布,增加了布线的灵活性;
(3)刚性构件的使用防止了叠层封装的弯折翘曲。
附图说明
图1为本发明的集成电路封装结构的截面图;
图2为本发明的集成电路封装结构的俯视图;
图3为本发明的集成电路封装结构的一侧表面电连接图;
图4为本发明的集成电路封装结构的立体图;
图5为本发明的封装基板的制作流程图;
图6为本发明的陶瓷叠层的制作流程图;
图7为本发明的集成电路封装结构的制作流程图。
具体实施方式
参见图1,本发明首先提供了一种叠层集成电路封装结构,其封装结构为一长方体封装体,其具有散热基板1,散热基板1上设置有多个焊盘2,在基板1上设置有陶瓷叠层7,所述陶瓷叠层7的每一层的厚度根据每层所封装的集成电路芯片3的厚度不同而不同,每一层的厚度均等于每层所封装的集成电路芯片3的最大厚度,例如在第三层陶瓷7中的两个集成电路芯片的厚度不同,但是该层的厚度等于较厚的集成电路芯片的厚度,在这种情况下,为了防止上层集成电路芯片的弯折,在较薄的芯片3上方设置一刚性构件6,其厚度等于较厚芯片的厚度减去较薄芯片的厚度。
所述陶瓷叠层7的除最底层(第1层)的其他各层(第2-5层)均具有容纳集成电路芯片3的凹槽9,凹槽9呈阶梯状分布,所述凹槽9可用封装材料进行灌封,所述封装材料为环氧树脂或聚酰亚胺等。第3-5层的集成电路芯片3依次叠置在其下层的集成电路芯片3上,可以电隔离或者也可以电接触。第1-4层的陶瓷叠层7的顶面分别具有线路4,所述线路4分别于其所对应的层中的集成电路芯片3电连接,并且,线路4可以在层间进行第一次电路重分布,层层之间的线路4彼此通过封装层7电隔离,线路4最终在陶瓷叠层7的侧表面漏出端部,陶瓷叠层7的侧表面上具有点阵式焊盘5,线路层分别于所述焊盘中的部分或全部进行电连接以引出端子。此外,焊盘2只是被封装层7覆盖一半,这样有利于后续重布线的电连接。
参见图2,其只示意性描述了只具有两层陶瓷叠层7的俯视图,可以看出每层的线路4的水平高度和焊盘每层的高度相同,呈对应关系,且根据实际需要,线路4可以在各层中根据实际情况的不同实现再分布。
参见图3,在该封装结构体的一个侧表面上,点阵式焊盘5为4×3的矩阵,焊盘2与点阵式焊盘5列向对齐,方便于重布线,根据实际电连接的需要,可将不同的焊盘5通过重分布线8电连接,并耦合至相应的焊盘2上。
参见图4,其立体的展示了侧表面的电连接情况,重分布线8可以跨越不同的侧表面以电连接不同表面的焊盘5。
图5-7示出了本发明的集成电路封装结构的封装方法。参见图5,步骤S11,提供一散热基板,该散热基板可以是金属基板、陶瓷基板或复合散热基板等;步骤S12,在散热基板上形成多个焊盘,焊盘可利用电镀、沉积或图案化的方式形成,多个焊盘呈长方形排列,长方形的长宽等于后续的陶瓷叠层的地面投影的长宽,步骤S13,经过切割打磨等工序,以此得到封装基板。
参见图6,步骤S21,提供N片陶瓷片,所述N是大于或等于3的自然数(否则不能产生芯片叠层结构)。所述N片陶瓷片的长宽尺寸相同,但厚度不同(根据芯片的不同而不同),其长宽等于上述焊盘中心连线所构成的长方形的长宽,所述陶瓷片为生陶瓷片;步骤S22,将除最底层的N-1片陶瓷片开窗形成框型槽,并且,所述框型槽的开口面积不同,总体是自上而下依次递减,框型槽在截面图上呈现阶梯状分布(参见图1);步骤S23,在除最顶层的N-1片陶瓷片的表面形成电路层(线路层),所述电路层为导电迹线,且可以对引出的电信号进行第一次再分布,电路层延伸至陶瓷片的边缘形成端部,该端部并均匀分开;步骤S24,将所述N片陶瓷片层叠压合,并进行高温烧结以形成一体结构;步骤S25,通过抛光表面得到陶瓷叠层。
参见图7,步骤S31,在上述的陶瓷叠层的每层陶瓷片的框型槽中设置集成芯片,所述陶瓷叠层的每一层的厚度根据每层所封装的集成电路芯片的厚度不同而不同,每一层的厚度均等于每层所封装的集成电路芯片的最大厚度,例如图1中的第三层陶瓷7中的两个集成电路芯片的厚度不同,但是该层的厚度等于较厚的集成电路芯片的厚度,在这种情况下,为了防止上层集成电路芯片的弯折,在较薄的芯片3上方利用粘着剂设置一刚性构件6,其厚度等于较厚芯片的厚度减去较薄芯片的厚度;步骤S32,在框型槽中填充环氧树脂或聚酰亚胺材料封装集成芯片;步骤S33,在陶瓷叠层的侧面上形成点阵式焊盘,所述点阵式焊盘电连接于全部或部分的所述线路层的端部;步骤S34,将陶瓷叠层和封装基板对准接合,是的陶瓷叠层覆盖所述多个焊盘中的每一个的一半;步骤S35,根据实际封装芯片的电连接需要,在陶瓷叠层的侧面形成重分布线,所述重分布线电连接至全部或部分的点阵式焊盘;步骤S36,最终形成集成电路封装结构。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (2)
1.一种叠层集成电路封装结构的封装方法,其包括以下步骤:
提供一散热基板,并在该散热基板上形成多个焊盘;
提供长宽尺寸相同的多个陶瓷片,将所述多个陶瓷片中的除最底层的其他陶瓷片开窗形成框型槽,并在除最顶层的其他陶瓷片的表面上形成线路层,所述线路层在相应的陶瓷片边缘露出端部;
叠置并烧结所述多个陶瓷片形成一体化陶瓷叠层;
在陶瓷叠层内设置集成芯片;
在陶瓷叠层的侧面形成点阵式焊盘,以电连接所有的所述端部;
将陶瓷叠层接合至所述散热基板上,并根据实际需要在陶瓷叠层的侧面形成重分布线电连接所述焊盘和所述点阵式焊盘,
焊盘与点阵式焊盘列向对齐,重分布线跨越不同的侧表面。
2.根据权利要求1所述的封装方法,其特征在于:所述陶瓷叠层内的集成芯片包括多个,陶瓷叠层的每一层的厚度根据每层所封装的集成芯片的厚度不同而不同。
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CN110444527A (zh) * | 2019-07-23 | 2019-11-12 | 中国科学技术大学 | 一种芯片封装结构、装置及方法 |
CN111081687B (zh) * | 2019-12-16 | 2022-02-01 | 东莞记忆存储科技有限公司 | 一种堆叠式芯片封装结构及其封装方法 |
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JPH04196579A (ja) * | 1990-11-28 | 1992-07-16 | Fujitsu Ltd | 積層型半導体装置 |
TW373308B (en) * | 1995-02-24 | 1999-11-01 | Agere Systems Inc | Thin packaging of multi-chip modules with enhanced thermal/power management |
US6297548B1 (en) * | 1998-06-30 | 2001-10-02 | Micron Technology, Inc. | Stackable ceramic FBGA for high thermal applications |
JP2002076167A (ja) * | 2000-08-29 | 2002-03-15 | Sony Corp | 半導体チップ、積層型半導体パッケージ、及びそれらの作製方法 |
JP2004228117A (ja) * | 2003-01-20 | 2004-08-12 | Idea System Kk | 半導体装置および半導体パッケージ |
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US8354743B2 (en) * | 2010-01-27 | 2013-01-15 | Honeywell International Inc. | Multi-tiered integrated circuit package |
CN102332410A (zh) * | 2011-09-29 | 2012-01-25 | 山东华芯半导体有限公司 | 一种芯片的封装方法及其封装结构 |
TWI490960B (zh) * | 2012-01-17 | 2015-07-01 | Chipmos Technologies Inc | 半導體封裝結構及其製作方法 |
US9209138B2 (en) * | 2013-12-09 | 2015-12-08 | Aeroflex Colorado Springs, Inc. | Integrated circuit shielding technique utilizing stacked die technology incorporating top and bottom nickel-iron alloy shields having a low coefficient of thermal expansion |
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