TWI400776B - 具有容置在凹部之裝置的陶瓷封裝基板 - Google Patents

具有容置在凹部之裝置的陶瓷封裝基板 Download PDF

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TWI400776B
TWI400776B TW096143690A TW96143690A TWI400776B TW I400776 B TWI400776 B TW I400776B TW 096143690 A TW096143690 A TW 096143690A TW 96143690 A TW96143690 A TW 96143690A TW I400776 B TWI400776 B TW I400776B
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package substrate
array capacitor
die
recess
integrated circuit
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TW096143690A
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TW200847349A (en
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Cengiz A Palanduz
Christopher C Jones
David R Bach
Timothe Litt
Larry L Binder
Kaladhar Radhakrishnan
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Intel Corp
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Description

具有容置在凹部之裝置的陶瓷封裝基板
本發明關於一種陶瓷封裝基板，特別是關於一種具有容置在凹部之裝置的陶瓷封裝基板。
電容器和其它裝置伴隨著封裝基板一起使用，以改善解耦合電容、阻抗下垂及其它效能參數。
本發明關於一種陶瓷封裝基板，特別是關於一種具有容置在凹部之裝置的陶瓷封裝基板。
在各種實施例中，描述有關具有一凹部在下方的一陶瓷封裝基板的一設備及方法，以及在那凹部中的一種裝置。在以下的敘述中，將描述各種實施例。然而，熟悉相關技術者將會認知，沒有一項或多項特定細節或有其它替代品及/或附加的方法、材料、或零件的各種實施例也可實施。在其它的例子中，眾所周知的結構、材料、或操作不會加以顯示或詳細描述，以避免模糊本發明各種實施例的各方面。同樣地，為了說明的目的，記載了特定的數目、材料、和結構，以便完整了解該發明。然而，該發明沒有特定細節也可以實施。進一步來說，可理解顯示在圖中的 各種實施例是說明性表現，且無需依比例尺繪製。
在說明書全文中關於“一個實施例”或“一實施例”，意指描述和該實施例有關的特殊外型、結構、材料或特徵，包含在本發明的至少一個實施例中，但不表示存在每一實施例中。因此，在說明書全文中各地方出現“在一個實施例中”或“在一實施例中”一詞，不需要參考該發明相同的實施例。進一步說明，特殊的外型、結構、材料或特徵，可以在一個或多個實施例中以任何適合的方式結合。在其它的實施例中，可包含各種不同的附加層及/或結構，且/或描述的外型可加以省略。
各種不同的操作將以最有助於了解該發明的方式，依次描寫為多重分離操作。然而，描述的順序不該理解為用來暗示這些操作是必要的相關順序。特別是這些操作不需以呈現的順序來執行。描述的操作可以不同的順序或串序或並序地加以執行，而非如所述實施例般地操作。各種的附加操作可被執行，且/或描述的操作可以在附加的實施例中加以省略。
圖1是一橫剖面側視圖，此圖例示根據本發明的一實施例的一晶粒封裝100。晶粒封裝100包括一晶粒102。晶粒102可以是一微處理器晶粒或另外一類型的積體電路晶粒。晶粒102是連結到一陶瓷封裝基板104。任何類型的傳導連接器可以用來連結晶粒102至該陶瓷封裝基板104，包括焊料球、一基板柵格陣列(land grid array)、金屬至金屬接合或其它傳導連接器。陶瓷封裝基板104包括一陶 瓷矩陣材料的多個層，在多個層中配置導孔和導線。這些導孔和導線，提供介於晶粒102及可連結至封裝基板104的其它零件之間的電子聯繫。
封裝基板104有一凹部150在它的底表面，此凹部150亦稱為空穴150。凹部150由封裝基板104的底表面往上延伸的凹部側壁110及一凹陷表面112所界定，凹陷表面112為該凹部150的頂表面112。凹部150可以具有任何希望的深度及容積。
在凹部150內有一種電性裝置106。在該說明的實施例中，裝置106是一陣列電容器，但在其它的實施例中，裝置106可為一標準電容器、一矽中(in-silicon)電壓調節器、另一類型整合電壓調節器、另一裝置或其它裝置。
裝置106電性地連結到陶瓷封裝基板104。該電性的連結可用各種適合的方法達成。裝置106具有導體(焊盤墊(land pad)或其它適合的導體)在它的頂表面上。可有焊墊或其它的連結點在凹部150的頂表面112。該裝置106藉由焊料凸塊或任何其它方法可連結至凹部150的頂表面112。在一實施例中，這些連結為表面安裝-焊料球將裝置106連接至在凹部150頂表面112的焊盤(land)。
封裝基板104的導線和導孔，將裝置106電性地連結至晶粒102。相較於裝置106的其它配置，因為裝置106在凹部150之中，所以電性訊號所必須傳輸介於裝置106及晶粒102之間的距離可以被縮短。相較於如果裝置106位在離晶粒102較遠之處，此縮短的距離可提供較佳的效能。例 如，陶瓷封裝基板104具有一厚度114。在該說明的實施例中，介於裝置106和晶粒102之間的距離116，小於基板104的厚度114。如果裝置106設置在缺少凹部150的一基板104的底側上，或裝置106離開基板104設置(例如當裝置106裝置在一主機板上)，介於裝置106及晶粒102之間的電性距離會較長，並可能降低晶粒封裝100的效能。
在該說明的實施例中，凹部150及在凹部150內的裝置106，實質上是在晶粒102的正下方。凹部150的中心及裝置106，實質上是在晶粒102的中心正下方。此配置方式可以幫助縮短介於裝置106及晶粒102之間的電性訊號傳輸路徑的電性長度。在其它的實施例中，凹部150和裝置106可在晶粒102的正下方，而不是在中心(on－center)。然而，在其它的實施例中，凹部150及裝置106可以不設置在該晶粒102的正下方；其它有別於縮短電性路徑距離的考量可導致這些其它的配置。
根據本發明的一實施例，圖2是一橫剖面視圖，此圖例示當封裝基板裝置104安裝在一印刷電路板108上時的晶粒封裝100。在一實施例中，例如，印刷電路板108是在一電腦系統中的一主機板，雖然不局限在此。封裝基板104可藉由任何適合的方法連結至該主機板，例如，一基板柵格陣列、焊料球或其它電性導體。藉由封裝基板104，晶粒102因而電性地連結至印刷電路板108。
在該例示的實施例中，藉由在裝置106的底側上的連接器，裝置106直接地連結到印刷電路板108。這些連接 器可以是任何適合的連接器類型，例如，一基板柵格陣列、焊料球或其它電性導體。裝置106可包含由該裝置106的底表面延伸的穿透導孔，以容許從在或鄰近裝置106的頂表面的電容器、電壓調節器或其它電性裝置至裝置106的底表面的電性連結。
在其它的實施例中，在裝置106的底表面可以沒有連接器。然而，裝置106可以只連結到封裝基板104。在這些實施例中，連接至晶粒102且/或印刷電路板108的任何電性連結是透過基板104而達成。
相較於延伸跨接封裝基板104的頂表面或底表面的裝置，或設置在其它地方(例如在印刷電路板108上)的裝置，使用在凹部150內的陣列電容器106或其它裝置106，能夠節省空間。在基板104的底表面上的傳統裝置會佔據空間，且由於封裝基板104和印刷電路板108之間的連結而使得那空間不再方便使用。同樣地，印刷電路板108本身也只有有限的空間。
根據本發明的一實施例，圖3是一橫剖面視圖，此圖更詳細地例示形成基板104的多重層。封裝基板104由多重層而形成。圖3中例是有三層302,304,及306，雖然在其它實施例中可使用更多層或更少層。每一層302,304,306包含一陶瓷矩陣材料，例如鋁。每一層302,304,306可實質地不含有機或聚合體材料。如在層302中所示，層包括導線310及導孔312，以容許封裝基板104傳輸介於晶粒102、印刷電路板108和在凹部150內的裝置106之間的電性訊號 。可以使用任何適合的方法以形成陶瓷層320,304,306的圖案，且形成導線310和導孔312。例如，可在綠色陶瓷片中衝擊出孔洞及下陷以形成層302,304,306。然後，供導線310及導孔312用的孔洞及下陷可以由一傳導材料填滿。
層306包含一孔洞308。在一層或多層306中的孔洞308形成凹部150。此孔洞308和供導孔312及導線310用的的孔洞和壓痕以同樣的方法產生。在另一實施例中，在如同層306之層中的孔洞308，可以用一不同於供導孔312及導線310用的孔洞和壓痕的方式加以形成。圖4是一頂視圖，此圖顯示層306及孔洞308。雖然在該例示實施例中的孔洞308是一長方形，但是在其它的實施例中其可以是不同的形狀。
層302,304,306形成後，將該等層堆疊及加熱以形成基板104。圖5是一橫剖面視圖，此圖說明堆疊在一起以形成基板的層302,304,306。加熱堆疊的層302,304,306以硬化層而產生最後的封裝基板104。具有孔洞308的多重層306可加以對準及堆疊，以便孔洞308合起來界定凹部150。也可使用形成基板104及凹部150的其它方法。
根據本發明的一實施例，圖6是一橫剖面視圖，此圖例示層302,304,306在堆疊及加熱後的完成基板104。依據圖所顯示，完成基板104具有接觸墊602在它的頂表面上用以電性地連結基板104至晶粒102，具有接觸墊604在凹部150的頂表面上用以電性地連結基板104至在凹部150內的裝置106，及具有接觸墊606在基板104的底表面用以電性 地連結基板104至印刷電路板108。在其它的實施例中，可以使用其它有別於接觸墊的連結，例如銷或其它適合的導體，且該連結可放置在不同的地方。
圖7是一橫剖面視圖，此圖例示在凹部150範圍內具有兩個電性裝置702，704的晶粒封裝100，而有別於如圖1及圖2中僅有一種裝置。超過一種以上的電性裝置702，704可直立地堆疊在凹部150範圍內。例如，在該例示實施例中，當底部電性裝置704是一矽中電壓調節器，則頂部電性裝置702是一陣列電容器。在其它的實施例中，裝置702,704可以是不同的。頂部裝置702可以有穿透的導孔，以提供電性連結於其底表面上，該底部裝置704可耦合至該底表面。在某些實施例中，底部裝置704可電性地直接連結至頂部裝置702及該印刷電路板108兩者。在其它的實施例中，底部裝置704可僅直接連結至頂部裝置702，且透過頂部裝置702及封裝基板104而達成和印刷電路板108的電性聯繫。在其它的實施例中，其它的連結配置也是可能實行。雖然該例示的實施例顯示裝置702,704直立地堆疊，但是它們二者可以也在凹部150範圍內橫向地彼此相鄰，而非直立地堆疊。
圖8是一橫剖面視圖，此圖例示晶粒封裝100的另一實施例，在該晶粒封裝中，兩晶粒102連結到一封裝基板104，且兩個電性裝置106(例如兩陣列電容器106)在一凹部150範圍內。在此一實施例中，每一裝置106可與一晶粒102對準，並提供電容於晶粒102。雖然例示成在同一凹 部150範圍內，但是每一裝置106可以在一不同的凹部150範圍內。
圖9是一橫剖面視圖，此圖例示晶粒封裝100的另一實施例，在該晶粒封裝中，兩晶粒102連結到一封裝基板104，且兩個裝置106,120在凹部150範圍內。在此實施例中，裝置106是一陣列電容器，且裝置120是一矽中電壓調節器。在其它的實施例中，裝置106和裝置120可以是不同的。提供一單一陣列電容器106供兩個晶粒102使用，而不是一個陣列電容器106供一個晶粒102使用。同樣地，提供一單一矽中電壓調節器120供兩個晶粒102使用，而不是一個矽中電壓調節器120供一個晶粒102使用。雖然例示成在同一凹部150範圍內，但是則每一裝置106,120可以在一不同的凹部150範圍內。雖然該例示的實施例顯示裝置106,120水平地彼此相鄰設置，但是它們兩者可以也在凹部150範圍內直立地彼此堆疊。
圖10是一橫剖面視圖，此圖例示晶粒封裝100的另一實施例，在該晶粒封裝中，兩晶粒102連結到一封裝基板104且一單一的裝置在凹部150範圍內。在該實施例中，裝置是一陣列電容器106，但在其它的實施例中，裝置可以是一不同類型的電性裝置。提供一單一的陣列電容器106供兩個晶粒102使用，而不是一個陣列電容器106供一個晶粒102使用。
圖11是一橫剖面視圖，此圖再次例示晶粒封裝100的另一實施例，在該晶粒封裝中，凹部105及裝置106皆在 封裝基板的頂部而非底部。在此實施例中，裝置106直接地連結至封裝基板104及晶粒102。晶粒102直接電性地連結至封裝基板104及裝置106。其它的連結配置可以存在其它的實施例中。一個或多個晶粒102、一個或多個凹部150及一個或多個裝置106的各種配置都是可能實行的。
依此等圖顯示及以上的描述，有許多不同方法，在其不同方法中，不同類型的電性裝置106能夠配置在一陶瓷封裝基板104的一凹部150內。可有提供的多重裝置106以支持一單一晶粒102，由一單一裝置106所支持的多重晶粒102。裝置106可直立地堆疊，或平行地彼此分開設置。裝置106可在一單一凹部150或多重凹部150內。裝置106可以直接連結至印刷電路板108或晶粒102，或者經由封裝基板104連結。凹部150可以在封裝基板104的底部，在封裝基板104的頂部，或在封裝基板104的頂部及底部兩部位。
為了例示及描述的目的，前面已提出本發明實施例的描述。它無意完備或局限該發明於所揭露的精確樣式。此描述及以下的申請專利範圍所包括的用語，例如左方、右方、頂部、底部、之上、之下、較高、較低、第一、第二...等，該等用語的使用僅為了描述的目的，不能解釋為限制之用。例如，在一基板或積體電路的裝置側(或主動表面)之情況中，代表相對直立位置的用語是那基板的“頂”表面；該基板事實上可在任一方位，以至於一基板的“頂部”側可以低於參考標準地上支架中的“底部”側，且仍是在該用語“頂部”的意義內。如這裡(包括在專利申請範圍 中)使用的用語“在..之上”，「一第一層在一第二層“之上”」，不是意指一第一層直接在第二層之上並立即地與第二層接觸，除非此用語有特別地敘述；在該第一層及該第二層(在第一層之上)之間可以有一第三層或其它結構。在此描述之裝置或物品的實施例，能夠以很多的位置及方向製造、使用或運送。依據以上的教示，熟悉該相關技術者能夠領會許多修改及變動是可能的。熟悉該相關技術者，將會認知顯示在該等圖中各種零件的各種均等組合及替代品。因此，意欲本發明的範圍不是受限於這詳細的描述，而是受到附錄於此之專利請求項的限制。
100‧‧‧晶粒封裝
102‧‧‧晶粒
104‧‧‧封裝基板
106‧‧‧陣列電容器
150‧‧‧凹部
108‧‧‧印刷電路板
110‧‧‧凹部側壁
112‧‧‧頂表面
114‧‧‧厚度
302，304，306‧‧‧層
308‧‧‧孔洞
310‧‧‧導線
312‧‧‧導孔
602，604，606‧‧‧接觸墊
704‧‧‧矽中電壓調節器
116‧‧‧距離
圖1是一橫剖面視圖，此圖例示根據本發明的一實施例之一晶粒封裝。
圖2是一橫剖面視圖，此圖例示當封裝基板安裝在一印刷電路板上時的晶粒封裝。
圖3是一橫剖面視圖，此圖更詳細地例示形成基板的多重層。
圖4是一頂部視圖，此圖顯示層及孔洞。
圖5是一橫剖面視圖，此圖例示堆疊在一起以形成基板的層。
圖6是一橫剖面視圖，此圖例示在堆疊及加熱各層後的完成基板。
圖7是一橫剖面視圖，此圖例示在凹部範圍內具有兩 個電性裝置的晶粒封裝。
圖8是一橫剖面視圖，此圖例示晶粒封裝之另一實施例，在該晶粒封裝中，兩晶粒連結至一封裝基板且兩個電性裝置在一凹部範圍內。
圖9是一橫剖面視圖，此圖例示晶粒封裝的另一實施例，在該晶粒封裝中，兩晶粒連結至一封裝基板且兩種裝置在凹部範圍內。
圖10是一橫剖面視圖，此圖例示晶粒封裝的另一實施例，在該晶粒封裝中，兩晶粒連結至一封裝基板且一單一裝置在凹部範圍內。
圖11是一橫剖面視圖，此圖再次例示晶粒封裝的另一實施例，在該晶粒封裝中，凹部及裝置皆在封裝基板的頂部而非底部。
100‧‧‧晶粒封裝
102‧‧‧晶粒
104‧‧‧封裝基板
106‧‧‧陣列電容器
150‧‧‧凹部
110‧‧‧凹部側壁
112‧‧‧頂表面
114‧‧‧厚度
116‧‧‧距離

Claims (16)

  1. 一種裝置，包含：一第一積體電路晶粒；一封裝基板，該封裝基板包括：一被耦合到該第一積體電路晶粒的頂表面；一底表面；包含一陶瓷矩陣材料的多個層；由該封裝基板的該底表面往上延伸的凹部側壁及一凹陷表面，該凹部側壁及凹陷表面，係用來界定在該封裝基板底部中的一空穴；和穿透該等層的電性導線和導孔，以提供一電性的傳導電路徑，該傳導路徑係由該頂表面至在該空穴中的凹陷表面；和在該空穴中的一陣列電容器和一矽中電壓調節器，該陣列電容器係藉由至少一些電性導線和導孔而電性地連結至該第一積體電路晶粒。
  2. 如申請專利範圍第1項所述的裝置，其中該空穴具有一中心，該第一積體電路晶粒具有一中心，且該空穴的中心大約直接在該第一積體電路晶粒的中心的下方。
  3. 如申請專利範圍第1項所述的裝置，進一步包含一印刷電路板，其與該封裝基板的底表面相鄰，且電性地連結到該封裝基板及電性地連結到在該空穴中的該第一電性 裝置。
  4. 如申請專利範圍第1項所述的裝置，其中該陣列電容器是位於該矽中電壓調節器和該凹陷表面之間。
  5. 如申請專利範圍第4項所述的裝置，其中該陣列電容器，係藉由連接至該凹陷表面上之導體的該陣列電容器的一頂表面上的導體，而電性地連結到該第一積體電路晶粒；且該陣列電容器，係藉由在該陣列電容器的一底表面上的導體及在該矽中電壓調節器的一頂表面上的導體，而電性地連結到該矽中電壓調節器。
  6. 如申請專利範圍第1項所述的裝置，其中該矽中電壓調節器和該陣列電容器橫向地隔開，而不是堆疊在該陣列電容器的頂部上或在該陣列電容器的下方。
  7. 如申請專利範圍第1項所述的裝置，進一步包含一第二積體電路晶粒，其係耦合至該封裝基板的該頂表面。
  8. 如申請專利範圍第7項所述的裝置，其中該第一和第二積體電路晶粒的每一者是一微處理器晶粒。
  9. 一種半導體裝置，包含：一封裝基板，包括一陶瓷材料及在該陶瓷材料中的導線，該封裝基板具有一最大厚度；一第一積體電路晶粒係電性地連結到該封裝基板的一頂表面；和一陣列電容器及矽中電壓調節器，其在該封裝基板之底部內的一凹部內，該凹部由側壁及一頂表面所界定，介於該凹部的該頂表面及該封裝基板的該頂表面之間的厚度 ，小於該封裝基板的最大厚度。
  10. 如申請專利範圍第9項所述的裝置，進一步包含與該封裝基板之該底表面相鄰的一印刷電路板、將該封裝基板電性地連結至該印刷電路板的第一組傳導連接器、和將該陣列電容器電性地連結至該印刷電路板的第二組傳導連接器。
  11. 如申請專利範圍第10項所述的裝置，其中該印刷電路板是在一電腦系統中的一主機板。
  12. 如申請專利範圍第11項所述的裝置，其中封裝基板和陣列電容器皆藉由一基板柵格陣列承座而連結到該印刷電路板。
  13. 如申請專利範圍第9項所述的裝置，其中該陣列電容器實質上是直接在該第一積體電路晶粒之下方。
  14. 如申請專利範圍第9項所述的裝置，其中該矽中電壓調節器係在與該陣列電容器相鄰的該凹部內。
  15. 如申請專利範圍第9項所述的裝置，進一步包含一第二積體電路晶粒，其係電性地連結到該封裝基板的該頂部表面，其中該第一和第二積體電路晶粒二者皆是微處理器晶粒。
  16. 如申請專利範圍第9項所述的裝置，其中該陣列電容器，係藉由連接至該凹陷表面上之導體的該陣列電容器的一頂表面上的導體，而電性地連結到該第一積體電路晶粒；且該陣列電容器，係藉由在該陣列電容器的一底表面上的導體及在該矽中電壓調節器的一頂表面上的導體， 而電性地連結到該矽中電壓調節器。
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