TWI708336B - 包含球形陣列封裝之堆疊的３ｄ電子模組 - Google Patents

包含球形陣列封裝之堆疊的３ｄ電子模組 Download PDF

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TWI708336B
TWI708336B TW105120001A TW105120001A TWI708336B TW I708336 B TWI708336 B TW I708336B TW 105120001 A TW105120001 A TW 105120001A TW 105120001 A TW105120001 A TW 105120001A TW I708336 B TWI708336 B TW I708336B
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克里斯汀 佛
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法商３Ｄ波拉斯公司
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Abstract

本發明關於一種3D電子模組(100)，其包含：- 兩個經電性測試的電子封裝(10)，各包含至少一封裝晶片(11)與輸出球(13)於該封裝的一單一面上，該單一面稱為該主要面(15)；- 彼此機械性連接的兩撓性電路(20)，各撓性電路(20)係與一封裝(10)相關聯，且該等撓性電路定位於該兩封裝之間，各撓性電路(20)包含：○在一面(21)上，面對該相關聯封裝之該等輸出球(13)的第一電性互連墊(22)；○在其端部，折疊於該相關聯封裝之一橫向面(16)上方的一部分(26)；○在此折疊部分(26)之該相對面上的第二電性互連墊(24)。

Description

包含球形陣列封裝之堆疊的3D電子模組
本發明係關於一種用於堆疊球形封裝的技術。更具體地，本發明係關於包含球形陣列封裝之堆疊的3D電子模組。
以高頻率(記憶體、處理器等等)來操作組件之市場上的現象已經造成提出新性能問題之未封裝晶片(裸晶)的使用。在大約1GHz之頻率以上之裸晶的探針測試變得非常棘手。第一結果是，在3D電子模組中之這些組件之堆疊的情形中，特定晶片將能夠以最大頻率操作，而其他者則沒有；結果係為包含複數個晶片的模組將無法以最大頻率操作。
防止此困難發生的一種方式係為使用封裝晶片，亦即，放置在本身可完全受到測試之封裝中的晶片。具體地，一封裝包含形式為焊料球的輸出，該等焊料球比該等晶片墊相隔地更開，例如：晶片墊的間隔：50至100μm； 將晶片封裝之球形陣列封裝的間隔：從400至800μm。
測試插座因此可被使用，且該等封裝因此能夠被測試。
根據此觀察，適合這些封裝且能夠以高頻率操作的堆疊技術必須被發現。
因此提出一種用於堆疊這些型態封裝的新技術。更具體地，本發明的主題係一種3D電子模組，其包含：- 兩個經電性測試的電子封裝，各包含至少一封裝晶片與輸出球於該封裝的一單一面上，該單一面稱為主要面，其結合兩橫向面；- 定位於兩封裝之間，彼此機械性連接且定位於兩封裝之間的兩撓性電路，各撓性電路係與一封裝相關聯且包含：○在一面上，與該相關聯封裝之該等球接觸的第一電性互連墊；○在其端部，折疊於該相關聯封裝之一橫向面上方的一部分；○在此折疊部分之該相對面上的第二電性互連墊。
根據本發明的一項特徵，該兩撓性電路係藉由夾於該兩撓性電路之間的一剛性印刷電路板而彼此機械性且電性 連接。
此剛性電路可包含潛在地嵌入於剛性電路中的被動及/或主動組件。
3D模組較佳地包含環氧樹脂珠，該環氧樹脂珠沿著該等撓性電路之折疊而定位於該兩撓性電路之間之該模組的邊界上。
該兩封裝的至少一者變薄直到該晶片的一面變得可見為止；該封裝隨後有益地包含置於該晶片之該可見面上的一散熱器。
根據本發明的另一項特徵，兩撓性電路的至少一者在其另一端部被折疊於與該第一橫向面相對之該封裝的另一橫向面上方，該撓性電路包含被動及/或主動組件於此另一端部。術語「主動組件」意指裸或封裝晶片。
被動及/或主動組件一般以高於1GHz的頻率來操作。
本發明亦關於一種3D電子堆疊，其特徵在於它包含譬如所說明之數個3D電子模組的一堆疊，該等模組係藉由與該主要面相對的面而彼此接合。
本發明的另一項主題係包含互連印刷電路板與3D電子模組的3D電子裝置或譬如已經說明的一堆疊，其經由與該等撓性電路之該第二電性互連墊接觸的電性互連球而安裝在互連印刷電路板上且電性連接至該電路板。
10‧‧‧球形陣列封裝
11‧‧‧晶片
12‧‧‧環氧型樹脂
13‧‧‧輸出球
14‧‧‧外面
15‧‧‧主要面
16‧‧‧橫向面
17‧‧‧充填樹脂
20‧‧‧撓性電路
20‧‧‧撓曲電路
21‧‧‧主要面
22‧‧‧第一電性互連墊
23‧‧‧相對面
24‧‧‧第二電性互連墊
25‧‧‧焊料球
26‧‧‧折疊部分
27‧‧‧主要部分
30‧‧‧黏著劑
40‧‧‧散熱器
41‧‧‧熱連接
50‧‧‧中央剛性印刷電路板
50‧‧‧核心電路
51‧‧‧層
60‧‧‧主動與被動組件
70‧‧‧珠
100‧‧‧3D電子模組
150‧‧‧金屬化穿孔
151‧‧‧樹脂
1000‧‧‧3D電子堆疊
1001‧‧‧環氧型樹脂
Lb‧‧‧長度
Ib‧‧‧寬度
eb‧‧‧厚度
Lc‧‧‧長度
Ic‧‧‧寬度
ec‧‧‧厚度
Lf‧‧‧長度
If‧‧‧寬度
ef‧‧‧厚度
本發明的其他特徵與優點將在研讀接下來、藉由非限 制性實例所產生且參考附圖的詳細說明時變得明顯，其中：圖1圖式地顯示根據本發明之3D電子模組的第一實例；圖2圖式地顯示根據本發明之3D電子模組之元件實例的分解圖：一封裝及與其有關的撓性(或「撓曲」)電路；圖3圖式地顯示根據本發明之3D電子模組的第二實例，其具有裝配有散熱器之變薄的封裝；圖4圖式地顯示具有被動及/或主動組件之3D電子模組的第三實例：- 其係安裝在兩撓性電路(圖4a)上或- 其係整合在剛性電路(或「核心」電路)中(圖4b)或- 其係安裝在「核心」電路的表面上(圖4c)；圖5圖式地顯示具有裝備有散熱器之變薄的封裝之3D電子模組堆疊的實例，其中一些與兩個相鄰模組共享，其具有(圖5a)或不具有(圖5b)主動及/或被動組件安裝於撓曲電路上。
從一圖至另一圖，相同的組件產生相同的參考。
在該說明書的剩下部份中，表達式「高」、「低」、「前」、「後」及「側」係參考所說明圖式的定向來使用。就該模組而言，可根據其他定向來定位堆疊或裝置，方向性用詞係藉由繪示來指示且不用於限制。
根據本發明之3D電子模組的第一實例係參考圖1與圖2來說明。兩個球形陣列(BGA)封裝係安裝於包含兩個聯接撓性或撓曲印刷電路板(PCBs)之一基材的兩面上。
球形陣列(BGA)封裝10各包含以環氧型樹脂12封裝的至少一晶片11；各晶片11係連接至被定位於該封裝之單一面(稱為主要面15)上之封裝的輸出球13。具有長度Lb、寬度Ib及厚度eb的封裝10因此具有主要面15及相對面(稱為外面14)，兩者皆具有維度Lb×Ib，以及具有維度Ib×eb的橫向面16。下列的維度是典型的：- 6mm
Figure 105120001-A0202-12-0005-9
Lb
Figure 105120001-A0202-12-0005-10
9mm；- 6mm
Figure 105120001-A0202-12-0005-11
Ib
Figure 105120001-A0202-12-0005-12
14mm；- 0.8mm
Figure 105120001-A0202-12-0005-13
eb
Figure 105120001-A0202-12-0005-14
1.4mm。
意圖堆疊的這些封裝10係經它們的製造商藉由測試插座與適當測試器所電性測試，然後以測試封裝來標示。在此等測試封裝的製造商之中，可能提及：Micron、Xilinx、Samsung、Freescale、Infineon、STMicroelectronics等等。根據本發明的3D模組包含此等測試封裝。
兩測試封裝係安裝在基材的兩面上，稱為在下面、彼此面對的PCB。更具體地，PCB包含兩撓性電路20。長度Lf(Lf=Lf1+Lf2)、寬度If及厚度ef的各撓性電路20亦具有裝配有第一互連墊22(像封裝之球13分佈)的主 要面21、具有維度Lf×If的相對面23以及具有維度If×ef的橫向面。我們具有：Lf
Figure 105120001-A0202-12-0006-15
Lb+eb以及If=Ib。
以下的維度係典型的：- 7mm
Figure 105120001-A0202-12-0006-16
Lf
Figure 105120001-A0202-12-0006-17
11mm；- 6mm
Figure 105120001-A0202-12-0006-18
If
Figure 105120001-A0202-12-0006-19
14mm；- 0.8mm
Figure 105120001-A0202-12-0006-20
eb
Figure 105120001-A0202-12-0006-21
1.4mm。
通常為多層的撓曲電路20大致上由聚醯亞胺製成，亦即，在裡面不具有玻璃纖維，以便允許實質的變形，諸如折疊；聚醯亞胺亦可在沒有纖維強化之下由環氧樹脂取代。它包含電性軌跡，該等電性軌跡意圖引導訊號於第一電性互連墊22與第二電性互連墊24之間，該第一電性互連墊22定位於該撓曲的主要面21(且與該封裝的輸出球13進行接觸)，該第二電性互連墊24則定位於具有維度Lf2×If、撓曲電路之一部分26的相對面23上(其意圖在該封裝的橫向面上方折疊)；這些第二互連墊24，其在圖2中是在無法看到的面23上，其係由虛線標示。一般而言：Lf1=Lb且Lf2
Figure 105120001-A0202-12-0006-22
eb。
各封裝10因此安裝在撓曲電路20上，以致於：- 使該封裝的輸出球13與撓曲電路之主要部分27的第一互連墊22(將不被折疊)機械性且電性接觸(藉由焊接，例如藉由使用習知含鉛或沒有鉛的焊料)，撓曲電路的一部分26因此自主要部分27突 出；以及- 使該封裝的橫向面16與該撓曲電路的此(突出)部分26機械性接觸(藉由將後者折疊90°)，使得第二互連墊24與該封裝的該橫向面16齊平。
以習知方式，將充填樹脂17(例如，環氧樹脂)插入於球13之間。
這些部分26係接合至該封裝的橫向面。此接合係使用一工具或治具來實施，以允許接合至橫向面16的部分26維持完全平坦。黏著劑30扮演在該封裝的橫向面16與折疊撓性部分26之間之位準調配器的角色。這在封裝時非常重要，且特別是，BGA封裝通常在傳輸時顯現一曲率(亦稱為「翹曲」)，該曲率依據該封裝的維度可達到50至150μm；此曲率因此對球25的共面性且因而對焊接性能有害。
因此得到兩對的封裝/撓曲電路，其係本身藉由接合撓曲電路的相對面23來組裝(黏著劑未顯示於圖式中)以便最終形成具有兩封裝10與PCB的3D模組，如圖1所示。焊料球25將定位於第二互連墊24上，以便允許此3D模組安裝在使用者的印刷電路板(或PCB)上。
各封裝10可如圖3所示地變薄：在變薄之後，晶片11的後面變得可看見。變薄封裝的外面14可接收例如金屬散熱器40，以便移除由晶片11產生的熱。散熱器40隨後經由其截面而連接至冷板。在散熱器與晶片11的後面之間的熱連接41通常使用熱黏著劑或最好的使用焊料 來得到；在此後來的情形中，外面14會被金屬化，例如，經由鎳與金的化學沈積。以此方式，撓曲電路之部分26的長度Lf2增加，從而允許第二互連墊24的數目或間隔增加。3D模組可包含散熱器40於各封裝10上，如圖3所示，或單一散熱器於一封裝上，該封裝將與另一3D模組的另一封裝共享，將在下文之3D模組堆疊的情形中看見。在此情形中，長度Lf2從一撓曲電路接著另一撓曲電路地改變，如圖5a與圖5b之模組100可見。
如圖1至圖3所示，該封裝/撓曲電路對可直接或如圖4與圖5所示經由中央剛性印刷電路板50組裝，該中央剛性印刷電路板，稱為「核心」電路，具有長度Lc、寬度Ic及厚度ec，包含接地與供應面，該電路則經由具有維度Lc×Ic的它的面而機械且電性連接至兩撓曲電路20的部分27。另外要提及的是，PCB可能包含只有兩個撓曲電路20或包含「核心」電路50於兩撓曲電路20之間。實際上，包含兩撓曲電路20、在該兩撓曲電路之間具有「核心」電路50的PCB電路，其係在各封裝10安裝於PCB電路的任一側上以前首先被產生，且從該等封裝突出之兩撓曲電路的部分26則在該等封裝的橫向面16上折疊。
圖4b顯示根據本發明之3D模組的實例，在兩撓曲電路20之間的PCB中，其包含通常多層的「核心」電路50，該核心電路整合主動及/或被動組件60以及特別地解耦合電容器。在圖4b中，整合組件60之層係在一側上的 兩層51與在另一側上的三層51之間。儘可能靠近封裝10之晶片11放置的這些電容器允許電力以最小的電感傳送。主動與被動組件60係放置於「核心」電路50的厚度內；其他層隨後接合至組件，當產生PCB時，情況往往如此。金屬化穿孔150通過「核心」與兩撓曲電路(或撓曲)的全部(如圖所示)或一部份，以便進行互連。
根據在圖4c中可看見的一項替代方案，主動及/或被動組件60，特別是電容器，可被安裝在包含多數層51之「核心」電路50的表面上；這些組件60通常是非常小格式(402，亦即，1mm×0.5mm格式)的組件，其允許將足夠的空間留給將通過「核心」電路50的金屬化穿孔。組件60使用表面安裝技術而安裝在PCB上，隨後樹脂151沈積在這些組件60上，以便具有平面化表面，該平面化表面將接收黏著劑，以允許撓曲20接合。電容器(e2)的現有厚度係0.6mm，且特定供應器已經提出小於0.4mm的厚度；安裝組件60的厚度將因此是0.7mm，就(e3)而言減少至0.5mm。1.7mm至1.5mm的總厚度(e4)完全可能。
圖4a顯示具有在各封裝10之兩相對橫向面16上方被折疊之撓曲電路20的模組。主要優點係起因於功能的隔開：
- 在該封裝的橫向面16上方(在該圖式底部)被折疊且支持外部連接(球25)的撓曲。
- 在該封裝之橫向面16上方被折疊的撓曲，該面與 先前面相對(在圖式頂部處)，其具有主動及/或被動組件60(電容器、電阻器等等)及/或「緩衝」型主動電路安裝於它們的面23上，因此使「核心」電路50為非必要。
潛在地，兩撓曲電路20中只有一者包含組件60於它的上折疊部份上。
具有被動及/或主動組件(其係整合在「核心」電路中或安裝於其上或安裝在撓曲上)的此方法允許3D模組電自發地產生，像DIMM(雙排型記憶體模組)，不管它是RDIMM(註冊雙排型記憶體模組)或LRDIMM(負載縮減雙排型記憶體模組)。
較佳地，當3D模組100的PCB包含定位於兩撓曲電路20之間的「核心」電路50時，充填二氧化矽環氧樹脂的珠70則引進於藉由各撓曲電路20所各別形成(當折疊於相關封裝10之橫向面16上方時)的彎曲之間。此珠70因此在寬度If上方散開，以允許在將球25焊接至「撓曲」電路的互連墊24步驟期間避免撓曲的潛在進入。在將撓曲電路折疊於封裝的兩橫向面上方的情形中，兩珠70將如圖4a與圖5a中所示地定位。
因此得到的多數個3D模組100可被堆疊；它們一般而言使用黏著劑或環氧型樹脂1001來接合。圖5a與圖5b顯示因此包含全部六個封裝10之三個模組100的堆疊1000，但是這沒有限制，因為各封裝的熱阻不再取決於堆疊，如在重疊封裝的情形中；實際上，各封裝10具有相 同的熱阻，因為它不會受到其鄰居所影響。
在這些圖中，封裝10變薄且裝配有散熱器40，其中一些在相鄰模組100的兩封裝10之間共享，特別為了不增加堆疊1000的最終厚度。在圖5a中，撓曲電路20係在各橫向封裝面16上方被折疊，在一側上具有連接件(球25)，且在另一側上具有被動及/或主動組件60；「核心」電路50因此不需要。在圖5b中，撓曲電路20在具有連接件(球25)的單一橫向封裝面16上方被折疊，且被動及/或主動組件被整合在「核心」電路50中。 不過，上文所說明之3D模組的任一者則可使用熱黏著劑或藉由焊接彼此堆疊與接合；具有變薄封裝(不具有面對橫向面16的被動組件)的3D模組可被堆疊至具有非變薄封裝(具有被動組件等等)的3D模組上。此堆疊1000當然意圖經由各撓曲電路的第二互連墊24以及定位於這些墊上的焊料球25而機械且電性連接至使用者的互連電路(未圖示)。
相關於目前已知之一切其他者之此3D堆疊技術的主要優點很多：- 在模組的橫向面上沒有路由；- 沒有用於層間互連的聚合物導通孔(TPVs)或模具導通孔(TMVs)；- 藉由起因於使用治具之接合之架構的球的共面性；- 實質上不限於欲被堆疊之封裝的數目； - 用以將電容性去耦整合在使用者之互連PCB中的可能性；○沒有模製；○沒有模具面的金屬化；○沒有雷射蝕刻。
一項缺點可以為3D模組的高度H，該高度H係取決於標準BGA封裝的長度Lb，該長度Lb係在6mm與9mm之間變化、應該添加折疊撓曲的厚度ef以及球的厚度，亦即就在一側上方的折疊而言大約700μm至800μm。
此堆疊方法對記憶體封裝的堆疊而言特別有益。
10‧‧‧球形陣列封裝
11‧‧‧晶片
12‧‧‧環氧型樹脂
13‧‧‧輸出球
14‧‧‧外面
15‧‧‧主要面
16‧‧‧橫向面
17‧‧‧充填樹脂
20‧‧‧撓性電路
21‧‧‧主要面
22‧‧‧第一電性互連墊
23‧‧‧相對面
24‧‧‧第二電性互連墊
25‧‧‧焊料球
30‧‧‧黏著劑
100‧‧‧3D電子模組
eb‧‧‧厚度
ef‧‧‧厚度
Lb‧‧‧長度

Claims (9)

  1. 一種3D電子模組，其包含：- 兩個經電性測試的電子封裝，各包含至少一封裝晶片與輸出球於該封裝的一單一面上，該單一面稱為主要面，其結合兩橫向面；- 彼此機械性連接的兩撓性電路，其定位於該兩封裝之間，各撓性電路係與該兩封裝中的個別一封裝相關聯且各撓性電路包含：○在一面上，與該相關聯封裝之該等輸出球接觸的第一電性互連墊；○在其端部，以90°折疊且接合於該相關聯封裝之一橫向面上方並延伸一長度以僅覆蓋該橫向面的一部分；○在此折疊部分之該相對面上的第二電性互連墊。
  2. 如請求項1之3D電子模組，其中，該兩撓性電路係藉由定位於該兩撓性電路之間的一剛性印刷電路板而機械性且電性彼此連接。
  3. 如請求項2之3D電子模組，其中，該剛性印刷電路板包含被動及/或主動組件。
  4. 如請求項1之3D電子模組，包含環氧樹脂珠，該環氧樹脂珠沿著該等撓性電路之折疊而定位於該兩撓性電路之間的邊界上。
  5. 如請求項1之3D電子模組，其中，至 少一封裝被配置以變薄直到該晶片的一面變得可見為止且包含置於該晶片之該面上的一散熱器。
  6. 如請求項1之3D電子模組，其中，至少一撓性電路在其另一端部被折疊於與該第一橫向面相對之該封裝的一橫向面上方，該撓性電路包含被動及/或主動組件於此另一端部。
  7. 如請求項1之3D電子模組，包含以高於1GHz之頻率來操作的被動及/或主動組件。
  8. 一種3D電子堆疊，其特徵在於它包含如請求項1之數個3D電子模組的一堆疊，該等模組係藉由與該主要面相對的面而彼此接合。
  9. 一種3D電子裝置，包含如請求項1之3D電子模組，並且更包含互連印刷電路板，該3D電子模組經由與該等撓性電路之該第二電性互連墊接觸的互連球而安裝在該互連印刷電路板上且電性連接至該互連電路。
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US20160381799A1 (en) 2016-12-29
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