CN102099904A - 用于用薄金属触头来封装集成电路的方法和系统 - Google Patents

用于用薄金属触头来封装集成电路的方法和系统 Download PDF

Info

Publication number
CN102099904A
CN102099904A CN2009801274186A CN200980127418A CN102099904A CN 102099904 A CN102099904 A CN 102099904A CN 2009801274186 A CN2009801274186 A CN 2009801274186A CN 200980127418 A CN200980127418 A CN 200980127418A CN 102099904 A CN102099904 A CN 102099904A
Authority
CN
China
Prior art keywords
substrate
subbing
metal layer
layer
substrate metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2009801274186A
Other languages
English (en)
Inventor
L·T·阮
A·波达
S·W·李
A·S·普拉布
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of CN102099904A publication Critical patent/CN102099904A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
    • H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D1/00—Processes for applying liquids or other fluent materials
    • B05D1/32—Processes for applying liquids or other fluent materials using means for protecting parts of a surface not to be coated, e.g. using stencils, resists
    • B05D1/322—Removable films used as masks
    • B05D1/327—Masking layer made of washable film
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D2252/00—Sheets
    • B05D2252/02—Sheets of indefinite length
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45147—Copper (Cu) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01075—Rhenium [Re]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2924/15738—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950 C and less than 1550 C
    • H01L2924/15747—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19042—Component type being an inductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19043—Component type being a resistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0393—Flexible materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15—Position of the PCB during processing
    • H05K2203/1545—Continuous processing, i.e. involving rolls moving a band-like or solid carrier along a continuous production path
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/14—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation
    • H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)

Abstract

描述了用于形成触头阵列以供在封装一个或多个集成电路器件时使用的方法和布置。特别地，描述了用于形成具有小于约10μm的厚度、并且在特定实施例中在0.5至2μm之间的厚度的触头的各种方法。

Description

用于用薄金属触头来封装集成电路的方法和系统
技术领域
本发明一般涉及集成电路（IC）的封装。更特别地，本发明涉及包括薄金属互连结构的封装方法和布置。
背景技术
存在用于封装集成电路（IC）管芯的许多常规过程。举例来说，许多IC封装利用已从金属片冲压或蚀刻的金属引线框架来提供到外部器件的电互连。管芯可以借助于键合引线、焊料块或其它适当的电连接被电连接到引线框架。通常，用成型材料来密封管芯和引线框架的一部分以保护在管芯的活性侧的精密电气组件，同时使引线框架的所选部分暴露以促进到外部器件的电连接。
许多常规冲压或蚀刻引线框架具有可以在约100～300μm（4～12密耳）范围内的厚度。进一步减小引线框架的厚度可以提供多个益处，包括封装尺寸的减小和引线框架金属的节省，这降低生产成本。然而，在某些封装格式中，较薄的引线框架具有在封装过程期间翘曲的更大倾向。举例来说，翘曲在无铅引线框架封装（LLP）和四方扁平无铅（QFN）封装格式中特别有问题。可以将诸如基材带（backing tape）的支撑结构应用于引线框架以减小翘曲的风险。然而，除其它问题之外，此类结构可能招致更高的成本。
虽然用于制造引线框架或用于使用引线框架技术来封装集成电路的现有技术很适用，但是正在继续努力开发用于封装集成电路的更高效的设计和方法。
发明内容
要求保护的本发明涉及用于形成触头阵列以供在封装一个或多个集成电路器件时使用的方法和布置。在本发明的一方面，向衬底上沉积底层涂料（primer），使得衬底上的第一区域未被该底层涂料覆盖。未被底层涂料覆盖的这些第一区域形成至少第一图案。在各种实施例中，该图案可以类似于包括器件区域的至少一个阵列的引线框架面板图案。每个器件区域又可以被图案化成具有触头阵列的无铅引线框架式图案。在特定实施例中，底层涂料被印刷到衬底上。为了促进印刷，衬底可以由柔性材料形成并被卷到卷轴上。然后可以在逐卷或逐条过程中实现印刷。在底层涂料被沉积在衬底上之后，然后在沉底上溅射或以其它方式沉积基底金属层。然后可以去除底层涂料，使得被沉积在未被沉积在底层涂料上的衬底的第一区域上的基底金属层的第一部分未被与底层涂料一起去除，并且保持与衬底附接，从而形成触头阵列。在特定实施例中，底层涂料是溶于水的，并且溶剂包括水或适当溶剂介质。相反，基底金属层的第二部分和被沉积在底层涂料上的材料的任何其它部分被与底层涂料一起去除。结果得到的触头阵列可以形成有小于约10 μm、并且在特定实施例中在0.5至2 μm之间的厚度。
在某些实施例中，然后将衬底切割成面板。每个面板具有常规引线框架面板覆盖区（footprint）并包括至少一个器件区域阵列。然后，可以将集成电路管芯附着并电连接到所述至少一个器件区域阵列，使得每个管芯位于相关器件区域内。在各种实施例中，然后可以用成型材料在面板层级密封所述至少一个器件区域阵列。然后可以去除该衬底，同时留下与成型材料附接的至少基底金属层，从而使触头的至少底面被暴露。然后可以将每个密封的器件区域阵列单颗化以提供许多单独的集成电路封装。
在本发明的另一方面，描述了用于形成用于一个或多个集成电路器件的触头阵列的另一方法。在各种实施例中，在衬底上沉积基底金属层。与上述过程相反，不在衬底上对底层涂料进行图案化。在特定实施例中，通过掩模来沉积基底金属层，使得结果得到的基底金属层形成引线框架式图案或其它互连图案。基底金属层可以是单个金属层（例如，Cu）或包括基底和阻挡层的金属堆。可以将基底金属层溅射到衬底上，并且在某些实施例中，其可以具有在约0.1至0.3 μm范围内的厚度，虽然在各种替换实施例中，更薄和更厚的基底金属层可能都是期望的。
然后，使用激光烧蚀过程使以基底层涂料形成的互连图案的特征变锐利。使用激光烧蚀来使互连图案的几何结构变锐利允许形成非常细微的特征和节距。此外，通过在不使用掩模的情况下沉积基底金属层，可以产生甚至更细微的特征和节距（例如，≤10 μm）。在这些实施例中，可以单独使用激光烧蚀来形成互连图案。在限定了互连图案之后，可以增加基底金属层的厚度，并且然后该过程可以如上所述地继续进行。
根据可能的需要，前述实施例中的一个或多个的变体和特征可以被包括在另一实施例中，并且在前述实施例中的任何一个中可以使用附加变体和特征。
在研究以下图和详细说明之后，本发明的其它装置、方法、特征和优点将变得对于本领域的技术人员来说显而易见。意图在于所有此类附加系统、方法、特征和优点被包括在本说明内，在本发明的范围内，并且受到随附权利要求的保护。
附图说明
通过参考结合附图进行的以下说明，可以最好地理解本发明及其优点，在附图中：
图1A是依照本发明的一个实施例的在上面具有互连图案的包括被布置成多个面板的许多器件区域的衬底的概略顶视图。
图1B是图1A所示的面板中的一个的放大概略顶视图。
图1C是图1B所示的面板上的器件区域中的一个的放大概略顶视图。
图2是举例说明依照本发明的一个实施例的用于在衬底上形成互连图案以供在封装集成电路器件时使用的过程的流程图。
图3A～3K是依照本发明的一个实施例的封装过程的各种阶段的概略侧视图。
图4举例说明逐卷印刷过程。
图5是举例说明依照本发明的一个实施例的用于封装集成电路器件的过程的流程图。
图6A在顶视平面图中举例说明根据本发明的一个实施例的已被处理成具有集成电路器件的示例性成型条和在其上面形成的成型盖帽的衬底。
图6B在侧视图中举例说明根据本发明的一个实施例的图6A的成型条。
图7A在侧视图中举例说明根据本发明的一个实施例的衬底正在被去除的图6B的成型条。
图7B在底视平面图中举例说明根据本发明的一个实施例的衬底被去除且电互连图案被从而暴露的情况下的图6A的成型条。
图8是举例说明依照本发明的另一实施例的用于在衬底上形成互连图案以供在封装集成电路器件时使用的另一过程的流程图。
在图中，相同的参考标号有时用来表示相同的结构元件。还应认识到图中的说明是概略的且不按比例。
具体实施方式
本发明一般涉及集成电路的封装。更特别地，本发明涉及包括薄金属互连结构的封装方法和布置。
在本节中描述根据本发明的装置和方法的示例性应用。提供这些示例仅仅是为了增加背景并帮助理解本发明。因此对于本领域的一位技术人员来说将显而易见的是可以在没有这些特定细节中的某些或全部的情况下实施本发明。在其它实例中，未详细地描述众所周知的过程步骤以免不必要地使本发明含糊难懂。其它应用是可能的，使得不应将以下示例视为限制性的。
在以下详细说明中，对附图进行参考，其构成本说明的一部分，并且其中以图示的方式示出了本发明的特定实施例。虽然足够详细地描述了这些实施例以使得本领域的一位技术人员能够实施本发明，但是应理解的是这些示例不是限制性的；使得可以使用其它实施例，并且在不脱离本发明的精神和范围的情况下可以进行变化。
首先参考图1A～1C，在部分顶视平面图中示出了根据本发明的一个实施例的适合于高温处理的示例性衬底100。在各种实施例中，衬底100可以由薄柔性材料形成。举例来说，衬底100通常可以由诸如聚酰亚胺、高温纸、或能够经受住典型高温封装过程的其它适当材料之类的适当聚合物组成。如本领域的技术人员将认识到的，典型的管芯附着和固化过程可以在150℃下运行达4小时，典型的引线键合过程可以根据器件的密度在200℃下运行5至15分钟，并且典型的密封剂成型过程可以在175℃下运行达5分钟。除能够经受住前述温度和时间之外，衬底100可以由材料101形成，可以容易地向该材料101施加一个或多个金属层。更具体而言，一个或多个金属电互连图案将在初始过程阶段中被沉积到衬底100上。衬底100最后将被从电互连图案去除，因为在稍后的阶段，使（一个或多个）图案的一部分暴露在成品封装的表面上。因此，衬底100还可以由可容易地从电互连图案去除的材料组成。另外，在其中在使用之后丢弃衬底的实施例中，衬底100可以由低成本材料形成。
在所示的实施例中，可以将衬底100和相关电互连图案划分成许多面板101。图1B呈现根据本发明的一个实施例的面板101的放大顶视图。与每个面板101相关联的电互连图案包括通过一个或多个金属层的沉积形成且可以被布置成二维阵列105的多个器件区域103。每个器件区域103被布置成接纳相关集成电路管芯。在所示的实施例中，每个面板101的覆盖区和二维阵列105的相关布置与典型引线框架面板的类似。然而，二维阵列105的数目以及每个阵列内的器件区域103的数目和布置可以根据期望的末端封装的类型而变。
图1C举例说明器件区域103中的一个的放大顶视图。触头部分（在下文中也称为触头、引线或电互连）106形成适合于引线键合或焊接到集成电路管芯的图案。在所示的实施例中，触头部分106仅位于器件区域103的周界上。然而，器件区域103可以采取多种不同的图案和结构。另外，在其中相关管芯将被引线键合到触头部分106的某些实施例中，每个器件区域103可以包括适合于与相关集成电路管芯的背表面相连的管芯附着焊盘（DAP）108。每个器件区域103甚至可以包括用于产生诸如SiP（封装中系统）封装之类的封装的多个管芯附着焊盘，其包括多个管芯或用于无源元件（例如，例如电阻器、电容器和电感器）的其它焊盘。通常，接触部分106的结构将取决于要求的触头的数目、封装约束、以及管芯是否被配置为如在倒装芯片（FC）式封装中一样用于与焊接接头引线键合或连接。
图2示出了举例说明诸如上文参考图1A～1C所述的用于在衬底上形成电互连图案的示例性方法的流程图。图3A～3F每个举例说明图2的过程中的各种步骤处的布置的一部分的概略横截面图。首先，如图3A所示，在202处向衬底300（诸如图1A的衬底100）的第一表面304施加底层涂料302。在一个特定实施例中，底层涂料302由可溶于水的油墨形成。可以用任何适当手段将底层涂料302施加于表面304。举例来说，可以用适当的印刷机（例如，丝网、模板或喷墨印刷机）将底层涂料302印刷到衬底的第一表面304上。
更具体而言，在图4所示的实施例中，在侧视横截面图中示出了正在经历逐卷印刷过程的图3A的衬底300。衬底300可以包括被卷起而形成初始供应卷410的薄材料。可以将衬底300从此供应卷拉下并使其移动或以其它方式处理通过具有印刷头或其它印刷组件421的印刷机420。随着衬底300经过印刷机420，印刷组件421能够将底层涂料302印刷或以其它方式散布到用于引线框架和到衬底上的其它电互连图案的设计布局中。更特别地，可以沉积底层涂料302，使得未被底层涂料302覆盖的衬底300的表面304上的所选区域被布置成期望的引线框架或其它电互连图案。
可以使用台板430来帮助在薄衬底300通过印刷过程时对其进行引导和/或保护。在各种实施例中，在印刷过程完成时，印刷衬底300被卷起到精轧辊411上。在某些实施例中，台板430可以被加热和/或包括被耦合到台板430的一个或多个替换固化组件，从而促进用于新印刷的底层涂料的固化过程。可以从许多市售或定制喷墨印刷机的任何喷墨印刷机中选择喷墨印刷机420。在某些实施例中，可以将图4所示的装置可以布置为与许多常见的现成喷墨印刷机一起工作。可替换地，可以将定制喷墨印刷机设计为与特定底层涂料302一起工作。
在某些实施例中，在204处在衬底300的表面304上、包括在被底层涂料302覆盖的那些部分上沉积粘附前体层306。应注意的是在各种实施例中，以作为卷411的卷起形式来处理衬底300。以卷起的形式来保持衬底300对于许多后续准备和封装过程（诸如下述那些）而言可能更便宜且更快。举例来说，当前可用的生产设备能够在逐卷过程中执行局部化沉积。具体而言，在某些实施例中，可以将机器配置为在衬底的大区域上施加压力，施加真空并允许金属溅射。
粘附前体层306可以由包括金属和金属合金的任何适当材料或多种材料形成，并促进稍后施加的金属基层到衬底300的粘附。更特别地，用来形成粘附前体层306的（一种或多种）材料将在很大程度上取决于随后用来形成基底金属层的（一种或多种）材料。举例来说，粘附前体层306可以由Cr或TiW形成且可以在溅射过程中被沉积在表面304上。然而，应注意的是不是在所有实施例中都要求粘附前体层。
继续图3C，在206处在衬底300的表面上、包括在被底层涂料302覆盖的那些部分上（和在粘附前体层306上，如果适用的话）沉积基底金属层308。基底金属层308可以由包括在引线框架（通常为Cu）和键合焊盘（常常为Al）中常用的那些材料的任何适当材料，并且可以借助于任何适当过程来沉积。在特定实施例中，将Al或Cu基底金属层308溅射到衬底300上。在替换实施例中，基底金属层308可以是包括一个或多个Al或Cu层以及一个或多个阻挡层的金属堆。
根据各种实施例，然后在208处使用适当溶剂来清洗衬底300的表面并去除金属层的不需要部分；也就是说，直接在底层涂料302上的那些金属部分。举例来说，在其中底层涂料302可溶于水的实施例中，使用被适当加压的喷水（例如，在某些实施例中约为200～300 psi）来去除粘附前体层306和基底金属层308的一部分、以及被沉积在底层涂料302上的任何其它层（在各种实施例中，可以存在沉积在基底金属层下面或上面的其它层）。图3D举例说明衬底300和由未被与底层涂料302一起去除的那部分基底金属层308形成的电互连图案的一部分。在所示的实施例中，每个器件区域中的结果得到的电互连图案包括触头310和管芯附着焊盘312。
一旦限定了电互连图案，如图3E所示，可以在步骤210处增加图案的厚度（即，触头310和管芯附着焊盘312的厚度）。举例来说，可以选择性地对基底金属层308的其余部分进行镀覆以增加厚度。可以借助于例如无电镀过程、电镀过程乃至在基底金属层308上沉积导电油墨的印刷过程来实现该镀覆。在后一种情况下，喷墨印刷过程可以利用金属纳米油墨。此类金属纳米油墨可以包括导电铜、银和/或金颗粒，并且可以被固化成残渣态，使得基本上只剩下这些金属颗粒。在其它实施例中，图案的厚度可以已适合于后续封装过程。在各种实施例中，期望的是基底金属的厚度举例来说小于约25 μm且常常小于10 μm，并且在某些特定实施例中，在约0.5至2 μm的范围内，虽然其它厚度在其它实施例中是可能的且被允许。本领域的技术人员将认识到典型的冲压或蚀刻金属引线框架相反地通常具有约100至300 μm的厚度。
根据将在把相关管芯连接到触头310时使用的电连接的类型，随后可以在基底金属层308上沉积各种其它金属层。举例来说，在某些实施例，特别是其中将使用焊接接头来物理上和电气上将管芯上的键合焊盘与相关触头310连接的那些实施例中，在212处在基底金属层308上镀覆或以其它方式沉积一个或多个阻挡金属层。举例来说，此类阻挡金属可以包括Ni或Co以及诸如NiPd堆或NiPdAu堆的金属堆。（一个或多个）阻挡层的厚度可以根据要求的封装类型而变，然而，在各种实施例中约1 μm或更薄的厚度很适用。
因此，如图3F所示的实施例所示，可以在214处在基底金属层308上和任何（一个或多个）阻挡金属层上沉积保护层316。举例来说，可以在基底金属层308上闪速沉积一薄层Ag、Au或Pd或适合于引线键合和/或焊接的任何其它焊料可润湿金属。在各种实施例中，例如，保护层可以具有小于0.1 μm的厚度。每个触头310上的保护层316的暴露表面将是用于与相关管芯电连接的键合表面318。
在替换实施例中，可以在去除底层涂料302之前在基底金属层308上沉积（一个或多个）阻挡金属层和保护层316。在这些实施例中，将（一个或多个）阻挡金属层和/或保护层316的不需要部分与基底金属层308的不需要部分一起去除。这样，可以使触头310的表面已经准备好与相关管芯上的键合焊盘的电连接。
在216处将衬底300切割成单独的条或面板301（在各种实施例中，类似于面板101）。举例来说，可以沿着诸如图1中的面板101之间的线110之类的划分单独面板的线来锯割或以其它方式切割衬底300。
参考图5和图3G～3K的流程图，将描述用于封装集成电路管芯的过程。在502处，使管芯320位于相关器件区域内。在图3G所示的实施例中，每个管芯320的背表面322借助于诸如举例来说环氧树脂或粘膜的适当管芯附着材料而物理上附着于相关管芯附着焊盘312。在其中未使用管芯附着焊盘的实施例中，可以使每个管芯320直接位于衬底300上。
在图3H所示的实施例中，在504处借助于金属（例如，金或铜）键合引线326将管芯的活性表面319上的键合焊盘电连接到触头310。应注意的是本发明的实施例还很适合于在封装利用焊接接头连接的管芯时使用。在这些实施例中，可以将每个管芯倒置，并且可以使每个管芯的活性表面直接位于邻近触头310，使得管芯的活性表面上的所选键合焊盘位于相应触头上。然后，可以对键合焊盘与触头310之间的焊料（采取焊球、镀覆焊层或焊膏等形式）进行回流以产生物理上和电气上将管芯320连接到触头310的焊接接头连接。
在506处，如图3I所示，用成型材料（化合物）330来密封电连接（例如，键合引线326或焊接接头）、管芯202、以及触头310和管芯附着焊盘312的部分（如果存在的话）。成型化合物330通常是具有低热膨胀系数的非导电塑料或树脂。在优选实施例中，将整个被填充切割的衬底面板301放置在模具中并基本上同时地密封，如分别举例说明顶视图和侧视图的图6A和6B所示。在另一实施例中，可以将模具配置为使得器件区域的每个二维阵列被密封为单个单元。然而，在特定实施例中，期望的是用一个成型盖帽331将整个切割衬底面板密封，使得当稍后去除衬底301时，被填充的器件区域的二维阵列保持相互固定。更具体而言，虽然典型的引线框架面板在单独的器件阵列之间不具有添加的成型材料，但此类形成在其中金属互连图案太薄而不能具有支撑其本身的足够结构完整性的目前情况下可能是优选的。因此，可以形成单个整体成型盖帽331，其包括在器件区域的各二维阵列上形成的成型盖帽部分331'、331''和331'''中的每一个。一旦衬底面板301被去除，此类单个成型盖帽331提供对密封器件区域的支撑。
然而，由于器件阵列之间的间隔区域332之间的成型材料主要用于为面板层级运输和处理提供支撑，所以与对于在封装集成电路器件顶部的更加永久性的密封区域而言所期望的相比，可以减少这些区域中的成型材料的量。照此，如图6B所示，器件阵列之间的区域332中的总体成型盖帽331的厚度可以小于实际器件阵列上的成型盖帽的厚度。此外，如图6A所示的实施例所示，可以将释放狭槽334结合到器件区域之间的成型化合物330中。释放狭槽334本质上是成型化合物330中的间隙或空隙。此类释放狭槽334帮助释放由于密封而存在于成型面板中的应力，从而减少面板的翘曲。如将认识到的，密封面板的翘曲可以引起器件损坏，包括对触头和/或电连接的损坏。在某些实施例中，还可以使用对翘曲具有抵抗力的更加非常规或定制的成型材料来密封面板。在其它实施例中，密封条可以不包括释放狭槽以保证获得非常坚固的条。在密封之后，可以在加热烘箱中对成型化合物330进行固化（例如，如果成型化合物是热固化塑料或可能要求固化的其它材料）。
如图3J所示，然后可以在508处剥离或以其它方式去除衬底300以使触头310或管芯附着焊盘312（在适用的情况下）暴露。更具体而言，图7A举例说明薄衬底301被剥离的图6B的成型条，并且图7B在底视平面图中描绘衬底被去除且电互连图案被暴露的情况下的图6A的成型条。如所示，衬底301的最后去除得到各种触头310和管芯附着焊盘312或保持与下面的其各自的管芯或集成电路器件相连的其它电互连图案和组件。在各种实施例中，然后可以丢弃该衬底。
在去除衬底300之后，可以在510处用Sn和/或焊料来镀覆触头310的底面336（在某些实施例中，和管芯附着焊盘的底面338，如果适用的话）以促进与印刷电路板（PCB）或其它衬底上的相应接触表面的连接。
在替换实施例中，在沉积基底金属层308之前，可以在衬底300上沉积附加焊料可润湿层。附加焊料可润湿层可以适合于稍后与PCB或其它衬底上的外部触头连接，并且可以由与上述保护层316类似的材料组成。另外，可以在刚刚描述的沉积焊料可润湿层之后和沉积基底金属层308之前在衬底300上沉积（一个或多个）附加阻挡层。此附加阻挡层可以由与上述（一个或多个）阻挡层类似的材料组成。当然，如上所述，这些附加层的不需要部分将与如上所述的底层涂料一起被去除。在其中使用此类焊料可润湿层和/或阻挡层的实施例中，可以不执行510处的镀覆。
然后可以在512处单颗化密封面板以提供许多单独的IC封装340，诸如图3K所示的。可以用任何适当的手段来单颗化密封面板。举例来说，可以使用锯割、成组切割（锯割）、激光切割或等离子体切割技术来单颗化面板。本领域的技术人员将认识到所述方法可以用来产生大量的无铅引线框架封装（LLP）或四方扁平无铅（QFN）封装格式。另外，对于大多数实施例而言，不要求新的设备且处理在很大程度上遵循标准流程。
现在将参考图8的流程图来描述本发明的另一方面。该过程可以在802处从粘附前体层在诸如上述衬底300的衬底的表面上的可选溅射或以其它方式沉积开始。与图2的流程图相反，在衬底上未对底层涂料进行图案化。在804处，在衬底上沉积基底金属层。在特定实施例中，通过掩模来沉积基底金属层，使得结果得到的基底金属层形成引线框架式图案或其它互连图案。基底金属层可以是单个金属层（例如，Cu）或包括基底和阻挡层的金属堆。可以将基底金属层溅射到衬底上（虽然诸如汽相沉积的其它方法可能是适当的），并且在某些实施例中，其可以具有在约0.1至0.3 μm范围内的厚度，虽然在各种替换实施例中更薄和更厚的基底金属层可能都是期望的。
然后在806处使用激光烧蚀过程使以基底层涂料形成的互连图案的特征变锐利。在激光烧蚀过程期间，用激光束来照射基底金属层。在低激光通量下，材料被所吸收的激光能量加热并蒸发或升华。在高激光通量下，材料通常被转换成等离子体。通常，激光烧蚀指的是用脉冲激光来去除材料，但是如果激光强度足够高，可以用连续波激光束来烧蚀材料。使用激光烧蚀来使互连图案的几何结构变锐利允许形成非常细微的特征。此外，通过在不使用掩模的情况下沉积基底金属层，可以产生甚至更细微的特征和节距（例如，≤10 μm）。在这些实施例中，可以单独使用激光烧蚀来形成互连图案。在限定了互连图案之后，可以在808处增加基底金属层的厚度，并且然后该过程可以如上文参考图2和5的流程图所述地继续进行。
前述说明出于解释的目的使用特定命名来提供本发明的透彻理解。然而，对于本领域的技术人员来说将显而易见的是不要求特定细节以便实施本发明。因此，本发明的特定实施例的前述说明是出于图示和说明的目的提出的。其并不意图是穷尽性的或使本发明局限于所公开的精确形式。对于本领域的一位普通技术人员来说将显而易见的是根据上述讲授内容，许多修改和变更是可能的。举例来说，可能期望有意地使基层308变粗糙以保证与成型化合物330的更好粘附。这可以经由诸如例如褐色或黑色氧化物处理的机械和/或化学过程来实现。
选择和描述了实施例以便最好地解释本发明的原理及其实际应用以从而使得本领域的其他技术人员能够最好地利用本发明和具有适合于预期的特定使用的各种修改的各种实施例。意图在于由所附权利要求及其等价物来限定本发明的范围。

Claims (17)

1.一种用于形成用于一个或多个集成电路器件的触头阵列的方法，包括：
向衬底上沉积底层涂料，使得衬底上的第一区域未被底层涂料覆盖，并且其中，未被底层涂料覆盖的第一区域形成至少第一图案；
在所述衬底上沉积基底金属层；
用溶剂来去除底层涂料，由此，不将沉积在未被沉积在底层涂料上的衬底的第一区域上的基底金属层的第一部分与底层涂料一起去除并保持与衬底附接，从而形成触头阵列，并且由此将基底金属层的第二部分和被沉积在底层涂料上的材料的任何其它部分与底层涂料一起去除。
2.如权利要求1所述的方法，还包括在沉积底层涂料之后和在沉积基底金属层之前在衬底上溅射粘附前体层，其中，不将被沉积在衬底的第一区域上的粘附前体层的第一部分与底层涂料一起去除，并且将覆盖底层涂料的粘附前体的第二部分与底层涂料一起去除，使得沉积在粘附前体层的第一部分上的基底金属层的第一部分在去除底层涂料之后借助于粘附前体层保持与衬底附接。
3.如权利要求1或2所述的方法，还包括选择性地镀覆基底金属层的一部分以增加基底金属层的厚度，其中，由无电镀过程、电镀过程和在基底金属层的第一部分上沉积导电油墨的印刷过程所组成的组中的一个来实现该选择性镀覆。
4.如前述权利要求中的任一项所述的方法，其中，所述衬底在沉积底层涂料之前被从第一卷轴打开并随后在逐卷过程中在沉积底层涂料之后被重新卷到第二卷轴上。
5.如前述权利要求中的任一项所述的方法，其中，形成第一图案的第一区域被图案化成包括至少一个器件区域阵列的至少一个引线框架面板图案，并且其中，每个器件区域被图案化成具有触头阵列的无铅引线框架式图案。
6.如前述权利要求中的任一项所述的方法，还包括在沉积基底金属层之前沉积焊料可润湿层，所述焊料可润湿层适合于与外部触头连接。
7.如权利要求6所述的方法，还包括在沉积焊料可润湿层之后和在沉积基底金属层之前沉积阻挡层。
8.一种用于形成用于一个或多个集成电路器件的触头阵列的方法，包括：
在衬底上沉积基底金属层；
在基底金属层上使用激光烧蚀来限定由基底金属层形成的触头阵列；
在使用激光烧蚀之后选择性地镀覆基底金属层的一部分以增加触头阵列的厚度。
9.如权利要求8所述的方法，其中，通过掩模来溅射基底金属层以粗略地限定触头阵列，并且其中，使用激光烧蚀来使触头的几何结构变锐利。
10.如权利要求8或9所述的方法，还包括在沉积基底金属层之前在衬底上溅射粘附前体层。
11.如权利要求8-10中的任一项所述的方法，其中，由无电镀过程、电镀过程和在基底金属层的第一部分上沉积导电油墨的印刷过程所组成的组中的一个来实现所述选择性镀覆。
12.如权利要求8-11中的任一项所述的方法，还包括在镀覆基底金属层之后在基底金属层上沉积保护层。
13.如权利要求8-12中的任一项所述的方法，其中，所述基底金属层被图案化成包括至少一个器件区域阵列的至少一个引线框架面板图案，并且其中，每个器件区域被图案化成具有相关触头阵列的无铅引线框架式图案。
14.如前述权利要求中的任一项所述的方法，还包括将衬底切割成面板，每个面板具有常规引线框架面板覆盖区，其中，每个面板包括至少一个器件区域阵列。
15.如权利要求5或13所述的方法，还包括将多个管芯附着和电连接到所述至少一个器件区域阵列，使得每个管芯位于相关器件区域内。
16.如权利要求15所述的方法，其中，每个器件区域还包括被从基底金属层图案化的管芯附着焊盘，使得相关器件区域内的触头阵列在圆周上围绕相关管芯焊盘，并且其中，每个管芯的背表面位于相关管芯附着焊盘上。
17.如权利要求15或16所述的方法，还包括
用包括管芯和触头的至少一部分的成型材料将所述至少一个器件区域阵列密封在条上；
在密封之后去除所述衬底，同时留下与所述成型材料附接的至少所述基底金属层，从而使触头的至少底面被暴露；以及
单颗化所述至少一个器件区域阵列以提供许多单独的集成电路封装。
CN2009801274186A 2008-07-16 2009-05-18 用于用薄金属触头来封装集成电路的方法和系统 Pending CN102099904A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/174046 2008-07-16
US12/174,046 US20100015329A1 (en) 2008-07-16 2008-07-16 Methods and systems for packaging integrated circuits with thin metal contacts
PCT/US2009/044396 WO2010008673A2 (en) 2008-07-16 2009-05-18 Methods and systems for packaging integrated circuits with thin metal contacts

Publications (1)

Publication Number Publication Date
CN102099904A true CN102099904A (zh) 2011-06-15

Family

ID=41530527

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801274186A Pending CN102099904A (zh) 2008-07-16 2009-05-18 用于用薄金属触头来封装集成电路的方法和系统

Country Status (6)

Country Link
US (1) US20100015329A1 (zh)
JP (1) JP2011528507A (zh)
KR (1) KR20110034016A (zh)
CN (1) CN102099904A (zh)
TW (1) TW201005879A (zh)
WO (1) WO2010008673A2 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104870105A (zh) * 2012-12-20 2015-08-26 3M创新有限公司 在后续处理期间实现精确配准的多种油墨的印刷

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112009000666T5 (de) * 2008-03-24 2011-07-28 Murata Mfg. Co., Ltd., Kyoto Verfahren zum Herstellen eines Elektronikkomponentenmoduls
US8647966B2 (en) * 2011-06-09 2014-02-11 National Semiconductor Corporation Method and apparatus for dicing die attach film on a semiconductor wafer
JP5960532B2 (ja) * 2012-07-25 2016-08-02 株式会社ディスコ パッケージ基板の加工方法
US20140091465A1 (en) * 2012-09-28 2014-04-03 Texas Instruments Incorporated Leadframe having sloped metal terminals for wirebonding
CN205282448U (zh) * 2015-05-28 2016-06-01 意法半导体股份有限公司 表面安装类型半导体器件
TWI582863B (zh) * 2015-08-20 2017-05-11 南茂科技股份有限公司 晶片封裝製程、晶片封裝體以及具有晶片封裝體之可撓性線路載板
EP3281710A1 (de) * 2016-08-10 2018-02-14 voestalpine Stahl GmbH Coil-coating-verfahren und metallband
DE102020106742A1 (de) * 2020-03-12 2021-09-16 Auto-Kabel Management Gmbh Elektrisches Kontaktteil sowie Verfahren zur Herstellung eines elektrischen Kontaktteils
US20210376563A1 (en) * 2020-05-26 2021-12-02 Excelitas Canada, Inc. Semiconductor Side Emitting Laser Leadframe Package and Method of Producing Same

Family Cites Families (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE786148A (fr) * 1971-07-13 1973-01-12 Westinghouse Electric Corp Ameliorations aux compositions adhesives resineuses thermodurcissables,ou se rapportant a ces compositions
US4442137A (en) * 1982-03-18 1984-04-10 International Business Machines Corporation Maskless coating of metallurgical features of a dielectric substrate
JPH0715087B2 (ja) * 1988-07-21 1995-02-22 リンテック株式会社 粘接着テープおよびその使用方法
US5059454A (en) * 1989-04-26 1991-10-22 Flex Products, Inc. Method for making patterned thin film
JP2866453B2 (ja) * 1990-07-04 1999-03-08 ローム株式会社 エキスパンドテープ及びチップ部品の実装方法
US5017271A (en) * 1990-08-24 1991-05-21 Gould Inc. Method for printed circuit board pattern making using selectively etchable metal layers
US5206181A (en) * 1991-06-03 1993-04-27 Motorola, Inc. Method for manufacturing a semiconductor device with a slotted metal test pad to prevent lift-off during wafer scribing
US5728599A (en) * 1993-10-28 1998-03-17 Lsi Logic Corporation Printable superconductive leadframes for semiconductor device assembly
US5597767A (en) * 1995-01-06 1997-01-28 Texas Instruments Incorporated Separation of wafer into die with wafer-level processing
JP3467611B2 (ja) * 1995-09-29 2003-11-17 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
US5827394A (en) * 1996-07-15 1998-10-27 Vanguard International Semiconductor Corporation Step and repeat exposure method for loosening integrated circuit dice from a radiation sensitive adhesive tape backing
US6312800B1 (en) * 1997-02-10 2001-11-06 Lintec Corporation Pressure sensitive adhesive sheet for producing a chip
US6176703B1 (en) * 1997-04-18 2001-01-23 Kaltenbach & Voigt Gmbh & Co. Medical or dental treatment instrument for chip-removing treatment of body tissue or a substitute material with an abrasive tool
US5923995A (en) * 1997-04-18 1999-07-13 National Semiconductor Corporation Methods and apparatuses for singulation of microelectromechanical systems
JP3955659B2 (ja) * 1997-06-12 2007-08-08 リンテック株式会社 電子部品のダイボンディング方法およびそれに使用されるダイボンディング装置
US6023094A (en) * 1998-01-14 2000-02-08 National Semiconductor Corporation Semiconductor wafer having a bottom surface protective coating
JP3903447B2 (ja) * 1998-01-21 2007-04-11 リンテック株式会社 粘着シート
JP2000038556A (ja) * 1998-07-22 2000-02-08 Nitto Denko Corp 半導体ウエハ保持保護用ホットメルトシート及びその貼り付け方法
DE69914418T2 (de) * 1998-08-10 2004-12-02 Lintec Corp. Dicing tape und Verfahren zum Zerteilen einer Halbleiterscheibe
JP3784202B2 (ja) * 1998-08-26 2006-06-07 リンテック株式会社 両面粘着シートおよびその使用方法
US6278618B1 (en) * 1999-07-23 2001-08-21 National Semiconductor Corporation Substrate strips for use in integrated circuit packaging
US6715762B2 (en) * 1999-12-10 2004-04-06 Jo Ann F. Simmons System for providing entertainment and enhancing human relationships
US6525405B1 (en) * 2000-03-30 2003-02-25 Alphatec Holding Company Limited Leadless semiconductor product packaging apparatus having a window lid and method for packaging
US6383833B1 (en) * 2000-05-23 2002-05-07 Silverbrook Research Pty Ltd. Method of fabricating devices incorporating microelectromechanical systems using at least one UV curable tape
US6319754B1 (en) * 2000-07-10 2001-11-20 Advanced Semiconductor Engineering, Inc. Wafer-dicing process
US6524881B1 (en) * 2000-08-25 2003-02-25 Micron Technology, Inc. Method and apparatus for marking a bare semiconductor die
US6610167B1 (en) * 2001-01-16 2003-08-26 Amkor Technology, Inc. Method for fabricating a special-purpose die using a polymerizable tape
JP2003243594A (ja) * 2001-01-31 2003-08-29 Sanyo Electric Co Ltd 半導体装置の製造方法
US6873059B2 (en) * 2001-11-13 2005-03-29 Texas Instruments Incorporated Semiconductor package with metal foil attachment film
FR2832852B1 (fr) * 2001-11-29 2004-02-27 Memscap Procede de fabrication d'un composant electronique incorporant un micro-composant inductif
DE10202881B4 (de) * 2002-01-25 2007-09-20 Infineon Technologies Ag Verfahren zur Herstellung von Halbleiterchips mit einer Chipkantenschutzschicht, insondere für Wafer Level Packaging Chips
US6709953B2 (en) * 2002-01-31 2004-03-23 Infineon Technologies Ag Method of applying a bottom surface protective coating to a wafer, and wafer dicing method
US7169685B2 (en) * 2002-02-25 2007-01-30 Micron Technology, Inc. Wafer back side coating to balance stress from passivation layer on front of wafer and be used as die attach adhesive
SG105544A1 (en) * 2002-04-19 2004-08-27 Micron Technology Inc Ultrathin leadframe bga circuit package
US6812552B2 (en) * 2002-04-29 2004-11-02 Advanced Interconnect Technologies Limited Partially patterned lead frames and methods of making and using the same in semiconductor packaging
US20040058478A1 (en) * 2002-09-25 2004-03-25 Shafidul Islam Taped lead frames and methods of making and using the same in semiconductor packaging
TW582078B (en) * 2002-11-29 2004-04-01 Chipmos Technologies Bermuda Packaging process for improving effective die-bonding area
US7002239B1 (en) * 2003-02-14 2006-02-21 National Semiconductor Corporation Leadless leadframe packaging panel featuring peripheral dummy leads
JP2004300231A (ja) * 2003-03-31 2004-10-28 Nitto Denko Corp 熱剥離性両面粘着シート、被着体の加工方法および電子部品
US6914447B2 (en) * 2003-04-23 2005-07-05 Texas Instruments Incorporated High activity, spatially distributed radiation source for accurately simulating semiconductor device radiation environments
US7014727B2 (en) * 2003-07-07 2006-03-21 Potomac Photonics, Inc. Method of forming high resolution electronic circuits on a substrate
US7265032B2 (en) * 2003-09-30 2007-09-04 Intel Corporation Protective layer during scribing
US7919864B2 (en) * 2003-10-13 2011-04-05 Stmicroelectronics S.A. Forming of the last metallization level of an integrated circuit
US7244664B2 (en) * 2003-10-30 2007-07-17 Texas Instruments Incorporated Method for dicing and singulating substrates
US7009286B1 (en) * 2004-01-15 2006-03-07 Asat Ltd. Thin leadless plastic chip carrier
US7227245B1 (en) * 2004-02-26 2007-06-05 National Semiconductor Corporation Die attach pad for use in semiconductor manufacturing and method of making same
US7169651B2 (en) * 2004-08-11 2007-01-30 Advanced Semiconductor Engineering, Inc. Process and lead frame for making leadless semiconductor packages

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104870105A (zh) * 2012-12-20 2015-08-26 3M创新有限公司 在后续处理期间实现精确配准的多种油墨的印刷
CN104870105B (zh) * 2012-12-20 2017-03-01 3M创新有限公司 在后续处理期间实现精确配准的多种油墨的印刷

Also Published As

Publication number Publication date
WO2010008673A3 (en) 2010-03-11
TW201005879A (en) 2010-02-01
WO2010008673A2 (en) 2010-01-21
KR20110034016A (ko) 2011-04-04
JP2011528507A (ja) 2011-11-17
US20100015329A1 (en) 2010-01-21

Similar Documents

Publication Publication Date Title
CN102099904A (zh) 用于用薄金属触头来封装集成电路的方法和系统
CN101601133B (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
KR100346630B1 (ko) 리드프레임과그제조방법
JP4032063B2 (ja) 半導体装置の製造方法
US8003444B2 (en) Semiconductor device and manufacturing method thereof
US6586677B2 (en) Plastic integrated circuit device package having exposed lead surface
US8236612B2 (en) Partially patterned lead frames and methods of making and using the same in semiconductor packaging
CN102629599B (zh) 四边扁平无引脚封装件及其生产方法
TWI304234B (en) Semiconductor package fabrication
CN102386106B (zh) 部分图案化的引线框以及在半导体封装中制造和使用其的方法
US8383950B1 (en) Metal etch stop fabrication method and structure
US10950517B2 (en) Printed circuit board and semiconductor package
US20090302466A1 (en) Semiconductor device and method for manufacturing the same
US20120038036A1 (en) Structure for Multi-Row Leadframe and Semiconductor Package Thereof and Manufacture Method Thereof
JP2004214265A (ja) 半導体装置および半導体装置の製造方法
US20100301465A1 (en) Lead frame, lead frame fabrication, and semiconductor device
CN102165586A (zh) 引线框基板以及该引线框基板的制造方法
CN100479144C (zh) 制造半导体封装的方法
US20180053713A1 (en) Semiconductor device and corresponding method
JP2005286057A (ja) 回路装置およびその製造方法
JP3786339B2 (ja) 半導体装置の製造方法
CN102446775A (zh) 无载具的半导体封装件及其制造方法
CN108447840A (zh) 一种半导体电阻桥封装结构和工艺
JP4679000B2 (ja) 板状体
CN101325191A (zh) 芯片上具有图案的四方扁平无引脚封装结构

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
AD01 Patent right deemed abandoned

Effective date of abandoning: 20110615

C20 Patent right or utility model deemed to be abandoned or is abandoned