TW201005879A - Methods and systems for packaging integrated circuits with thin metal contacts - Google Patents
Methods and systems for packaging integrated circuits with thin metal contacts Download PDFInfo
- Publication number
- TW201005879A TW201005879A TW098118898A TW98118898A TW201005879A TW 201005879 A TW201005879 A TW 201005879A TW 098118898 A TW098118898 A TW 098118898A TW 98118898 A TW98118898 A TW 98118898A TW 201005879 A TW201005879 A TW 201005879A
- Authority
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- Taiwan
- Prior art keywords
- metal layer
- substrate
- base metal
- layer
- series
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 88
- 229910052751 metal Inorganic materials 0.000 title claims description 34
- 239000002184 metal Substances 0.000 title claims description 34
- 238000004806 packaging method and process Methods 0.000 title abstract description 10
- 239000010410 layer Substances 0.000 claims description 147
- 239000000758 substrate Substances 0.000 claims description 91
- 239000010953 base metal Substances 0.000 claims description 60
- 230000008569 process Effects 0.000 claims description 38
- 239000000463 material Substances 0.000 claims description 23
- 238000000151 deposition Methods 0.000 claims description 22
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 238000000465 moulding Methods 0.000 claims description 16
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- 238000007639 printing Methods 0.000 claims description 11
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
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- 238000000608 laser ablation Methods 0.000 claims description 6
- 239000002243 precursor Substances 0.000 claims description 6
- 229910052728 basic metal Inorganic materials 0.000 claims description 4
- 150000003818 basic metals Chemical class 0.000 claims description 4
- 239000002904 solvent Substances 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 229910052500 inorganic mineral Inorganic materials 0.000 claims description 3
- 239000011707 mineral Substances 0.000 claims description 3
- 238000007789 sealing Methods 0.000 claims 3
- 208000034656 Contusions Diseases 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 229910052732 germanium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 239000008187 granular material Substances 0.000 claims 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 7
- 239000010949 copper Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 5
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- 230000008901 benefit Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229940126639 Compound 33 Drugs 0.000 description 3
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- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
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- 229910000831 Steel Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
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- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
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- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/046—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer
- H05K3/048—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by selective transfer or selective detachment of a conductive layer using a lift-off resist pattern or a release layer pattern
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/027—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed by irradiation, e.g. by photons, alpha or beta particles
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D1/00—Processes for applying liquids or other fluent materials
- B05D1/32—Processes for applying liquids or other fluent materials using means for protecting parts of a surface not to be coated, e.g. using stencils, resists
- B05D1/322—Removable films used as masks
- B05D1/327—Masking layer made of washable film
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
- B05D2252/00—Sheets
- B05D2252/02—Sheets of indefinite length
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2224/85001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector involving a temporary auxiliary member not forming part of the bonding apparatus, e.g. removable or sacrificial coating, film or substrate
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- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
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- H05K3/16—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using spraying techniques to apply the conductive material, e.g. vapour evaporation by cathodic sputtering
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Landscapes
- Engineering & Computer Science (AREA)
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- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
Description
201005879 六、發明說明: 【發明所屬之技術區域】 本發明涉及一般的封裝積體電路(integrated circuit, ic)。尤其是,該發明涉及到封裝方法和配置,涉及薄金 屬互連結構。 【先前技術】 有一些習知用於積體電路晶粒封裝的製程。例如,許 Ο多1C封裝利用一已加蓋或自一金屬片蝕刻之金屬引線架以 提供至外部元件的電氣互連。該晶粒可藉接合線、銲料凸 塊或其他適合的電氣連接的方式電氣連接至該引線架。一 般來說,當移除經曝露的引線架的所選部份以促進至外部 元件的電氣連接時,該晶粒和該部份引線架以—模塑材|斗 膠封以在該晶粒的主動方面上保護該敏感電子組件。 許多傳統壓印或蝕刻引線架具有可能大約100至3的 微米(4至12密耳(mil))範圍的厚度。進—步減少引線 _架的厚度可提供多個好處,包括減少封裝尺寸和引線架金 屬的保護’從而降低生產成本。但是在一些封裝形式中, 在封裝製程期間,較薄的引線架具有較大的翹曲傾向。例 如在無引線引線架封裝(leadless leadframe package,LLP ) 和四方組合件無引線(quad flatpack no-lead,Qfn )封裝形 式中’趣曲的問題可能是尤其嚴重。一支持結構,如背部 膠帶’可用於引線架以減少翹曲的風險。但是,在其他問 題之中’這樣的結構可能需要較高的成本。 3 201005879 雖然使用引線架技術用於製造引線架和用於封裝積體 電路的現有技術是做的不錯,但甚至有繼續努力以發展較 有效的用於封裝積體電路的設計和方法。 【發明内容】 本申請的發明涉及用於形成一系列針對封裝一個或多 個積體電路裝置的接觸之方法和配置。在本發明某一方面 中,將一底層沉積至一基板上,致使該基板第一區域未藉 該底層所覆蓋。未藉該底層所覆蓋的該第一區域形成至少 一第一圖案。在各種實施例中,圖案可能類似於一包括至 少一系列裝置區域的引線架面板圖案。反過來,每個裝置 區域可能經圖案化成一具有一系列接觸的無引線引線架型 圖案。在一特定實施例中,該底層印刷於該基板上。為了 促進印刷,基板可以由—可撓式材料形成和在—捲筒上捲 動。然後該印刷可轉筒對捲筒或帶對帶製程完成。在該 底層/儿積到該基底上後,然後—基本金屬層經滅射或沉積 到該基板上。然後移除該底層,致使沉積在沒有沉積於底 層士之該基板的第一區域上的該基本金屬層的第一部份未 隨著該底層移除而移除並且依舊附加在該基板,因此形成 一糸列的接觸。在-特定實施例中,該底層是水溶性並且 :溶刺包括水或是適合的溶劑介質。相對昭下,沉積在底 層上的該基本合廛甩从够 A …、 層的第一。p份和任何其他部份的材料隨 著該底層移除而移除。甚々a 約10微半66 、 生的—系列接觸可能形成一小於 、 度,並且在特定的實施例中,是在0.5至2 201005879 微米β 在一些實施例中,然後將該基板切割成面板。每個面 板可具有一傳統的引線架面板足跡並且包括至少一個裝置 £域。然後積體電路晶粒可以接附和電氣連接到至少一系 列裝置區域’致使每個晶粒定位在一相關的裝置區域内。 在各種實施例中’然後至少一系列裝置區域可以模塑材料 膠封在該面板位準處。然後可以刪除基板,同時保留至少 依附該模塑材料的該基本金屬層,從而讓至少接觸的底部 © 表面曝露出來。然後經膠封的每個系列裝置區域可單一化 以提供多個個別積體電路封裝。 在本發明的另一方面中,描述用於形成一系列針對一 個或多個積體電路裝置的接觸之另一種方法。在各種實施 例中,將一基本金屬層沉積於一基板上。相對於上述製程, 沒有底層在基板上圖案化。在一特定實施例中,該基本金 屬層透過一遮罩沉積,致使產生的基本金屬層形成一引線 ❹架型圖案或其他互連圖案。該基本金屬層可以是一單一金 屬層(如銅)或一包括基本和阻擋層的金屬疊層。該基本 金屬層可濺射到該基板上,並在一些實施例中,可能有約 11至0.3微米範圍的厚度,雖然在各種替代實施例中,較 薄和較厚的基本金屬層皆可能是理想的。 ,然後以該基本層形成的互連圖案的特點是使用雷射燒 姓製程削尖。雷射燒蚀的使用以削尖該互連圖案的幾何形 狀’允許用於非常好的特點和情況的形成。此夕卜,即使較 好的特點和情況(如微米)可能藉未使用一遮罩沉積該 201005879 基本金屬層而產生。在這些實施例中’可以單獨使用雷射 燒姓以形成互連圖案。在該互連圖案定義後,該基本金屬 層的厚度可增加’並且然後該製程可能會如上述處理。 上述實施例的一種或多種變化和特點可以包含在另一 個實施例中,並且更多的變化和特點可以用在上述實施例 中任何一種,如同可預期的。 本發明的其他設備、方法、特點和優勢將是明顯的, 或者具有該領域的技術人士在審查下列圖式與詳細說明後 將明瞭。本發明意圖將落在本發明的範疇内的所有這些額 外的系統、方法、特點和優勢列入該描述,並藉所附的申 請專利範圍加以保護。 【實施方式】 本發明涉及一般的積體電路封裝。尤其是,該發明涉 及封裝的方法和配置,其涉及薄金屬互連結構。 …根據本發明的設備和方法的範例應用是在本節中描 述。这些例子僅僅提供添加内容和幫助本發明的了解。因 此可以㈣’具有該領域的技術人士可以在沒有部份或全 部的具體細節下執行本發明。在其他情況下,I所周知的 製程步驟沒有詳細說明以避免不必要的模糊本發明。其他 應用是可能的’例如’以下的例子不應該成為限制。 在下面的詳細描述中, 部份的描述和藉由說明的方 中。雖然這些實施例描述的 參考所附的圖式,其中形成一 式顯示於本發明的具體實施例 足夠詳細以使得熟知此領域的 201005879 技術人士能執行本發明,但是應理解,這些例子並不卩, 例如,在未違背本發明的精神和範缚下可使用並 他實施例。 變其 首先參考圖iAi 1C,顯示根據本發明某—實施 一適用於高溫處理的示範基板1〇〇之部份圖解頂端圖。 各種實施例中’紐⑽可由—可撓性材料形成。例如, 基板100 -般可由-適當的聚合物組成,如聚醜胺、& 紙或能夠承受典型高溫封裝製程的其他適合的材料。:: ©知該領域的技術人士們將明瞭,一典型的晶粒黏接和= 製程可能會在15(TC運作4小時,當取決於裝置的密度,一 典型的線接合製程可能會在2〇〇 運作5至15分鐘和一 型的膠封模塑製程可能會在175。。運作5分鐘。:了能夠: 受上述溫度和時間外,基板100可由一材料到一個或多個 可以隨時應用的金屬層所形成。更具體而言,在最初的製 程階段,-個或多個金屬電氣互連圖案將沉積到基板1〇〇。 最終基板100將自在稍後階段中暴露在完成封裝的表面上 霤的部份圖案的該電氣互連圖案移除。因此,基板1〇〇也可 由隨時可自電氣互連圖案移除的材料組成。此外,在實施 例中的基板是在使用後丟棄,基板100可以一低成本的材 料形成。 在說明實施例中’基板100及其相關的電氣互連圖案 可分為若干面板1〇1。圖1B呈現根據本發明某一個實施例 的一面板101的擴大圖解頂端圖。與每個面板1〇1相關的 該電氣互連圖案包括透過-個或多個金屬層的沉積所形成 201005879 的多個裝置區域103,並且其可以安排成二維陣列ι〇5。每 個襄置區域103安排成接受一相關的積體電路晶粒。在說 明實施例中’每個面板1G1収跡和二維陣列1()5的相關 配置是相似於一典型的引線架面板。然而,兩者二維陣列 105的數量以及該裝置區域1〇3的數量和配置,其中每個陣 列可根據理想的末端封裝類型而改變。 圖1C說明某一個裝置區域103的擴大圖解頂端圖。接 觸部份(以下也稱為接觸、引線或電氣互連)1〇6形成適合 用於線接合或焊接到一積體電路晶粒的一圖案。在所說明 實施例巾’接觸部份106僅適用於裝置區域1〇3的周圍。 然而,裝置面積103可承擔各種不同的圖案和配置。此外, 在一些實施例中,一相關的晶粒是以線接合到接觸部份 1〇6’每個裝置區域103可包括—晶粒黏接塾(心以㈣ pad’ DAP) 1G8,其適合用於與—相關的積體電路晶粒的背 部表面連接。每個裝置區域1〇3甚至可能包括用於產生封 裝的多個晶粒黏接墊,如系統級封I ,
SiP),其包括多個晶粒或用於被動元件的其他墊(如電阻 器 '電容器和電感器)。-般情況下’該接觸部份ι〇6的 配置將取決於所需的接觸數量、封裝的限制以及是否該晶 粒於以線接合或以焊料接點連接配置在覆晶(fHp ehip,Fc) 類型的封裝。 圖2顯示說明用於在一基板上形成一電氣互連圖案的 一不範方法之流程,如上面所述參考圖1八至ic。圖3A至 3F每個說明在圖2的製程中的各個階段的部份配置的圖解 201005879 側面圖。首先,於2〇2將—底層3()2應用到一基板_ (如 圖1A的基板100)的一第一表面3〇4,如圖从所說明。在 某一個特^的實施例中,該底層逝由水溶性墨水形成。 該底層302可以任何合適的方式制於該表面綱。例如, 底層302可以―適當的印刷機(例如,_屏幕、模板或喷 墨印刷機)印刷到該基板的第一表面3〇4。
更具體地說’圖4說明的實施例中,圖3a的基板3〇〇 以側面橫截面顯示經歷一捲筒對捲筒的印刷製程。基板3〇〇 可包括-薄材料’其捲起來以形成—初步的供應捲彻。基 板300可脫離這供應捲和移動或者以其他方式透過具有印 刷頭或其他印刷構件421的印刷機42〇處理。當基板3〇〇 經過印刷機420,該印刷構件421可以印刷或以其他方式將 底層302分配到用於在基板上的引線架或其他電氣互連圖 案之經設計的佈局。更具體地說,該底層3〇2可沉積致使 將於基板300上未藉底層302所覆蓋的表面3〇4上的所選 的區域安排成一理想的引線架或其他電氣互連圖案。 當該薄基板300經過印刷製程時,一平台43〇可用於 幫助引導及/或保護該基板。在各種實施例中,在完成印刷 製程中’將該印刷基板300捲起到完成捲々η上。在一些 實施例中,平台430可加熱及/或包括一個或多個替代固化 的構件以組合之,以便促進用於該新的印刷底層的固化製 程。噴墨印刷機420可以由任何一些隨手可取的商用或定 製噴墨印刷機所選擇。在一些實施例中,於圖4顯示的組 裝可安排以與許多共同現成的喷墨印刷機運作。另外,一 201005879 定製的喷墨印刷機可以設計成與一特定底層302運作。 在一些實施例中,在204中,一黏著先驅層300是沉 積在該基板300的表面304,其包括藉底層3〇2所覆蓋的那 些部份。應該注意的是,在各種實施例中,該基板3〇〇以 如同捲411般捲的形式處理。保持該基板3〇〇以捲的形式 可能對於許多後續的準備及封裝製程會較便宜且較快速 (如下述)。例如’現有的生產設備能夠以捲對捲的製程 進行局部沉積。具體來說,某些實施例中的一機器可能被 配置以在一大面積的基板上夾住,應用於真空並且允許金 屬濺射。 該黏著先驅層306可由任何合適的材料形成,包括金 屬和金屬合金並且促進一稍後應用的金屬基本層到基板 3〇〇的黏著。更具體地說,所利用以形成該黏著先驅層306 的材料將大大取決於隨後所使用以形成一基本金屬層的材 料。例如,該黏著前驅層306可由鉻或鈦鎢形成並且在濺 射製程中可沉積於表面304上。應當注意的是,該黏著前 驅層並不需要在所有實施例中。 繼續圖3C,在206中,一基本金屬層308沉積在基板 3〇〇的表面上,其包括藉該底層3〇2所覆蓋的那些部份(假 如有應用’則在該黏著前驅層3〇6上)^該基本金屬層3〇8 可由任何合適的材料形成,包括那些常用的引線架(通常 是銅)和接合墊(常常是鋁),以及可以任何適當的製程 方式沉積。在特定的實施例中,鋁或銅基本金屬層3〇8是 濺射到基板300。在替代的實施例中,該基本金屬層3 〇8可 201005879 能是包括一個或多個鋁或銅層的一金屬堆疊,以及一個戋 多個屏障層。 根據各種實施例中,在208中,然後用來清潔基板3〇〇 的表面和移除不需要的金屬層部份的一合適的溶劑,也就 是說,這些金屬部份直接在該底層302上◊例如,在實施 例中的底層302是水溶性,一適當的加壓水嘴射(在一此 實施例中約200 i 300碎每平方对)&用來移除該基本: 屬層308和該黏著先驅層306的部份,以及任何其他層(在 © 各種實施例中可能有其他層沉積該基本金屬層下或上), 其沉積在該底層302上。圖3D說明基板300及部份電氣互 連圖案由未隨該底層302移除的基本金屬層3〇8的部份所 形成。在說明實施例中,在每個裝置區域中產生的電氣互 連圖案包括接觸310和一晶粒黏接墊312。 一旦該電氣互連圖案經界定,在步驟21〇中該圖案的 厚度(即接觸310和晶粒黏接墊312的厚度)可能會增加, 如圖3E所示。例如,其餘基本金屬層3〇8的部份可選擇地 錄膜以增加厚度。該鑛膜可由例如一無電製程、一電鍵製 程或甚至-印刷製程的方式完成將一導電油墨沉積到該基 本金屬層綱上。在猶後的情,一喷墨印刷製程可利 用金屬奈米油墨(nanoink)。這種金屬奈米油墨可以包括 導電銅、銀及/或金顆粒,並可以固化成一殘留形式,例如, 實質上只有這些金屬顆粒存在。在其他一些實施例,該圖 案的厚度可能已經適合用於隨後的封裝製程。在各種實施 例中,用於該基本金屬的厚度理想為小於例如約25微米, 201005879 而且往往小於10微米,並在某些特定實施例中,範圍約〇_5 至2微米,但其他厚度是可能的並且允許在其他實施例中。 熟知該領域的技術人士將明瞭,一典型的壓印或蝕刻金屬 引線架,相比之下,一般具有1〇〇至300微米的等級的厚 度。 根據將用於連接相關晶粒的接觸310的電氣連接的類 型’其他各種金屬層可隨後沉積到該基本金屬層308上。 例如’在一些實施例中,尤其是將使用那些焊料接點以物 理和電氣連接到接合墊在與相關接觸310的晶粒上,在212 ® 中,一個或多個阻擋金屬層可鍍膜或以其他方式沉積在該 基本金屬層308上。例如,這種阻擋金屬可能包括鎳或鈷 以及諸如鎳把堆疊或鎳把金堆疊的金屬堆疊。阻槽層的厚 度可根據理想類型的封裝而改變,但1微米的等級或更薄 的厚度在各種實施例中運作良好。 此外’顯示於圖3F的實施例說明中,在214中,一個 保護層316可沉積在該基本金屬層308上和在任何金屬阻 擋層上。例如’一薄層的銀、金或鈀或任何其他適合用於 ❹ 線接合及/或焊接的焊料可濕性金屬可短暫地沉積在基本金 屬層308上。在各種實施例中,例如該保護層可能有小於 〇.1微米的厚度。在每個接觸310上的該經曝露的保護層316 的表面將是用於與一相關晶粒的電氣連接的黏接表面318。 在替代的實施例中,在該底層302移除之前,該阻擋 金屬層和保護層316可沉積在該基本金屬層3〇8上。在這 些實施例中’該不需要的阻擋金屬層及/或保護層316的部 12 201005879 份隨著不需要的基本金屬層308的部份移除◎這樣,該接 觸310的表面可能已經準備用於與在該相關晶粒上接合墊 電氣連接。 在216中,將該基板300切成個別的帶或面板3〇1 (類 似於在各種實施例中的面板1〇1) ^例如’該基板3〇〇可鋸 或其他方式沿著線將其切割以分成個別的面板,諸如在圖i 中的面板1 01之間的線n 〇。 參考圖5的流程圖和圖3(}至3&,一用於封裝積體電 ©路晶粒的製程將敘述於下。在5〇2巾,將晶粒32〇定位在 相關裝置區域内。在圖3G的實施例說明中,每個晶粒32〇 的背部表面322通過一合適的晶粒黏接材料(例如,環氧 樹脂或黏著膜)的方式以物理接附到一相關的晶粒黏接墊 312。在不使用晶粒黏接墊的實施例中,每個晶粒32〇可直 接定位到基板300上。 在實施例說明圖3H,在5〇4中,在該晶粒的主動表面 319上的接合墊藉金屬(例如,金或銅)接合線似的方式 電氣連接到接觸310。應當注意的是,本發明實施例也非常 適合使用在利用焊料接點連接的封裝晶粒。在這些實施例 中,每個晶粒可倒裝並且每個晶粒的主動表面可直接定位 於相鄰的接觸310,例如將在該晶粒的主動表面上的所選的 接合墊定位於該相應的接觸。然後可以將在接合墊和接觸 310之間的銲接(以焊接球’鑛膜銲接層或焊接斧等的形式) 回烊以產生焊料接點連接,其將晶粒與接觸3 1〇物理和 氣連接320。 13 201005879 在506中,該電氣連接(例如,接合線或焊料接 點)日曰粒202和部份接觸3 1〇和晶粒黏接整312 (如果存 在)以模塑材料d# 竹、化合物)330封裝,如圖31所示。該模 塑化合物330诵奢jl a 遇I是一具有較低的熱膨脹係數的非導電塑 膠或樹月日纟最佳的實施例中,將該整個位於切割基板 面板3〇1以實質上同時模塑和膠封放置,如圖6A和6B所 不,刀別說明頂部和側面。在另—項實施例中,可配置該 模塑致使每個二維陣列的裝置區域膠封成一單一單元。然 而’在特定實施例中,理想上以某一模塑罩331將整個切 割基板面板膠封,致使當稍後移除該基板301時,定位於 裝置區域的二維陣列保持填充到另一個。更具體地說,雖 然典型的引線架面板不增加在分隔的裝置陣列之間的模 塑材料,在目前的情況下這樣的形成可能是最好的由於 金屬互連圖案太薄以致於沒有足夠的結構完整性以支持自 己。因此,一單一完整模塑罩331可形成,其包含形成在 各自的裝置區域的二維陣列的每個模塑罩部份331,、331,, 和331’’’。一旦基板面板301被刪除,這種單一模塑罩331 提供支持該經膠封的裝置區域。 然而,由於該模塑材料在裝置陣列之間的該分隔地區 332之間提供主要服務’為了提供用於面板等級的運輸和處 理之支持,當與理想用於在積體電路裝置頂部的較長期晶 膠封地區相比較下’在這些地區的模塑材料的數量可能會 減少。因此,在裝置陣列之間的地區332中的整體模塑罩 331的厚度可以比在實際裝置陣列上的模塑罩的厚度小,如 201005879 圖6B所示。此外,如圖6A說明的實施例所顯示,免除狹 缝334可將在裝置區域之間的模塑化合物33〇納人。該免 除狹縫334基本上是在模塑化合物33〇中的溝槽或空隙。 這種免除狹縫334幫助緩解由於膠封所造成的在模塑面板 呈現的麼力,從而減少面板的龜曲。將明瞭的是,經膠封 的面板的翹曲可能會導致裝置損壞,包括損壞接觸及/或電 氣連接。在-些實施例中,用於抗翹曲的一較不傳統的或 定製的模塑材料也可以用來膠封面板。在其他一些實施 〇例’該經膠封的帶可能不包括免除狹縫,以確保獲得一非 常堅固的帶。在經膠封後,該模塑化合物330可在一加熱 爐固化(例如,如果該模塑化合物是一種熱固性塑膠或可 能需要固化的其他材料)。 在508中,然後基板3〇〇可以剝除或其他的方式移除 以曝露該接觸310和晶粒黏接墊312 (如有應用),如圖 3J所示。更具體地說,圖7A說明圖6B的模塑帶具有一待 剝除的薄基板301。圖7B以底部平面圖描述圖6A的具有 經移除和經曝露的電氣互連圖案的模塑帶。如所示,基板 301的完成移除導致在不同的接觸31〇和晶粒黏接墊312或 依舊與各自的晶粒或積體電路裝置下方相連接的其他電氣 互連圖案和構件。在各種實施例中,然後基板可被丟棄。 在基板300移除之後’在510中,該接觸31〇的底部 表面336 (在某些實施例中,假如有應用的話,晶粒黏接墊 的底部表面338 )可能會以錫及/或焊料鍍膜,以促進與在 印刷電路板(printe(j circuit board,PCB )或其他基板上的 15 201005879 對應的接觸面的連接。 在替代的實施例中,在該基本金屬層308沉積之前, 一額外的焊料可濕性層可沉積在基板300上。該額外的焊 料可濕性層可適合於隨後與在PCB或其他基板上的外部接 觸相連接,並且可能是由類似上文所述的保護層316的材 料所组成。此外,在剛才所說的焊料可濕性層沉積後和在 >儿積該基本金屬層308以前,一額外的阻擋層可沉積在基 板300上。這種額外的阻擋層可由類似以上所述的阻擋層 的材料所組成。當然,這些額外層的不需要的部份,如上❹ 所述隨底層移除。在使用這種焊料可濕性層及/或阻擋層的 實施例中,在510中,可能無法執行鍍膜。 在512中,然後該經膠封的面板可單一化以產出多個 個別1C封裝340’如圖3K所說明。該經膠封的面板可以任 何合適的方式來單-化。例如,該面板可使用据、鋼切割 (鋸)、雷射切割或電漿切割的技術來單一化。在熟知該 領域的技術人士將明瞭到,所描述的方法可用來產生多個 無引線引線架封裝(leadless leadframe package ’ LLp )或❿ 四方組合件無引線(qUad flatpack n〇_lead,qfn )封裝格式。 此外’對於最佳的實施例,不需要新的設備並且主要地處 理是如下標準流程所述。 現在將參照圖8的流程圖描述本發明的另一觀點。在 8〇2中’該製程可能會以隨意的濺射或以其他方式將該黏著 先ϋ層沉㈣基板的表面上而開始’如上文所述的基板 3〇〇。與圖2的流程圖相對照下,沒有底層圏案化到該基板 16 201005879 上。在804中,一金屬層沉積在該基板上。在一特定的實 施例中’該基本金屬層通過遮罩而沉積致使完成的基本金 屬層形成一弓丨線架型圖案或其他互連圖案。該基本金屬層 ΤΓΧτξ:單—金屬層(如銅)或包括基本和阻擋層的金屬 叠層。該基本金屬層可濺射到該基板上(儘管如氣相沉積 的其他方去可能是合適的),並在一些實施例中,可能有 範圍約0· 1至0.3微米的厚度,雖然在各種替代實施例中, 較薄和較厚的基本金屬層皆可能是理想的。 ® 在806中,然後以該基本層形成的互連圖案的特點是 使用田射燒餘製程削尖。在雷射燒钱的期間中,以雷射射 束照射該基本金屬層。在低雷射通量下,材料藉吸收雷射 月b量而加熱並且蒸發或昇華。在高雷射通量下,材料通常 是轉換成電槳。通常情況下,雷射燒餘是指以脈衝雷射移 除材料,但如果雷射強度是夠高的話,它是有可能以連續 波雷射射束來燒蝕材料。雷射燒蝕的使用以削尖該互連圖 案的幾何形狀,允許用於非常好的特點的形成。此外,即 使較好的特點和情況(如< 1〇微米)可能藉未使用—遮罩 沉積該基本金屬層而產生。在這些實施例中,可以單獨使 用雷射燒蝕以形成互連圖案。在8〇8中,在該互連圖案定 義後,該基本金屬層的厚度可增加,並且然後該製程可能 會如上述參照圖2和5的流程圖處理。 上述用於解釋的目以說明使用特定的術語以提供一 個深入了解本發明。然而,這將是明顯的,為了執行:發 明,熟知該領域的技術人士不需要這些具體細節。因此, 17 201005879 本發明的具體實施例的上述說明是呈現用於說明和描述的〜 目的。不意圖詳盡或限制本發明的所揭示確切形式。這將 是明顯的,對具有該領域通常技術的人士來說,許多修改 和變化有可能於上述教義中。例如,它可能是理想的,竟 圖粗糙該基本層308以確保與該模塑化合物33〇較好地黏 附。這可透過一機械及/或化學製程完成,例如,棕色或累 色氧化處理(brown or black oxide treatment)。 選擇和描述的實施例是以最好的敘述本發明的原則和 匕的實際應用,從而使熟知該領域的技術人士在當適用於 _ 特定用途設想時,能充分利用本發明和具有各種修改的各 種實施例。其意圖藉以下申請專利範圍和其他等效物界定 該本發明的範_。 【圖式簡單說明】 本發明和其優勢可藉參照上述說明並配合所附圖式得 以最佳的了解,其中: 圖1A是根據本發明某一實施例的具有一互連圖案於上 ❹ 的一基板的圖解頂端圖,其包括排列在複數個面板中的多 個裝置區域。 圖1B是於圖1A中說明的某一面板的擴大圖解頂端圖。 圖1C是於圖lBf說明的某一裝置區域的擴大圖解頂 端圖。 圖2是根據本發明某一實施例說明使用於封裝積體電 路裝置的在基板上形成互連圖案的一製程之一流程。 18 201005879 圖3A-3K是根據本發明某一實施例的一封裝製程的各 個階段的圖解側面圖。 圖4說明一捲筒對捲筒的印刷製程。 圖5是根據本發明某一實施例說明封裝積體電路裝置 的一製程之一流程圖。 圖6A是根據本發明某一實施例以頂端平面圖說明一經 製程至一示範模塑帶的基板具有積體電路裝置和隨即形成 的一模塑罩。
圖6B.是根據本發明某一實施例以側面立體圖說明圖 6A的模塑帶。 圖7A是根據本發明某一實施例以側面立體圖說明 6B的模塑帶具有一待移除的基板。 圖7B是根據本發明某一實施例以底部平面圖說 6A的模塑帶因此具有經移除和經曝露的電氣互連圖案。 圖8是根據本發明另一實施例說明使用於封裝積 路裝置的纟一基板上形成一互連圖案的另 阁。 褽程之一流程 在圖式中’類似的元件符號有時_指定相似的 ,且件。亦應意識到在圖式中的㈣是圖解的 繪製的。 疋叛比例 【主要元件符號說明】 100 基板表面 101 面板 201005879 103 裝置區域 105 二維陣列 106 接觸部份 108 晶粒黏接塾 110 線 202-216 方法的流程圖 300 基板 301 面板 302 底層 304 表面 306 黏著先驅層 308 基本金屬層 310 接觸 312 晶粒黏接塾 316 保護層 318 接合表面 319 主動表面 320 晶粒 322 背面表面 326 接合線 330 模塑化合物 331 模塑罩 331 模型罩部份 331 模塑罩部份 201005879 331 模塑罩部份 332 區域 334 免除狹縫 336 底部表面 338 底部表面 340 1C封裝 410 供應捲 411 捲 420 印刷機 421 印刷構件 430 平台 502-512 製程的流程圖 802-808 製程的流程圖 ❿ 21
Claims (1)
- 201005879 七、申請專利範圍: i、一種用於形成一系列針對一個或多個積體電路裝置 的接觸之方法,其中包括: 將一底層沉積至一基板上,致使該基板第—區域未藉 該底層所覆蓋,並且其中未藉該底層所覆蓋的該第一區域 形成至少一第一圖案; 將一基本金屬層沉積於該基板上; 以一溶劑移除該底層’藉以沉積在沒有沉積於該底層 上之該基板的第一區域上的該基本金屬層的第一部份未隨❹ 著該底層移除而移除並且依舊附加在該基板因此形成一 系列的接觸,和藉以沉積在該底層上的該基本金屬層的第 一。卩伤和任何其他部份的材料隨著該底層移除而移除。 2、 如申請專利範圍第!項之方法,進一步包括在沉積 該底層之後和沉積該基本金屬層之前錢射一黏著前驅層於 該基板上’其中沉積於該基板第一區域上的該黏著先驅層 第-部份未隨著該底層移除而移除,並且重疊該底層的該 黏著先驅層第二部份是隨著該底層移除而㈣致使藉自〇 在該底層移除後的該黏著先驅層的方式,沉積在該黏著前 驅層第一部份的基本金屬層第一部份依舊附加在該基板。 3、 如申請專利範圍第Μ之方法,其中該基本金屬層 的厚度約小於1 0微米。 4、 如申請專利範圍第!項之方法,進一步包括將該基 本金屬層的部份選擇性鍍膜使得該基本金屬層的厚度增 加,其中,該選擇性鍍膜是由一無電製程、一電鍍製程和 22 201005879 一印刷製程所組成的群組擇一達成,使得一導電油墨沉積 在該基本金屬層第一部份上。 5、 如申請專利範圍第1項之方法,其中基板由一高分 子材料或一高溫規格紙所形成。 6、 如申請專利範圍第丨項之方法其中在以捲筒對捲 筒的製程中,在該底層沉積之前將該基板自第一捲筒展 開,在沉積該底層後將該基板隨後重新捲到第二捲筒上。 7、 如申請專利範圍第丨項之方法,其中將該底層印刷 ❹ 至該基板上。 8、 如申請專利範圍第丨項之方法,其中該底層是水溶 性並且該溶劑包括水。 9、 如申請專利範圍第丨項之方法,其中將形成該第一 圖案的第一區域圖案化成至少一個包含至少一系列裝置區 域的引線架平面圖案,並且其中將每個裝置區域圖案化成 一具有一系列接觸的無引線引線架型態圖案。 ❹ 10、 如中請專利範㈣9項之方法,進—步包括將該 基板切割成面&,每個面&具有一習#的引線架面板足 跡,其中每個面板包含至少一系列的襞置區域。 11、 如申請專利範圍第9項之方法,進一步包括將複 數個晶粒接附和電氣連接到至少一系列的裝置區域,致使 將每個晶粒定位在一相關裝置區域内。 12、 如申請專利範圍第11項之方法1中每個裝置區 域進-步包括自該基本金屬層圖案化的一晶粒接附塾,致 使在該相關裝置區域内的該系列接觸環環相繞著該相關晶 23 201005879 粒接附墊’並且其中將每個晶粒的背部表面定位在一相關 晶粒接附墊上。 13、如中請專利範圍第μ之方法,其中利用接合線 將在該晶粒的主動表面上之1/0》與自該相關裝置區域的 相關接觸電氣連接。 U、如中請專利範圍第11Jg之方法,其中每個晶粒的 主動表面包括複數個1/0塾,並且其中將每個ι/〇塾定位在 一相關接觸上’該方法進-步包括在該I/Q墊和相關接觸之 間回焊焊料以將該晶粒物理和電氣連接到相關接觸。 15、如申請專利範圍第丨丨項之方法,進一步包括: 將在-帶上至少一系列的裝置區域以模塑材料膠封, 其包括至少部份的晶粒和接觸; 在該膠封之後移除該基板,同時保留至少依附該模塑 :枓的該基本金屬4,從而讓至少接觸的底部表面曝露出 裝 將至)-裝置區域單一化以提供多個個別積體電路封 請專利範圍第】項之方法,進—步包括在沉 之前沉積—焊料可濕性層,該焊料可濕性 層適合與外部捿觸連接。 「、如申請專利範圍第16項之方法,進—步包括在沉 ^ ^可錢沉積層之後和沉積該基本金屬層 —阻擋層。 貝 U、如申請專利範圍第i項之方法,其中在使用雷射 24 201005879 燒#之前該基本金屬層的厚声矣太 幻厚度為在約0-1至〇.3微米的範圍 内0 19、如申請專利範圍第1項之方法,進-步包括在沉 積該基本金屬層之前將一黏著前驅層機射在該基板上。 2〇、如申請專利範圍第i項之方法,其中選擇性鑛膜 由一無電製程、-電鑛製程和一印刷製程所組成的群組擇 一達成,使得一導電油墨沉積在該基本金屬層第一部份上。 2卜如申請專利範圍帛丨項之方法,進一步包括在將 〇該基本金屬層鍍膜之後將一保護層沉積在該基本金屬層 上。 22、 如申請專利範圍第21項之方法,進一步包括在沉 積該保護層之前將一阻擋層沉積在該基本金屬層上。 23、 如申請專利範圍第i項之方法,其中將該基本金 屬層圖案化成至少一個包含至少一系列裝置區域的引線架 面板圖案,並且其中將每個裝置區域圖案化成一具有一相 關系列接觸的無引線引線架型態圖案。 ® 24、如申請專利範圍第23項之方法,進一步包括將該 基板切割成面板,每個面板具有一習知的引線架面板足 跡’其中每個面板包含至少一系列的裝置區域。 25、 如申請專利範圍第23項之方法,進一步包括將複 數個晶粒接附和電氣連接到至少一系列的裝置區域,致使 將每個晶粒定位在一相關裝置區域内。 26、 如申請專利範圍第25項之方法,其中每個裝置區 域進一步包括自該基本金屬層圖案化的一晶粒接附墊,致 25 201005879 使在該相關裝置區域内的該㈣接觸環環相繞著該相關晶 粒接附墊,並且其中將每個晶粒的背部表面定位在一相關 晶粒接附墊上。 27、 如申請專利範圍第25項之方法,其中利用接合線 將在該晶粒的主動表面上之1/0墊與自該相關裝置區域的 相關接觸電氣連接。 28、 如申請專利範圍第25項之方法,其中每個晶粒的 主動表面包括複數個I/O墊’並且其中將每個1/〇墊定位在 一相關接觸上,該方法進一步包括在該1/(3墊和相關接觸之❿ 間回焊焊料以將該晶粒物理和電氣連接到相關接觸。 29、 如申請專利範圍第25項之方法,進一步包括: 將在一帶上至少一系列的裝置區域以模塑材料膠封, 其中包括至少部份的晶粒和接觸; 在該膠封之後移除該基板,同時保留至少依附該模塑 材料的該基本金屬層’從而讓至少接觸的底部表面曝露出 來;和 將至少一裝置區域單一化以提供多個個別㈣電路封❹ 襞。 30、 一種用於形成一系列針對一個或多個積體電路裝 置的接觸的方法,其中包括: 將一基本金屬層沉積在一基板上; 在該基本金屬層上使用雷射燒蝕以界定自該基本金屬 層所形成的一系列接觸; 在使用雷射燒蝕之後將該基本金屬層的部份選擇性鍍 26 201005879 膜以增加一系列接觸的厚度。 31、如申請專利範圍第30項之方法,其中透過一遮罩 將該基本金屬層濺射以大約界定一系列接觸,並且其中雷 射燒蝕是用來將該接觸的幾何形狀明確。 八、圖式: (如次頁)27
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WO2009119374A1 (ja) * | 2008-03-24 | 2009-10-01 | 株式会社村田製作所 | 電子部品モジュールの製造方法 |
US8647966B2 (en) * | 2011-06-09 | 2014-02-11 | National Semiconductor Corporation | Method and apparatus for dicing die attach film on a semiconductor wafer |
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-
2008
- 2008-07-16 US US12/174,046 patent/US20100015329A1/en not_active Abandoned
-
2009
- 2009-05-18 JP JP2011518750A patent/JP2011528507A/ja active Pending
- 2009-05-18 CN CN2009801274186A patent/CN102099904A/zh active Pending
- 2009-05-18 WO PCT/US2009/044396 patent/WO2010008673A2/en active Application Filing
- 2009-05-18 KR KR1020117003545A patent/KR20110034016A/ko not_active Application Discontinuation
- 2009-06-06 TW TW098118898A patent/TW201005879A/zh unknown
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WO2010008673A3 (en) | 2010-03-11 |
JP2011528507A (ja) | 2011-11-17 |
KR20110034016A (ko) | 2011-04-04 |
US20100015329A1 (en) | 2010-01-21 |
CN102099904A (zh) | 2011-06-15 |
WO2010008673A2 (en) | 2010-01-21 |
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