JP2866453B2 - エキスパンドテープ及びチップ部品の実装方法 - Google Patents

エキスパンドテープ及びチップ部品の実装方法

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Publication number
JP2866453B2
JP2866453B2 JP2176848A JP17684890A JP2866453B2 JP 2866453 B2 JP2866453 B2 JP 2866453B2 JP 2176848 A JP2176848 A JP 2176848A JP 17684890 A JP17684890 A JP 17684890A JP 2866453 B2 JP2866453 B2 JP 2866453B2
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JP
Japan
Prior art keywords
tape
preform layer
chip
wafer
preform
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2176848A
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English (en)
Other versions
JPH0464250A (ja
Inventor
和孝 柴田
豊 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
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Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP2176848A priority Critical patent/JP2866453B2/ja
Priority to US07/816,398 priority patent/US5316853A/en
Publication of JPH0464250A publication Critical patent/JPH0464250A/ja
Application granted granted Critical
Publication of JP2866453B2 publication Critical patent/JP2866453B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)
  • Die Bonding (AREA)

Description

【発明の詳細な説明】 （イ）産業上の利用分野 この発明は、半導体ウェハのダイシング時に用いられ
るエキスパンドテープ及びチップ部品の実装方法に関す
る。
（ロ）従来の技術 従来、半導体ウェハのダイシング時には、エキスパン
ドテープが使用される。このエキスパンドテープは、展
伸性を有する合成樹脂フィルムよりなり、第３図（ａ）
に示すように、その表面11aにウェハ14をはりつける。
この状態で、ウェハ14をダイシングし〔第３図（ｂ）参
照〕、エキスパンドテープ11を引き伸ばすと、ウェハ14
がチップ15,…,15に分離する〔第３図（ｃ）参照〕。こ
れらチップ15は、次のダイボンディング工程で、プリフ
ォーム材（例えば銀やはんだのペースト）を用いて、リ
ードフレーム等にダイボンディングされる。
（ハ）発明が解決しようとする課題 上記従来のエキスパンドテープを用いるダイシング工
程は、ダイボンディング工程とは別個のものであり、工
程数が多くなり、それだけ人員も必要となる問題があっ
た。一方、エキスパンドテープとは別にプリフォーム材
を管理する手間が必要である問題点もあった。
この発明は、上記に鑑みなされたもので、工程を簡略
化し、また材料管理の手間が省けるエキスパンドテープ
及びチップ部品の実装方法の提供を目的としている。
（ニ）課題を解決するための手段及び作用 上記課題を解決するため、この発明のエキスパンドテ
ープは、ウェハのダイシング後に引き伸ばすことを前提
とするエキスパンドテープであって、展伸性を有するフ
ィルム上に、はんだ材としてのプリフォーム層を形成し
てなるものであり、ウェハをはりつけダイシングを行っ
た後、テープを引き伸ばしてチップをプリフォーム層と
共に分離してからチップをテープ上より取り上げた時、
チップ底面にプリフォーム層が付着した状態となってい
る。
従って、そのまま直ちにリードフレーム等にダイボン
ディングすることができ、工程の簡略化及び人員の削減
を図ることができる。又、プリフォーム層がエキスパン
ドテープと一体となっているから、材料管理の手間が省
ける。
一方、この発明のチップ部品の実装方法は、展伸性を
有するフィルム上にはんだ材としてのプリフォーム層を
形成してなるエキスパンドテープのプリフォーム層上に
ウェハを設け、次にウェハをプリフォーム層と一緒に個
々のチップに切断し、更にエキスパンドテープを延伸方
向に引き伸ばしてチップをプリフォーム層と共に個々に
分離した後、それぞれプリフォーム層が底面に付着した
各チップをピックアップし、そのプリフォーム層により
チップを実装対象物にダイボンディングすることを特徴
とする。
（ホ）実施例 この発明の一実施例を第１図及び第２図を用いて以下
に説明する。
第１図は、実施例に係るエキスパンドテープ１の断面
を示している。このエキスパンドテープ１は、展伸性を
有する合成樹脂フィルム２上に、はんだ材としてのプリ
フォーム層３を形成してなるものである。プリフォーム
層３は、例えば銀ペーストやはんだペーストを塗布して
形成される。
第２図（ａ）〜（ｄ）は、この実施例に係るエキスパ
ンドテープ１を用いたチップ部品の実装方法におけるダ
イシング工程を順に示す図である。まず、エキスパンド
テープ１のプリフォーム層３上にウェハ４がはりつけら
れる〔第２図（ａ）参照〕。次に、ダイシングソウ（図
示せず）を用いてウェハ４をチップ5,…,5に切断する。
この時、ダイシング溝6,…,6の深さは、フィルム２に達
するようにして、プリフォーム層３も切断されるように
する〔第２図（ｂ）参照〕。
この状態でエキスパンドテープ１に引張力を加えて伸
ばすと、チップ5,…,5が分離する〔第２図（ｃ）参
照〕。この時、プリフォーム層３もチップ5,…,5と共に
3a,…,3aに分離する。
分離されたチップ５は、第２図（ｄ）に示すように、
コレット７で吸着しピックアップする。この時、チップ
５底面に、分割されたプリフォーム層3aが付着してい
る。このため、直ちにチップ５をリードフレーム層にダ
イボンディングすることができ、工程の簡略化を図るこ
とができる。
（ヘ）発明の効果 以上説明したように、この発明のエキスパンドテープ
は、ウェハのダイシング後に引き伸ばすことを前提とす
るものであり、展伸性を有するフィルム上に、はんだ材
としてのプリフォーム層を形成してなることで、ウェハ
をはりつけダイシングを行った後、テープを引き伸ばし
てチップをプリフォーム層と共に分離してからチップを
テープより取り上げれば、チップ底面にはんだ材として
のプリフォーム層が付着した状態になるので、はんだを
使用せずにそのまま直ちにリードフレーム等にダイボン
ディングすることが可能となり、工程の簡略化及び人員
の削減を図ることができると共に、プリフォーム材の管
理の手間を省くことができる。
【図面の簡単な説明】
第１図は、この発明の一実施例に係るエキスパンドテー
プの要部断面図、第２図（ａ）、第２図（ｂ）、第２図
（ｃ）及び第２図（ｄ）は、それぞれ順に同エキスパン
ドテープを用いたチップ部品の実装方法におけるダイシ
ング工程を説明する図、第３図（ａ）、第３図（ｂ）及
び第３図（ｃ）は、それぞれ順に従来のエキスパンドテ
ープを用いたダイシング工程を説明する図である。 1:エキスパンドテープ、2:フィルム、 3:プリフォーム層、4:ウェハ、 5:チップ。

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】ウェハのダイシング後に引き伸ばすことを
    前提とするエキスパンドテープであって、展伸性を有す
    るフィルム上に、はんだ材としてのプリフォーム層を形
    成してなるエキスパンドテープ。
  2. 【請求項２】展伸性を有するフィルム上にはんだ材とし
    てのプリフォーム層を形成してなるエキスパンドテープ
    のプリフォーム層上にウェハを設け、次にウェハをプリ
    フォーム層と一緒に個々のチップに切断し、更にエキス
    パンドテープを延伸方向に引き伸ばしてチップをプリフ
    ォーム層と共に個々に分離した後、それぞれプリフォー
    ム層が底面に付着した各チップをピックアップし、その
    プリフォーム層によりチップを実装対象物にダイボンデ
    ィングすることを特徴とするチップ部品の実装方法。
JP2176848A 1990-07-04 1990-07-04 エキスパンドテープ及びチップ部品の実装方法 Expired - Fee Related JP2866453B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2176848A JP2866453B2 (ja) 1990-07-04 1990-07-04 エキスパンドテープ及びチップ部品の実装方法
US07/816,398 US5316853A (en) 1990-07-04 1991-12-27 Expand tape

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2176848A JP2866453B2 (ja) 1990-07-04 1990-07-04 エキスパンドテープ及びチップ部品の実装方法
US07/816,398 US5316853A (en) 1990-07-04 1991-12-27 Expand tape

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JPH0464250A JPH0464250A (ja) 1992-02-28
JP2866453B2 true JP2866453B2 (ja) 1999-03-08

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JP2004273895A (ja) * 2003-03-11 2004-09-30 Disco Abrasive Syst Ltd 半導体ウエーハの分割方法
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JP2008235398A (ja) * 2007-03-19 2008-10-02 Disco Abrasive Syst Ltd デバイスの製造方法
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US7749809B2 (en) * 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
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