CN102097399A - 芯片层叠和3-d电路的热传导 - Google Patents
芯片层叠和3-d电路的热传导 Download PDFInfo
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Abstract
本发明涉及一种芯片层叠和3-D电路的热传导。一种半导体器件组件和方法可包括单个半导体层或层叠半导体层,例如半导体晶片或晶片部分(半导体管芯)。在每个半导体层上,穿过其中形成的金刚石层可有助于热的传送和消散。金刚石层可包括半导体层的后部上的第一部分和垂直延伸到半导体层内——例如,完全穿过半导体层——的一个或多个第二部分。然后可形成至金刚石层的热触点以使热传导而离开一个或多个半导体层。可穿过金刚石层形成导电通孔,以提供信号传送和散热能力。
Description
相关申请的交叉引用
此申请要求2009年12月10日提交的美国临时专利申请S/N 61/285,325和2010年1月15日提交的美国临时专利申请S/N 61/295,292的优先权,以上申请通过引用结合在本文中。
具体实施方式
以下将具体参考本教示的现有实施例(示例性实施例),在附图中示出其示例。在可能的时候,将在全部附图中使用相同的附图标记来指示相同或相似的部分。包含在此说明书中且构成此说明书一部分的附图例示了本发明的实施例,而且与说明书一起用来说明本发明的原理。在附图中:
图1是根据本教示的实施例的半导体器件的立体图;
图2-6是描绘根据本教示的实施例的各种器件结构的横截面图;以及
图7-13是在用于形成根据本教示实施例的器件的本教示的过程实施例期间形成的中间结构的横截面图。
应当注意到,已经简化了附图的一些细节,并将这些附图绘制成便于理解本发明实施例而不是保持严格的结构精度、细节和比例。
金刚石层是有效的导热体。在本公开的实施例中,可形成金刚石层以提供热传导路径,从而引导热离开层叠模块的内部和/或垂直穿过该层叠模块。
金刚石材料可以是未掺杂的,例如提供导热但电绝缘的层。在其它使用中,金刚石层可包括掺杂剂浓度以提供导电连接器,例如,足以获得可有效地用于降低衬底噪声和衬底电阻的导电和导热金刚石层的P+硼浓度,其可使器件闭锁(device latch-up)最小化。可在衬底上沉积或生长金刚石的同时利用注入或原位掺杂将掺杂剂引入金刚石材料。
图1是本教示的实施例的立体图。图1描绘半导体组件10,其可包括在半导体层16的前(电路)侧或表面14上形成的互连层(电路)12。半导体组件可以是功能半导体器件、功能半导体器件的一部分或处于制造过程中的半导体器件。半导体层可包括,例如,半导体晶片、单个半导体管芯、外延半导体层、包括半导体晶片和外延层的半导体衬底组件、诸如半导体晶片的一部分的多个未单立半导体管芯。
图1还描绘集成电路(IC)焊盘18,诸如在半导体层16的前面上形成的接合焊盘或互连焊盘。图1的器件还描绘了在半导体层16的电路侧14上形成的热传导焊盘20和在半导体层16的后(非电路)侧或表面24上形成的金刚石层22。金刚石层22可至少部分地延伸穿过半导体层16或完全穿过半导体层,如图2所示。
半导体层可包括诸如金属氧化物半导体(MOS)器件、双极结型晶体管(BJT)之类的一个或多个有源器件、诸如扩散电阻器之类的电阻器等。诸如密封环、触点、通孔、金属、层间电介质、多晶硅等其它结构也可形成在半导体层上和/或半导体层内。
图2的横截面图描绘在可控塌陷芯片连接(“CCCC”或“C4”连接)32、34形成之后的、根据图1器件沿A-A的器件30。可由金刚石层22部分地提供热传导和传输。此外,穿过衬底的通孔(TSV)36可用于使热垂直穿过器件30。形成于金刚石层22的后表面37上的C4连接38可与TSV 36相连接以将热传送到相邻衬底。因此,在一种使用中,提供从连接到C4连接34的表面、到焊盘20,到TSV 36,到C4连接38、然后到诸如印刷电路板(PCB)、类似于器件30的另一个器件或另一个接收衬底之类的接收衬底的热传输路径39。热传输可发生在连接34和38之间或者离开金刚石层22且朝向两个连接34和38的方向上。
可形成金刚石层22使之从半导体层16的后表面24延伸且穿过半导体层16。TSV 36可接触金刚石层22和焊盘20,该焊盘20具有与半导体层的前(电路)侧或表面共面的平坦表面。可形成,例如,如图所示的其它金属化结构。
其它C4连接40可仅连接至金刚石层22,且可用于使热离开金刚石层22传输到C4连接40所附连的接收衬底(未示出)。在另一个实施例中,C4连接38、40可从另一个器件接收热,并使热横向地传送而穿过金刚石层22以便散热。
金刚石层22还可提供离开连接至热传导焊盘20和C4连接32的有源电路的热传导。如图2所示,三个金属化层42用于将电输入/输出(I/O)信号通过电路横向地传输到其它器件或器件电路,并且将器件运行期间产生的热沿路径43垂直传输到金刚石层22以便从电路传导出去。在半导体层16的前表面上形成的金属化层42可包括一个或多个导体。另外,可形成一个或多个介电层44和钝化层46用于电隔离。
可利用市场上可大批量购买到的背面有金刚石的晶片来形成图2的器件30,这些背面有金刚石的晶片诸如硅晶片,或者可在晶片的背面上生长、附连或以其它方式设置背面金刚石层。对于金刚石具有选择性的蚀刻(即,蚀刻金刚石的速率低于蚀刻硅的速率)可用于蚀刻而穿过硅前表面,以通过沟槽、通孔或另一个开口(在本文中合称为“沟槽”或“开口”)使金刚石从晶片的前面暴露。因此,从电路侧蚀刻硅且从硅的前表面暴露金刚石。接下来,可进行金刚石生长工艺,以便例如利用金刚石填充工艺在暴露的平坦金刚石层上并且穿过硅中的开口生长金刚石。提供金刚石晶体结构的后侧金刚石层可在金刚石穿过开口的生长期间用作金刚石晶核。金刚石沉积方法可包括,例如,在约700℃的温度下的甲烷的热灯丝分解。
一旦已经生长了金刚石使之延伸而穿过硅层中的开口,就可,例如,利用化学机械抛光(CMP)工艺或蚀刻来使金刚石平坦化,从而使上表面平坦化。可使延伸穿过硅中开口而生长的金刚石层平坦化,使得它一般与半导体层前表面共面。因此图2的结构包括金刚石层22,其具有平坦下部和从下面的平坦层延伸且穿过半导体层16的垂直定向的金刚石层部,该垂直定向的金刚石层部可与半导体层16的前表面14共面。
在半导体器件30的使用中,可采用图2中器件30的形貌,其利用金刚石填充的沟槽区和至热传导焊盘20的接触以使热垂直地离开半导体层16传送到金刚石层22。在图2的左侧描绘的C4连接32(例如,球栅阵列“BGA”)因此可用于从附连C4连接的表面离开、穿过金属化层42至金刚石层22的热传导。然后热可穿过C4连接传导到接收衬底。热还可横向地传导而穿过金刚石层22。
图3描绘图2的热传导焊盘的一部分的放大图(图2中包括C4连接32的两个左侧结构)。可用金刚石衬底层52和金刚石沟槽填充54在随后器件的使用期间传热,使热快速离开半导体层16。可由金属化层(图2中的42)中使用的金属系统(金属化)来提供至金刚石沟槽填充54顶部的热传导。在该特定情况下,用三层金属来形成结构56-66,可利用金属镶嵌工艺和三个电介质层44A-44C来形成结构56-66。穿过钝化层46的焊盘开口50可暴露顶部金属66以完成如图所示的热传导焊盘。
图3的结构可包括用于形成至金刚石填充54的触点56和金属互连层58的金属层1、用于形成至金属层58的通孔60和金属互连层62的金属层2以及用于形成通孔64和金属互连层66的金属层3。在这种使用中,触点56不用于向金刚石沟槽填充54传送电信号,而通孔60、64分别在层58和62之间以及层62和66之间传送电信号。因此这三个金属层包括至金刚石填充54的触点层56和两个通孔层60、64。C4互连32可用于提供从焊盘66的顶部至类似于图2和3的组件的另一个芯片组件的热传导。后侧C4连接40可用于将后侧金刚石层52热耦合到接收衬底(未示出)。因此热可从硅层16传送至金刚石层52,至C4连接40,至接收衬底。在另一种使用中,热可从另一个器件的焊盘传送至C4连接40,至金刚石层52,横向穿过金刚石层52至散热片以便散热。在实施例中,导体40适用于在器件运行期间向金刚石层传导热或使热离开金刚石层,但不适用于在器件运行期间传导电信号。
图4描绘图2的热传导焊盘的一部分的放大图(图2的右侧结构)。在该实施例中,将不会在该器件上形成图2的C4结构34,但将由类似于图4器件的另一个器件提供。将形成C4连接38以通过TSV 36从金属58-66并从连接至金属66的另一个器件接收热。在形成图2的接合焊盘20之后,可将另一个器件上的类似于38的C4结构附连至金属66,使得热可通过通孔36传送至焊盘68再到C4连接38。这可提供具有优于先前层叠器件的改进的热处理的层叠器件设计。
因此图4描绘从硅-金刚石IC衬底16、52、54的后侧加工的TSV 36,其可用于从另一个器件发送热或将热发送到另一个器件。TSV形成过程可包括穿过后侧金刚石层52、穿过硅16并穿过介电层44C的沟槽蚀刻,以便通过一个或多个通孔开口从硅-金刚石复合晶片的后侧暴露金属158。例如,利用钨的金属填充的后续导电层沉积可填充一个或多个通孔,以提供至金属1结构58的电接触。图案化导电后侧焊盘68随后是诸如用于形成C4连接38的C4工艺之类的焊球工艺,可用于完成至金属1的TSV接触。可使用其它TSV形成工艺,包括从晶片的前侧形成TSV的工艺。在实施例中,TSV填充材料仅限于不与金刚石化学相互作用的材料。在另一个实施例中,可由,例如,氮化物或二氧化硅在金刚石侧壁上形成TSV垫。垫可使导体与金刚石和/或与衬底电绝缘。可将未掺杂的金刚石形成为绝缘层,然而,该未掺杂的金刚石与宽范围的TSV填充材料和金属兼容。在其它实施例中,导体可物理接触导电地掺杂的金刚石层,以提供具有改进的热传导的衬底接触。
得到类似于图4的结构的过程可包括形成绝缘金刚石“指销”54,该绝缘金刚石“指销”54穿过硅层16延伸以环绕其中形成TSV 36的硅层16的中心硅部分70。尽管图4的横截面描绘两个垂直指销54,在中心半导体区70的任一侧上有一个,但垂直金刚石结构可形成完全围绕其中延伸TSV 36的中心硅区70的周围的一个连续区域。因为在此实施例中,金刚石是绝缘体,所以中心硅部分70与硅层16中形成的其它导电或半导电结构电隔离。因此不需要附加隔离来使金属TSV 36与硅层16电隔离,因为通过使用围绕TSV 36的金刚石填充沟槽隔离54来提供TSV金属填充与半导体层的隔离。
图5描绘多个层叠的半导体组件,诸如半导体晶片、半导体晶片衬底组件或例如半导体管芯的半导体晶片部分。可利用基于金刚石的衬底、金刚石沟槽填充和热传导焊盘在电和热上通过引线连接层叠芯片或3D IC。图5示出用于层叠三个IC的本教示的一个实施例。具有一个或多个TSV的接合焊盘可用于I/O传送,而热传导焊盘可用于热传送。
图5的层叠半导体组件100可包括第一层叠半导体管芯102、第二层叠半导体管芯104和第三层叠半导体管芯106。层叠组件可包括利用类似方法形成的先前实施例的各种结构。图5还描绘可用于将每个半导体管芯102-106以机械方式附连在一起的电介质108。
C4连接40可提供导热连接以使热传导而离开层叠组件100。例如,可利用C4连接38、40的焊料回流将C4连接40附连至接收衬底107上的焊盘105。在实施例中,C4连接38、40适用于提供离开金刚石层22的热传导。可由置于芯片102和芯片104之间的C4连接32和38以及TSV 36提供从芯片102至芯片104的导热路径。可由置于芯片104和芯片106之间的C4连接32和38以及TSV 36提供从芯片104至芯片106的导热路径。金属化层42可提供芯片之间信号的电传送和热量的热传送。可在金刚石层22的边缘处横向地形成其它热连接,例如,与诸如散热片之类的散热器109相连接,从而热通过金刚石层22水平地消散,并且通过C4连接38、40消散。
因此,层叠IC组件可形成为封装件或模块100。C4连接38、40可附连至接收衬底107上的焊盘105。由IC产生的热可有效地离开一个或多个半导体层传导到接收衬底107和/或散热器109,在散热器109中热可消散,从而降低由于过度热水平导致的不利效果。
图6描绘可根据本教示的另一个实施例形成和提供的器件110。该实施例可包括诸如半导体晶片或晶片部分的半导体层112。金刚石层114可形成在半导体层112的后部,或者可将预制金刚石层附连至半导体晶片。可将金刚石沟槽填充工艺用于形成穿过半导体层112中的开口的金刚石沟槽填充。为了形成金刚石沟槽填充116,可从半导体层112的前(电路)侧118向半导体层112内蚀刻开口,以便从半导体层一侧暴露后侧金刚石层114,然后金刚石层114可用作生长穿过开口的金刚石沟槽填充116的晶核。例如,利用CMP的平坦化步骤可用于使穿过开口延伸而超过半导体层112的前表面118的任何金刚石沟槽填充部分平坦化。
图6还描绘形成焊盘120的金属层1、可形成开口122和焊盘124的金属层2和可形成通孔126和焊盘128的金属层3。
接下来,可通过从金刚石层114的暴露侧132各向异性蚀刻穿过金刚石层114和金刚石沟槽填充116来形成穿过金刚石的通孔(TDV)130,以形成一个或多个TDV开口。蚀刻继续穿过金刚石层114和金刚石沟槽填充116以暴露金属1焊盘120的后侧。可利用,例如,钨填充工艺或化学气相沉积(CVD)工艺形成金属层,以便用导体填充TDV开口。
接下来,可利用焊盘金属化工艺来形成诸如接合焊盘之类的焊盘134、诸如C4球之类的焊料球136、球栅阵列(BGA)结构,或者可在焊盘134上形成其它导体。可形成保护性钝化层138以完成图6的结构。
图6的结构可用于提供穿过金刚石层114和金刚石填充116的I/O传送。在这个实施例中,TDV结构130不穿过半导体衬底112。因为两个金刚石结构114、116可以是电绝缘体,所以不需要用将TDV与半导体衬底电隔离的电介质覆盖开口,并且不需要其它隔离技术。导电通孔130通过金刚石层与半导体层电隔离。如图6所示,金刚石层116和导电通孔130的一部分直接置于半导体层112的各部分之间。
图6的结构组合了穿过金刚石层114、116的热传导和信号传导(I/O传送),提供有价值的管芯面积节省。该结构可具有各种优点。例如,该结构可与很多或所有的金属系统一起使用。此外,它可利用C4工艺、插入件以及铜-铜(Cu-Cu)晶片和/或管芯接合等提供管芯-管芯附连。另外,该结构可包括使用穿过硅和/或穿过衬底的通孔技术以及一个或多个金刚石填充沟槽。在本发明的实施例中不需要常规的穿过硅的通孔所需的各种电隔离工艺和结构,例如,因为TDV不穿过硅。
一些半导体组件可包括含有用于热传导和/或电隔离的金刚石层的一个或多个半导体管芯以及不含有金刚石层的一个或多个半导体管芯。其它实施例可包括具有至少两个开口——一个填充有导体而另一个填充有金刚石层——的半导体层。例如,通过使用P型掺杂剂或N型掺杂剂(取决于器件是PMOS还是NMOS),金刚石层可以是电导体,或者可以是电绝缘体。
在另一个实施例中,可导电地掺杂金刚石层以提供电传导以及热传导。
在图7-13中描绘了包括穿过诸如半导体晶片的半导体层的金刚石层的半导体组件的形成方法。图7描绘了半导体层200和覆盖半导体层200的一侧——例如后侧——的金刚石层202。可与半导体层分离地形成金刚石层202,并利用氧化物层将其附连至半导体层的后侧。在其它工艺中,可在半导体层的后侧生长或沉积金刚石层。
在提供金刚石层和半导体层之后,在半导体层200的一侧——例如前侧——上形成诸如光刻胶层之类的图案化掩模204,以具有暴露半导体层200的前侧的开口206。
接下来,例如通过蚀刻,去除半导体层200的第一部分,以在半导体层200中形成一个或多个开口,以从半导体层的前侧暴露金刚石层202,如图8所示。半导体层200中的一个或多个开口从半导体层的前侧延伸到后侧。
随后,暴露的金刚石层202可用作晶核,以穿过半导体层中蚀刻的开口生长金刚石层部分208。当生长的金刚石层部分208与半导体层200的前部齐平时可停止生长过程,或者如图9所示,生长过程可继续直到生长的金刚石层部分208延伸过开口。生长的金刚石层208延伸过开口。
如图9所示,可在半导体层200的前部和生长的金刚石层208上形成旋涂或沉积的填充层210,然后可利用,例如CMP,来使填充层和生长的金刚石层208平坦化,从而得到图10的结构。填充层可在CMP期间保护半导体层。
接下来,如图11所示,可在半导体层200和生长的金刚石层208上形成图案化掩模220。掩模中具有开口,以限定穿过生长的金刚石层208和半导体层200的TSV。蚀刻图11的结构以形成穿过生长的金刚石层208的第一开口、穿过半导体层200的第二开口,并且蚀刻穿过半导体层的后侧上的金刚石层202以得到图12的结构。随后,去除掩模220以得到图13的结构。通过用诸如金属之类的导体填充图13中的开口,可形成先前附图中的类似于TSV 36的TSV 130。可用诸如氧化物之类的电介质覆盖开口,以提供与半导体层200、后侧金刚石层202和生长的金刚石层208电绝缘的TSV。在可选实施例中,可利用第一掩模穿过生长的金刚石层208形成TSV,并且可在不同时间利用第二掩模穿过半导体层200形成TSV。
在一个实施例中,一种半导体组件包括:半导体层,该半导体层包括前侧、后侧以及穿过其中从后侧延伸至所述前侧的开口;以及延伸穿过开口并且包括在半导体层的前侧的第一表面和在半导体层的后侧的第二表面的金刚石层。在该实施例中,金刚石层可提供电连接器或者金刚石层提供不导电散热片。在该实施例中,金刚石层可包括延伸穿过开口的第一部分以及覆盖半导体层的后侧的第二部分。在该实施例中,至少一部分导电通孔直接置于半导体层的各部分之间并且至少一部分金刚石层直接置于半导体层的各部分之间。在该实施例中,延伸穿过开口的金刚石层是导电的。在该实施例中,延伸穿过开口的金刚石层是电绝缘体。在该实施例中,该开口是第一开口,且半导体组件还包括:半导体层还包括穿过其中从后侧延伸到前侧的第二开口;以及填充半导体层中的第二开口的导电层。在该实施例中,金刚石层是导电金刚石层。在该实施例中,还包括金刚石层内浓度足以得到导电金刚石层的p型掺杂剂。在该实施例中,金刚石层是电绝缘体。
在另一个实施例中,一种半导体组件,包括:半导体层,该半导体层具有前侧、后侧以及穿过其中从后侧延伸至前侧的开口;延伸穿过开口并且包括在半导体层的前侧的第一表面和在半导体层的后侧的第二表面的金刚石层的第一部分;覆盖半导体层的后侧的金刚石层的第二部分;延伸穿过金刚石层的第一部分和金刚石层的第二部分的开口;以及填充延伸穿过金刚石层的第一部分和金刚石层的第二部分的开口的导体,以提供在半导体层的前侧和半导体层的后侧之间延伸的导电路径。在该实施例中,填充开口的导体可提供在金刚石层的第一部分的前表面和金刚石层的第二部分的后表面之间延伸的导电路径。在该实施例中,金刚石层的第一部分是电绝缘体并且填充开口的导体通过金刚石层的第一部分与所述半导体层电隔离。
在又一个实施例中,一种用于形成半导体组件的方法包括:去除半导体层的第一部分以穿过其中形成从半导体层的前侧延伸至半导体层的后侧的第一开口;形成延伸穿过第一开口并且包括在半导体层的前侧的第一表面和在半导体层的后侧的第二表面的金刚石层;去除半导体层的第二部分以穿过其中形成从半导体层的前侧延伸至半导体层的后侧的第二开口;以及形成延伸穿过第二开口并且包括在半导体层的前侧的第一表面和在半导体层的后侧的第二表面的导电层。在该实施例中,较佳的是还包括使半导体层前侧的金刚石层的第一表面平坦化以形成与半导体层的前侧共面的平坦化金刚石表面。在该实施例中,较佳的是,半导体层是第一半导体层,平坦化金刚石表面是第一平坦化金刚石表面,且该方法还包括:利用导热连接使第一平坦化金刚石表面与穿过第二半导体层的开口形成的第二平坦化金刚石表面相连接,其中在半导体组件的运行期间,导热连接适用于使热传导而离开所述第一和第二半导体层。在该实施例中,较佳的是,还包括:穿过金刚石层蚀刻至少一个开口;在穿过金刚石层的至少一个开口内形成导电通孔,其中在半导体组件的运行期间,金刚石层将导电通孔与半导体层电隔离。在该实施例中,较佳的是,还包括:在至少一个开口内形成导电通孔将导电通孔直接置于半导体层的第一和第二部分之间。
将意识到,附图可能省略诸如电互连层和半导体器件扩散、导体和电介质等多种元件,以便更清楚地示出热传导焊盘和热管理的特征。此外,图2-6描绘芯片-芯片连接的C4方法。如果对于热传导焊盘,在连接中可维持足够的热传导率,则可使用芯片-芯片连接的其它示例,例如利用插入件。
尽管陈述本发明的宽泛范围的数值范围和参数是近似值,但仍然尽可能精确地报告在特定示例中陈述的数值。
然而,任何数值固有地包含必然来自它们相应的试验测量中存在的标准偏差的某些误差。而且,应当将本文中公开的所有范围理解为包含其中所包含的任何和所有的子范围。例如,“小于10”的范围可包括在最小值0和最大值10之间(含0和10)的任何和所有子范围,即具有等于或大于0的最小值和等于或小于10的最大值的任何和所有子范围,例如1到5。在某些情况下,该参数所述的数值可取负值。在这种情况下,陈述为“小于10”的范围的示例值可以采用负值,例如,-1、-2、-3、-10、-20、-30等。
虽然已经关于一个或多个实现示出了本发明,但可对所示示例作出变化和/或修改,而不背离所附权利要求的精神和范围。此外,虽然已经关于若干实现中的仅一个实现公开本发明的具体特征,但在需要和对任何给定或具体功能有利时,可将这样的特征与另一实现的一个或多个其它特征组合。此外,在术语“包括”、“包含”、“具有”、“有”、“用”或它们的变化用于详细描述和权利要求的范围内时,这些术语旨在以与术语“包括”相似的方式包括。术语“至少一个”用于表示可选择所列出项目中的一个或多个。此外,在本文的讨论和权利要求中,针对两种材料所使用的术语“在...上”,一个在另一个“上”,表示材料之间的至少某些接触,而“在...上方”表示材料接近,但可能有一个或多个附加的介入材料,使得接触是可能的但不是必需的。如本文中所使用的,“在...上”或“在...上方”都不表示任何方向性。术语“共形”描述涂层材料,其中下层材料的角受到共形材料的保护。术语“约”指示所列出的值可有某种改变,只要改变不会导致所示实施例的过程或结构的不一致即可。最后,“示例性”指示该描述用作示例,而不表示它是理想的。通过考虑说明书和实施本文所公开的发明,本发明的其它实施例对于本领域技术人员将变得显而易见。旨在认为说明书和示例仅仅是示例性的,而本发明的真实范围和精神由所附权利要求指明。
基于与晶片或衬底的常规平面或工作面平行的平面来限定本申请中使用的相对位置的术语,而与晶片或衬底的定向无关。本申请中使用的术语“水平”或“横向”定义为与晶片或衬底的常规平面或工作面平行的平面,而与晶片或衬底的定向无关。术语“垂直”指的是垂直于水平的方向。诸如“在...上”、“侧”(如在“侧壁”中)、“上”、“下”、“在...之上”、“顶部”和“在...下”之类的术语是相对于晶片或衬底的顶面上的常规平面或工作面来限定的,而与晶片或衬底的定向无关。
Claims (10)
1.一种半导体组件,包括:
半导体层,所述半导体层包括前侧、后侧以及穿过其中从所述后侧延伸至所述前侧的开口;以及
延伸穿过所述开口并且包括在所述半导体层的所述前侧的第一表面和在所述半导体层的所述后侧的第二表面的金刚石层。
2.如权利要求1所述的半导体组件,其特征在于,所述半导体层是第一半导体层,且所述半导体组件还包括:
附连至所述第一半导体层的前侧的第二半导体层,其中所述第二半导体层包括:
后侧、前侧和从所述第二半导体层的后侧延伸到所述第二半导体层的前侧的开口;
延伸穿过所述第二半导体层中的开口并且包括在所述第二半导体层的前侧的第一暴露表面和在所述第二半导体层的后侧的第二表面的金刚石层;以及
至所述金刚石层的导热连接,其中所述导热连接适用于在所述半导体组件的运行期间使热传导而离开所述第一和第二半导体层。
3.如权利要求1所述的半导体组件,其特征在于,还包括:
所述金刚石层是电绝缘体;以及
在所述金刚石层内且接触所述金刚石层的导电通孔,其中所述导电通孔通过所述金刚石层与所述半导体层电隔离。
4.如权利要求1所述的半导体组件,其特征在于,还包括:
所述金刚石层是电导体且其中包括开口;以及
在所述金刚石层的开口内且接触所述金刚石层的导电通孔,其中所述导电通孔通过所述金刚石层电连接到所述半导体层。
5.如权利要求1所述的半导体组件,其特征在于,还包括:
所述金刚石层是电导体且其中包括开口;以及
覆盖所述金刚石层中的开口的电介质垫;以及
所述金刚石层的开口内的导电通孔,其中所述电介质垫使所述导电通孔与所述金刚石层电隔离。
6.如权利要求1所述的半导体组件,其特征在于,还包括:
所述金刚石层是电绝缘体;
附连至所述金刚石层的导电层,其中所述导电层适用于将热传导到或离开所述金刚石层,并且不适用于在所述半导体组件的运行期间传导电信号。
7.一种半导体组件,包括:
半导体层,所述半导体层具有前侧、后侧以及穿过其中从所述后侧延伸至所述前侧的开口;
延伸穿过所述开口并且包括在所述半导体层的所述前侧的第一表面和在所述半导体层的所述后侧的第二表面的金刚石层的第一部分;
覆盖所述半导体层的后侧的金刚石层的第二部分;
延伸穿过所述金刚石层的第一部分和所述金刚石层的第二部分的开口;以及
填充延伸穿过所述金刚石层的第一部分和所述金刚石层的第二部分的开口的导体,以提供在所述半导体层的前侧和所述半导体层的后侧之间延伸的导电路径。
8.一种用于形成半导体组件的方法,包括:
去除半导体层的第一部分以穿过其中形成从所述半导体层的前侧延伸至所述半导体层的后侧的第一开口;
形成延伸穿过所述第一开口并且包括在所述半导体层的所述前侧的第一表面和在所述半导体层的所述后侧的第二表面的金刚石层;
去除所述半导体层的第二部分以穿过其中形成从所述半导体层的前侧延伸至所述半导体层的后侧的第二开口;以及
形成延伸穿过所述第二开口并且包括在所述半导体层的所述前侧的第一表面和在所述半导体层的所述后侧的第二表面的导电层。
9.如权利要求8所述的方法,其特征在于,还包括:
从所述半导体层的前侧蚀刻所述半导体层以暴露在所述半导体层的后侧上形成的金刚石层;以及
利用在所述半导体层的后部上形成的金刚石层作为晶核生长延伸穿过所述第一开口的金刚石层。
10.一种用于形成半导体组件的方法,包括:
去除半导体层的厚度以在所述半导体层中形成开口并暴露所述半导体层的后侧上的第一金刚石层;
利用所述第一金刚石层作为晶核穿过所述半导体层中的开口生长第二金刚石层;
穿过第一金刚石层和第二金刚石层蚀刻至少一个开口,以提供从所述第一金刚石层的后表面延伸到所述第二金刚石层的前表面并且延伸穿过所述半导体层的至少一个通孔开口;以及
用导电层填充所述至少一个通孔开口,以提供从所述第一金刚石层的后表面延伸到所述第二金刚石层的前表面并且延伸穿过所述半导体层的至少一个通孔。
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Also Published As
Publication number | Publication date |
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US20120248627A1 (en) | 2012-10-04 |
KR20110066075A (ko) | 2011-06-16 |
US20110140126A1 (en) | 2011-06-16 |
KR101193370B1 (ko) | 2012-10-19 |
CN102593021A (zh) | 2012-07-18 |
US8232137B2 (en) | 2012-07-31 |
TW201133730A (en) | 2011-10-01 |
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