WO2023279575A1 - 半导体结构及其制备方法 - Google Patents

半导体结构及其制备方法 Download PDF

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Publication number
WO2023279575A1
WO2023279575A1 PCT/CN2021/125491 CN2021125491W WO2023279575A1 WO 2023279575 A1 WO2023279575 A1 WO 2023279575A1 CN 2021125491 W CN2021125491 W CN 2021125491W WO 2023279575 A1 WO2023279575 A1 WO 2023279575A1
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substrate
layer
dielectric layer
semiconductor structure
filling hole
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PCT/CN2021/125491
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English (en)
French (fr)
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王路广
王晓玲
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长鑫存储技术有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3736—Metallic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures

Definitions

  • the present application relates to but is not limited to a semiconductor structure and its preparation method.
  • TSV Through Silicon Via
  • conductive substances such as copper, tungsten, polysilicon, etc.
  • TSV stacks multi-layer chips together Since TSV stacks multi-layer chips together, the power consumption density increases sharply, and the higher heat generation and poor heat dissipation make the operating temperature of the chip higher, which seriously affects the reliability and stability of TSV.
  • the higher operating temperature can also easily cause the expansion of the TSV metal, causing stress and deformation of the silicon substrate and the dielectric layer, and affecting the performance of the device.
  • the application provides a semiconductor structure and a preparation method thereof.
  • the first aspect of the present application provides a method for fabricating a semiconductor structure, including: providing a substrate, the substrate including a substrate and a first dielectric layer on the substrate; forming through-silicon vias in the substrate, the The through-silicon hole penetrates the first dielectric layer and extends into the substrate, and the depth of the through-silicon hole is smaller than the thickness of the substrate; a conductive structure is formed in the through-silicon hole; A dielectric layer and a filling hole are formed in the substrate, the filling hole surrounds the conductive structure, and exposes the sidewall of the conductive structure and part of the substrate, and the sidewall of the filling hole is stepped ; forming a heat conduction structure in the filling hole.
  • the sidewall of the filling hole is prepared into a stepped shape, so that the heat conduction structure formed in the filling hole is also stepped, and the stepped heat conduction structure is conducive to the upward diffusion of heat of the conductive structure, avoiding heat accumulation.
  • the device temperature is too high, which affects the device characteristics of the active region in the semiconductor structure.
  • the conductive structure includes a metal barrier layer and a conductive layer, and before forming the conductive structure in the through silicon via, it further includes: forming a second A dielectric layer; forming a first metal layer on the surface of the second dielectric layer.
  • the forming a filling hole in the first dielectric layer and the substrate includes: etching the first dielectric layer to form a filling hole in the first dielectric layer hole; remove part of the second dielectric layer, so that the remaining upper surface of the second dielectric layer is lower than the upper surface of the substrate, so as to form a filling gap in the substrate, the filling gap and the The filled via holes together constitute the filled hole.
  • the diameter of the filling hole increases in steps from the bottom to the top.
  • the forming a heat conduction structure in the filling hole includes: filling a heat conduction metal in the filling hole as the heat conduction structure, and the heat conduction structure fills the filling hole.
  • the substrate includes a silicon substrate, and forming a heat conduction structure in the filled hole further includes: annealing the obtained heat conduction structure, and the heat conduction structure reacts with the substrate A metal silicide layer is formed.
  • the second dielectric layer includes a silicon dioxide layer; the first metal layer includes a cobalt layer, an aluminum layer, a titanium nitride layer, or a ruthenium layer; and the metal barrier layer includes a tantalum layer or Tantalum nitride layer; the thermally conductive metal includes tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt.
  • the second aspect of the present application provides a semiconductor structure, including: a base, the base includes a substrate and a first dielectric layer located on the upper surface of the substrate; a conductive structure penetrates through the first dielectric layer and extends to the In the substrate, the depth of the conductive structure is smaller than the thickness of the base; the heat conduction structure is located in the base and surrounds the conduction structure, and the side wall of the heat conduction structure is stepped.
  • the semiconductor structure further includes: a first metal layer located on the sidewall and bottom of the conductive structure; a second dielectric layer located in the substrate and covering the bottom of the first metal layer and some side walls.
  • the conductive structure includes a metal barrier layer and a conductive layer; the metal barrier layer is located between the conductive layer and the first metal layer.
  • the diameter of the heat conduction structure increases in steps from the bottom to the top.
  • the heat conducting structure includes a heat conducting metal.
  • the substrate includes a loose area, and the loose area is located in the substrate and surrounds the conductive structure.
  • the substrate includes a silicon substrate, and the semiconductor structure further includes a metal silicide layer, and the metal silicide layer is located between the heat conducting structure and the loose region.
  • the heat conduction structure in the above semiconductor structure surrounds the conductive structure, and the sidewall of the heat conduction structure is stepped, thereby effectively improving the heat dissipation performance of the conduction structure and improving the reliability and stability of the conduction structure.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure in an embodiment of the present application.
  • FIG. 2 is a schematic cross-sectional view of a semiconductor structure obtained after forming TSVs in a substrate according to an embodiment of the present application.
  • Fig. 3 is a schematic cross-sectional view of a semiconductor structure obtained after forming a second dielectric layer in a TSV according to an embodiment of the present application.
  • FIG. 4 is a schematic cross-sectional view of a semiconductor structure obtained after forming a first metal layer on the surface of a second dielectric layer according to an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional view of a semiconductor structure obtained after forming a metal barrier layer on the surface of the first metal layer according to an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained after forming a conductive layer in an embodiment of the present application.
  • FIG. 7 to 13 are schematic cross-sectional structural views of the step of forming filled vias in the first dielectric layer according to an embodiment of the present application.
  • FIG. 14 is a schematic cross-sectional view of a semiconductor structure obtained after filling gaps are formed in a substrate according to an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained after forming a heat conducting structure in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of a cross-sectional structure of a semiconductor structure obtained after forming a loose region in a substrate according to an embodiment of the present application.
  • FIG. 17 is a schematic cross-sectional structure diagram of a semiconductor structure obtained after forming a heat conducting structure in another embodiment of the present application.
  • An embodiment of the present application provides a method for preparing a semiconductor structure, as shown in Figure 1, comprising:
  • Step S10 providing a base, the base includes a substrate and a first dielectric layer on the substrate.
  • Step S20 forming a TSV in the substrate, the TSV penetrates the first dielectric layer and extends into the substrate, and the depth of the TSV is smaller than the thickness of the substrate.
  • Step S30 forming a conductive structure in the TSV.
  • Step S40 forming a filling hole in the first dielectric layer and the substrate, the filling hole surrounds the conductive structure, and exposes the sidewall of the conductive structure and part of the substrate, the filling The side walls of the holes are stepped.
  • Step S50 forming a heat conduction structure in the filling hole.
  • the sidewall of the filling hole is prepared into a stepped shape, so that the heat conduction structure formed in the filling hole is also stepped.
  • the device temperature is too high, which affects the device characteristics of the active region in the semiconductor structure.
  • the material of the substrate may be silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-germanium-on-insulator, silicon-germanium-on-insulator, or germanium-on-insulator, etc.
  • the material of a dielectric layer may be at least one of silicon dioxide, silicon oxynitride, silicon nitride and low dielectric constant (Low-k) dielectric.
  • the low dielectric constant dielectric material may be hydrogen silicate or porous silicate.
  • the first dielectric layer may be a silicon dioxide layer.
  • the upper surface of the substrate may be provided with a shallow trench isolation structure and an active region.
  • step S20 a cross-sectional view of the semiconductor structure obtained after forming TSVs 12 in the substrate 11 , wherein the TSVs 12 penetrate the first dielectric layer 111 and partially extend into the substrate 112 .
  • the TSV 12 does not penetrate the substrate 112 , so the depth of the TSV 12 is smaller than the thickness of the substrate 11 .
  • a conductive structure 15 is formed in the TSV 12 .
  • a second dielectric layer 13 is formed on the sidewall and bottom of the TSV 12.
  • the material of the second dielectric layer 13 can be silicon dioxide, silicon oxynitride, silicon nitride and low dielectric constant ( At least one of Low-k) dielectrics.
  • the low dielectric constant dielectric material may be hydrogen-containing silicate or porous silicate.
  • a silicon oxide layer may be deposited on the sidewall and bottom of the TSV 12 as the second dielectric layer 13 by chemical vapor deposition (CVD) or atomic layer deposition (ALD).
  • FIG. 4 shows a cross-sectional schematic view of the semiconductor structure obtained after forming the first metal layer 14 on the surface of the second dielectric layer 13 .
  • the first metal layer 14 may be a cobalt layer, an aluminum layer, a titanium nitride layer or a ruthenium layer.
  • a conductive structure 15 is formed in the TSV 12 , wherein the conductive structure 15 includes a metal barrier layer 151 and a conductive layer 152 , as shown in FIG. 5 .
  • the barrier metal layer 151 can be deposited on the surface of the first metal layer 14 first, and the barrier metal layer 151 can be a tantalum layer or a tantalum nitride layer. Then, on the basis of the structure shown in FIG. 5 , a conductive layer 152 is formed in the TSV 12 .
  • a copper seed layer may be deposited on the surface of the metal barrier layer 151, and then an electroplating process is used to deposit copper in the TSV 12 to fill the TSV 12, so that the copper layer is in phase with the upper surface of the first dielectric layer 111. flush.
  • a cross-sectional schematic view of the semiconductor structure obtained after forming the conductive structure 15 in the TSV 12 is shown in FIG. 6 .
  • step S40 as shown in FIG. 14, a filling hole 17 is formed in the first dielectric layer 111 and the substrate 112, the filling hole 17 surrounds the conductive structure 15, and exposes the sidewall of the conductive structure 15 and part of the substrate 112, The side walls of the filling holes 17 are stepped.
  • the step of forming the filling hole 17 in the first dielectric layer 111 and the substrate 112 includes:
  • Step S41 Etching the first dielectric layer 111 to form filled via holes 171 in the first dielectric layer 111 .
  • Step S42 removing part of the second dielectric layer 13, so that the upper surface of the remaining second dielectric layer 13 is lower than the upper surface of the substrate 112, so as to form a filling gap 172 in the substrate 112, filling the gap 172 and filling the through hole 171 Together they form the filling hole 17 .
  • the step of forming the filled via hole 171 in step S41 may refer to FIGS. 7 to 13 .
  • the filled via hole 171 shown in FIG. 13 is gradually formed by performing multiple photolithography processes on the first dielectric layer 111 .
  • a photoresist layer 16 is formed on the upper surface of the semiconductor structure shown in FIG. 6, as shown in FIG. part, as shown in FIG. 8; part of the first dielectric layer 111 is removed through an etching process, and the photoresist is removed by cleaning to obtain a semiconductor structure as shown in FIG.
  • the etching gas may include fluorine-based gases such as sulfur hexafluoride and carbon tetrafluoride; in order to form a complete stepped filled via hole 171 structure, coating photoresist, exposure, development, etching and cleaning can be performed again and other processes, as shown in Figures 10 to 12, process the semiconductor structure shown in Figure 9 to obtain the semiconductor structure shown in Figure 12; repeat the process in Figures 10 to A stepped filled via 171 is formed in the layer 111 , as shown in FIG. 13 .
  • fluorine-based gases such as sulfur hexafluoride and carbon tetrafluoride
  • part of the second dielectric layer 13 can be removed on the basis of the semiconductor structure shown in FIG. 13 , so that the upper surface of the second dielectric layer 13 is lower than the upper surface of the substrate 112. , thereby forming a filling gap 172 in the substrate 112 , as shown in FIG. 14 .
  • the filling through hole 171 and the filling gap 172 jointly constitute the filling hole 17 , and the diameter of the filling hole 17 increases in steps from the bottom to the top.
  • a heat conduction structure 18 is formed in the filling hole 17 .
  • a thermally conductive metal may be filled in the filling hole 17 as the thermally conductive structure 18 , and the thermally conductive structure 18 fills the filling hole 17 , as shown in FIG. 15 .
  • the heat conducting metal may be tungsten, silver, platinum, aluminum, nickel, ruthenium or cobalt.
  • the thermally conductive metal can be granular to facilitate heat dissipation.
  • the heat conduction structure 18 is narrow at the bottom and wide at the top, which facilitates the heat to be dissipated upwards, preventing the heat from being dissipated in time and causing damage to the TSV 12 .
  • Components around the bottom have an effect.
  • the bottom diameter of the heat conduction structure 18 is small and the top diameter is large, the occupied area of the active area can be reduced, the congestion of devices in the active area can be reduced, and the heat dissipation efficiency can be increased.
  • the substrate 112 may be a silicon substrate, and after the thermal conduction structure 18 is formed in the filling hole 17, the resulting thermal conduction structure 18 is annealed, and the thermal conduction structure 18 and the The substrate 112 reacts to form a metal silicide layer.
  • the metal silicide can effectively solve the problem of difficult heat dissipation in the TSV structure.
  • Metal silicide has good thermal conductivity. When the heat conduction metal conducts the heat on the conductive structure 15 to the substrate 112, the metal silicide will not block the heat, but can quickly conduct heat to avoid heat accumulation. Increasing the temperature of the substrate on the substrate 112 affects the working performance of the device in the active region.
  • the following steps are further included: performing ion bombardment on the exposed substrate 112 to form a porous structure in the substrate 112.
  • a region 19 , a porous region 19 surrounds the conductive structure 15 .
  • Ar ion bombardment may be performed on the substrate 112 exposed by the filling hole 17 to form the porous region 19 .
  • the radio frequency power can be controlled at 30W to 100W, such as 40W, 50W, 60W, 70W, 80W and 90W, and the flow of Ar gas that is introduced is 10sccm-150sccm, such as 30sccm, 50sccm, 80sccm, 100sccm and 120sccm,
  • the ion bombardment time can be 10 seconds-200 seconds, for example, it can be 30 seconds, 50 seconds, 80 seconds, 100 seconds, 150 seconds and 180 seconds.
  • the ion bombardment may be performed on the substrate 112 after the remaining photoresist is removed after the filling hole 17 is formed, or the ion bombardment may be performed on the substrate 112 before the residual photoresist is removed.
  • a schematic diagram of the cross-sectional structure of the semiconductor structure obtained after ion bombardment is shown in FIG. 16 . After the porous region 19 is formed, a thermally conductive metal is filled in the filling hole 17 to form a thermally conductive structure 18 , and the semiconductor structure shown in FIG. 17 is obtained.
  • the loose region 19 is formed by bombarding the substrate 112 with ions, which can further improve the heat dissipation capability of the semiconductor structure. This is because, after the heat conduction structure 18 conducts heat to the substrate 112 , the loose area 19 in the substrate 112 can speed up the dissipation of heat and avoid heat accumulation.
  • An embodiment of the present application also provides a semiconductor structure, as shown in FIG. 15 , including: a base 11, the base 11 includes a substrate 112 and a first dielectric layer 111 located on the upper surface of the substrate 112; The first dielectric layer 111 extends into the substrate 112 , the depth of the conductive structure 15 is smaller than the thickness of the base 11 ; the heat conduction structure 18 is located in the base 11 and surrounds the conduction structure 15 , and the sidewall of the heat conduction structure 18 is stepped.
  • the substrate 11 may be a silicon substrate 11, and the first dielectric layer 111 may be a silicon dioxide layer.
  • the conductive structure 15 may be located in the through-silicon via 12 (shown in FIG. 2 ) to realize vertical electrical interconnection of multi-layer chips. Due to the stacking of multi-layer chips, it is easy to cause a sharp increase in power consumption density, so that the temperature of the conductive structure 15 rises sharply, and it is easy to affect the reliability and stability of the conductive structure 15 and electronic devices. By arranging a heat conduction structure 18 with stepped sidewalls around the conductive structure 15, the speed of heat dissipating upwards can be increased, and the heat dissipation efficiency can be increased.
  • the semiconductor structure further includes a first metal layer 14 and a second dielectric layer 13 .
  • the first metal layer 14 is located on the sidewall and bottom of the conductive structure 15
  • the first metal layer 14 is attached to the sidewall and bottom of the conductive structure 15 .
  • the second dielectric layer 13 is located in the substrate 112 and covers the bottom and part of the sidewall of the first metal layer 14 .
  • the conductive structure 15 includes a metal barrier layer 151 and a conductive layer 152 , and the metal barrier layer 151 is located between the conductive layer 152 and the first metal layer 14 .
  • the barrier metal layer 151 may be a tantalum layer or a tantalum nitride layer
  • the conductive layer 152 may be a copper layer.
  • the diameter of the thermally conductive structure 18 increases in steps from the bottom to the top.
  • the heat conduction structure 18 By designing the heat conduction structure 18 so that its diameter increases stepwise from the bottom to the top, the occupied area of the active area in the substrate 112 by the heat dissipation structure can be reduced, and the crowding of the active devices can be avoided; Dissipation, by designing the heat dissipation structure to be narrow at the bottom and wide at the top, it is beneficial to accelerate the upward dissipation of heat, avoiding the accumulation of heat around the bottom of the conductive structure 15 and causing the temperature of the substrate 112 to rise, affecting the performance of electronic devices in the active region.
  • the thermally conductive structure 18 includes a thermally conductive metal, such as tungsten, silver, platinum, aluminum, nickel, ruthenium, or cobalt.
  • the thermally conductive metal may be filled in the filling hole 17 in the form of particles.
  • the substrate 112 includes a porous region 19 .
  • the loose region 19 is located in the substrate 112 and surrounds the conductive structure 15 .
  • the heat derived from the heat conduction structure 18 can be further dissipated, and the temperature of the substrate 112 can be avoided after the heat is accumulated in the substrate 112 , thereby affecting the working performance of active devices.
  • the substrate 112 includes a silicon substrate, and the semiconductor structure further includes a metal silicide layer (not shown in the figure), and the metal silicide layer is located between the thermally conductive structure 18 and the porous region 19 between.
  • metal silicide Similar to heat-conducting metals, metal silicide also has high thermal conductivity, and can accelerate the conduction and dissipation of heat generated by the conductive structure 15 together with the heat-conducting structure 18 to reduce heat accumulation.
  • the heat conduction structure formed in the filled hole is also stepped, and the stepped heat conduction structure is conducive to the formation of the conductive structure.
  • the heat is diffused upwards to avoid heat accumulation causing excessive temperature of the device and affecting the device characteristics of the active region in the semiconductor structure.

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Abstract

本申请提供一种半导体结构及其制备方法，其中，半导体结构的制备方法，包括：提供基底，基底包括衬底及位于衬底上的第一介质层；于基底内形成硅通孔，硅通孔贯穿第一介质层并延伸至衬底内，且硅通孔的深度小于基底的厚度；于硅通孔内形成导电结构；于第一介质层和衬底内形成填充孔，填充孔环绕导电结构，且暴露出导电结构的侧壁及部分衬底，填充孔的侧壁呈台阶状；于填充孔内形成导热结构。上述半导体结构的制备方法，通过将填充孔的侧壁制备为台阶状，使得填充孔内形成的导热结构也呈台阶状，有利于导电结构的热量向上扩散，提高了硅通孔结构的散热能力，从而得到可靠性和稳定性更好的硅通孔结构的。

Description

半导体结构及其制备方法
本申请要求在2021年07月05日提交中国专利局、申请号为202110758551.4、发明名称为“半导体结构及其制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及但不限于一种半导体结构及其制备方法。
背景技术
硅通孔技术(Through Silicon Via，TSV)是一项高密度封装技术，通过铜、钨、多晶硅等导电物质的填充，实现硅通孔的垂直电气互连。
由于TSV将多层芯片堆叠在一起，导致功耗密度急剧上升，较高的发热量和较差的散热性使得芯片的工作温度较高，严重影响了TSV的可靠性和稳定性。较高的工作温度还容易造成TSV金属的膨胀，使得硅基材和介电层发生应力形变，影响元件性能。
发明内容
以下是对本申请详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本申请提供一种半导体结构及其制备方法。
本申请的第一方面提供一种半导体结构的制备方法，包括：提供基底，所述基底包括衬底及位于所述衬底上的第一介质层；于所述基底内形成硅通孔，所述硅通孔贯穿所述第一介质层并延伸至所述衬底内，且所述硅通孔的深度小于所述基底的厚度；于所述硅通孔内形成导电结构；于所述第一介质层和所述衬底内形成填充孔，所述填充孔环绕所述导电结构，且暴露出所述导电结构的侧壁及部分所述衬底，所述填充孔的侧壁呈台阶状；于所述填充孔内形成导热结构。
上述半导体结构的制备方法，通过将填充孔的侧壁制备为台阶状， 使得填充孔内形成的导热结构也呈台阶状，台阶状的导热结构有利于导电结构的热量向上扩散，避免热量聚集造成器件温度过高，影响半导体结构中有源区的元件特性。通过提高硅通孔结构的散热能力，可以提高硅通孔结构的可靠性和稳定性。
根据本申请的一些实施例，所述导电结构包括金属阻挡层和导电层，所述于所述硅通孔内形成导电结构之前还包括：于所述硅通孔的侧壁及底部形成第二介质层；于所述第二介质层表面形成第一金属层。
根据本申请的一些实施例，所述于所述第一介质层和所述衬底内形成填充孔，包括：刻蚀所述第一介质层，以于所述第一介质层内形成填充通孔；去除部分所述第二介质层，使得保留的所述第二介质层的上表面低于所述衬底的上表面，以于所述衬底内形成填充间隙，所述填充间隙与所述填充通孔共同构成所述填充孔。
根据本申请的一些实施例，所述填充孔的直径自底部至顶部呈阶梯型增大。
根据本申请的一些实施例，所述于所述填充孔内形成导热结构，包括：于所述填充孔内填充导热金属作为所述导热结构，所述导热结构填满所述填充孔。
根据本申请的一些实施例，所述衬底包括硅衬底，所述于所述填充孔内形成导热结构，还包括：将所得导热结构进行退火处理，所述导热结构与所述衬底反应形成金属硅化物层。
根据本申请的一些实施例，所述第二介质层包括二氧化硅层；所述第一金属层包括钴层、铝层、氮化钛层或钌层；所述金属阻挡层包括钽层或氮化钽层；所述导热金属包括钨、银、铂、铝、镍、钌或钴。
根据本申请的一些实施例，于所述第一介质层内形成填充孔之后，且于所述填充孔内形成导热结构之前，还包括：对暴露出的所述衬底进行离子轰击，以于所述衬底内形成疏松区域，所述疏松区域环绕所述导电结构。
本申请的第二方面提供一种半导体结构，包括：基底，所述基底包括衬底及位于所述衬底上表面的第一介质层；导电结构，贯穿所述第一介质层并延伸至所述衬底内，所述导电结构的深度小于所述基底的厚 度；导热结构，位于所述基底内，且环绕所述导电结构，所述导热结构的侧壁呈台阶状。
根据本申请的一些实施例，半导体结构还包括：第一金属层，位于所述导电结构的侧壁和底部；第二介质层，位于所述衬底内，覆盖所述第一金属层的底部及部分侧壁。
根据本申请的一些实施例，所述导电结构包括金属阻挡层和导电层；所述金属阻挡层位于所述导电层与所述第一金属层之间。
根据本申请的一些实施例，所述导热结构的直径自底部至顶部呈阶梯型增大。
根据本申请的一些实施例，所述导热结构包括导热金属。
根据本申请的一些实施例，所述衬底包括疏松区域，所述疏松区域位于所述衬底内，且环绕所述导电结构。
根据本申请的一些实施例，所述衬底包括硅衬底，所述半导体结构还包括金属硅化物层，所述金属硅化物层位于所述导热结构与所述疏松区域之间。
上述半导体结构中的导热结构环绕于导电结构周围，且导热结构的侧壁呈台阶状，从而有效改善了导电结构的散热性能，提高了导电结构的可靠性和稳定性。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
并入到说明书中并且构成说明书的一部分的附图示出了本申请的实施例，并且与描述一起用于解释本申请实施例的原理。在这些附图中，类似的附图标记用于表示类似的要素。下面描述中的附图是本申请的一些实施例，而不是全部实施例。对于本领域技术人员来讲，在不付出创造性劳动的前提下，可以根据这些附图获得其他的附图。
图1为本申请一实施例中一种半导体结构的制备方法流程图。
图2为本申请一实施例中于基底内形成硅通孔后得到的半导体结构的截面结构示意图。
图3为本申请一实施例中于硅通孔内形成第二介质层后得到的半导体 结构的截面结构示意图。
图4为本申请一实施例中于第二介质层表面形成第一金属层后得到的半导体结构的截面结构示意图。
图5为本申请一实施例中于第一金属层表面形成金属阻挡层后得到的半导体结构的截面结构示意图。
图6为本申请一实施例中形成导电层后得到的半导体结构的截面结构示意图。
图7至图13为本申请一实施例中于第一介质层内形成填充通孔步骤的截面结构示意图。
图14为本申请一实施例中于衬底内形成填充间隙后得到的半导体结构的截面结构示意图。
图15为本申请一实施例中形成导热结构后得到的半导体结构的截面结构示意图。
图16为本申请一实施例中于衬底内形成疏松区域后得到的半导体结构的截面结构示意图。
图17为本申请另一实施例中形成导热结构后得到的半导体结构的截面结构示意图。
附图标号说明：11、基底；111、第一介质层；112、衬底；12、硅通孔；13、第二介质层；14、第一金属层；15、导电结构；151、金属阻挡层；152、导电层；16、光刻胶层；17、填充孔；171、填充通孔；172、填充间隙；18、导热结构；19、疏松区域。
具体实施方式
下面将结合本申请实施例中的附图，对申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。需要说明的是，在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互任意组合。
本申请的一个实施例提供了一种半导体结构的制备方法，如图1所示， 包括：
步骤S10：提供基底，所述基底包括衬底及位于所述衬底上的第一介质层.
步骤S20：于所述基底内形成硅通孔，所述硅通孔贯穿所述第一介质层并延伸至所述衬底内，且所述硅通孔的深度小于所述基底的厚度。
步骤S30：于所述硅通孔内形成导电结构。
步骤S40：于所述第一介质层和所述衬底内形成填充孔，所述填充孔环绕所述导电结构，且暴露出所述导电结构的侧壁及部分所述衬底，所述填充孔的侧壁呈台阶状。
步骤S50：于所述填充孔内形成导热结构。
上述半导体结构的制备方法，通过将填充孔的侧壁制备为台阶状，使得填充孔内形成的导热结构也呈台阶状，台阶状的导热结构有利于导电结构的热量向上扩散，避免热量聚集造成器件温度过高，影响半导体结构中有源区的元件特性。通过提高硅通孔结构的散热能力，可以提高硅通孔结构的可靠性和稳定性。
其中，在步骤S10中，衬底的材料可以为硅、碳化硅、氮化硅、绝缘体上硅、绝缘体上层叠硅、绝缘体上层叠锗化硅、绝缘体上层锗化硅或绝缘体上层锗等，第一介质层的材料可以为二氧化硅、氮氧化硅、氮化硅和低介电常数(Low-k)介电质中的至少一种。其中，低介电常数介电质材料可以是含氢硅酸盐或多孔性硅酸盐。在本申请实施例中，第一介质层可以为二氧化硅层。衬底上表面可以设置有浅沟道隔离结构和有源区。
在步骤S20中，参照图2所示，于基底11内形成硅通孔12后得到的半导体结构截面图，其中，硅通孔12贯穿第一介质层111并部分延伸至衬底112内。硅通孔12未穿透衬底112，故硅通孔12的深度小于基底11的厚度。
在示例性实施方式中，于基底11内形成硅通孔12之后，参照图3至图5所示，可以先在硅通孔12内形成第二介质层13和第一金属层14，然后再于硅通孔12内形成导电结构15。
如图3所示，于硅通孔12的侧壁及底部形成第二介质层13，第二介质层13的材料可以为二氧化硅层、氮氧化硅、氮化硅和低介电常数(Low-k)介电质中的至少一种。其中，低介电常数介电质材料可以是含氢硅酸盐或多 孔性硅酸盐。在示例性实施方式中，可以采用化学气相沉积工艺(CVD)或原子层沉积工艺(ALD)在硅通孔12的侧壁及底部沉积氧化硅层作为第二介质层13。图4展示了于第二介质层13表面形成第一金属层14后得到的半导体结构的截面结构示意图。其中，第一金属层14可以是钴层、铝层、氮化钛层或钌层。
在步骤S30中，参照图6所示，于硅通孔12内形成导电结构15，其中，导电结构15包括金属阻挡层151和导电层152，如图5所示。例如，可以先在第一金属层14的表面沉积金属阻挡层151，金属阻挡层151可以是钽层或氮化钽层。然后，在图5所示结构的基础上，于硅通孔12内形成导电层152。例如，可以在金属阻挡层151的表面沉积铜籽晶层，然后使用电镀工艺，于硅通孔12内沉积铜，填满硅通孔12，使得铜层与第一介质层111的上表面相平齐。于硅通孔12内形成导电结构15后得到的半导体结构的截面结构示意图如图6所示。
在步骤S40中，参照图14所示，于第一介质层111和衬底112内形成填充孔17，填充孔17环绕导电结构15，且暴露出导电结构15的侧壁及部分衬底112，填充孔17的侧壁呈台阶状。
在示例性实施方式中，参照图14所示，于第一介质层111和衬底112内形成填充孔17的步骤包括：
步骤S41：刻蚀第一介质层111，以于第一介质层111内形成填充通孔171。
步骤S42：去除部分第二介质层13，使得保留的第二介质层13的上表面低于衬底112的上表面，以于衬底112内形成填充间隙172，填充间隙172与填充通孔171共同构成填充孔17。
在示例性实施方式中，步骤S41中形成填充通孔171的步骤可以参考图7至图13。通过对第一介质层111进行多次光刻工艺，逐步形成如图13所示的填充通孔171。例如，首先在图6所示半导体结构的上表面形成光刻胶层16，如图7所示；然后，经过曝光和显影，露出第一介质层111的部分上表面，即需要刻蚀去除的部分，如图8所示；经过刻蚀工艺去除部分第一介质层111，清洗去除光刻胶，得到如图9所示的半导体结构，，可以采用干法刻蚀去除部分第一介质层111，刻蚀气体可以包括六氟化硫和四氟化碳等氟基气体；为了形成完整的台阶状的填充通孔171结构，可以再次进行涂覆光刻胶、 曝光、显影、刻蚀以及清洗等工艺，如图10至图12所示，对图9所示的半导体结构进行加工，以得到图12所示的半导体结构；重复进行图10-图12中的工艺，即可在第一介质层111内形成台阶状的填充通孔171，如图13所示。
为了进一步提高硅通孔12结构的散热能力，可以在图13所示半导体结构的基础上，去除部分第二介质层13，以使得第二介质层13的上表面低于衬底112的上表面，从而在衬底112内形成填充间隙172，如图14所示。填充通孔171和填充间隙172共同构成填充孔17，填充孔17的直径自底部至顶部呈阶梯型增大。
在步骤S50中，参照图14至图15所示，于填充孔17内形成导热结构18。在示例性实施方式中，可以在填充孔17内填充导热金属作为导热结构18，导热结构18填满填充孔17，如图15所示。其中，导热金属可以是钨、银、铂、铝、镍、钌或钴。例如，导热金属可以是颗粒状，以利于热量散发。通过在硅通孔12(参照图2所示)结构周围形成阶梯状的导热结构18，且导热结构18下窄上宽，有利于热量向上散发，避免热量无法及时散去而对硅通孔12底部周围的元器件造成影响。同时，由于导热结构18的底部直径较小，顶部直径较大，可以减小占用有源区的面积，减缓有源区器件的拥挤程度，增大散热效率。
在示例性实施方式中，参照图图14至图15所示，衬底112可以是硅衬底，在填充孔17内形成导热结构18后，对所得导热结构18进行退火处理，导热结构18与衬底112反应形成金属硅化物层。金属硅化物能够有效解决TSV结构散热困难的问题。金属硅化物具有良好的导热性能，当导热金属将导电结构15上的热量传导至衬底112时，金属硅化物不会对热量形成阻拦作用，而是可以快速地对热量进行传导，避免热量聚集于衬底112上而提高基底温度，影响有源区器件的工作性能。
在示例性实施方式中，参照图16至图17所示，于填充孔17内形成导热结构18之前还包括如下步骤：对暴露出的衬底112进行离子轰击，以于衬底112内形成疏松区域19，疏松区域19环绕导电结构15。作为示例，可以对填充孔17暴露出的衬底112进行Ar离子轰击，以形成疏松区域19。例如，射频功率可以控制在30W至100W，例如可以为40W、50W、60W、70W、 80W和90W，通入的Ar气流量为10sccm-150sccm，例如可以为30sccm、50sccm、80sccm、100sccm和120sccm，离子轰击时间可以为10秒-200秒，例如可以为30秒、50秒、80秒、100秒、150秒和180秒。在示例性实施方式中，可以在形成填充孔17后，将残留的光刻胶去除之后再对衬底112进行离子轰击，也可以在去除残留的光刻胶之前对衬底112进行离子轰击。经过离子轰击后得到的半导体结构截面结构示意图如图16所示。形成疏松区域19之后，于填充孔17内填充导热金属，形成导热结构18，得到图17所示的半导体结构。
通过离子轰击衬底112形成疏松区域19，可以进一步提高半导体结构的散热能力。这是因为，当导热结构18将热量传导至衬底112后，衬底112中的疏松区域19可以加快热量的散发，避免热量聚集。
本申请的一个实施例还提供了一种半导体结构，如图15所示，包括：基底11，基底11包括衬底112及位于衬底112上表面的第一介质层111；导电结构15，贯穿第一介质层111并延伸至衬底112内，导电结构15的深度小于基底11的厚度；导热结构18，位于基底11内，且环绕导电结构15，导热结构18的侧壁呈台阶状。
其中，基底11可以是硅基底11，第一介质层111可以是二氧化硅层。导电结构15可以位于硅通孔12(参照图2所示)中，以实现多层芯片的垂直电气互连。由于多层芯片堆叠放置，容易导致功耗密度急剧上升，使得导电结构15的温度急剧升高，容易影响导电结构15和电子器件的可靠性和稳定性。通过在导电结构15的周围设置侧壁呈阶梯状的导热结构18，可以提高热量向上散发的速度，增大散热效率。
在示例性实施方式中，参照图13所示，半导体结构还包括第一金属层14和第二介质层13。请继续参考图15，其中，第一金属层14位于导电结构15的侧壁和底部，第一金属层14贴合设置于导电结构15的侧壁和底部。请继续参照图13所示，第二介质层13位于衬底112内，覆盖第一金属层14的底部及部分侧壁。
在示例性实施例方式中，参照图14所示，导电结构15包括金属阻挡层151和导电层152，金属阻挡层151位于导电层152与第一金属层14之间。其中，金属阻挡层151可以是钽层或氮化钽层，导电层152可以是铜层。
在示例性实施方式中，如图15所示，导热结构18的直径自底部至顶部呈阶梯型增大。通过将导热结构18设计为直径自底部至顶部呈阶梯型增大，可以减少散热结构对衬底112中有源区的占用面积，避免加剧有源器件的拥挤程度；同时，由于热量一般是向上散发，通过将散热结构设计为下窄上宽，有利于加快热量向上散发，避免热量聚集于导电结构15底部周围而导致衬底112温度升高，影响有源区内电子器件的性能。
在示例性实施方式中，参照图14至图15所示，导热结构18包括导热金属，例如，导热金属可以是钨、银、铂、铝、镍、钌或钴。作为示例，导热金属可以以颗粒状填充于填充孔17内。通过将导热结构18设计为颗粒状，既可以充分利用导热金属优异的导热性能将热量及时传导出去，又可以利用颗粒间的空隙，便于热量散发。
在示例性实施方式中，参照图16至图17所示，衬底112包括疏松区域19。如图17所示，疏松区域19位于衬底112内，且环绕导电结构15。通过在衬底112中设置疏松区域19，可以将导热结构18导出的热量进一步散发，避免热量聚集于衬底112中后提高衬底112温度，进而影响有源器件的工作性能。
在示例性实施方式中，参照图17所示，衬底112包括硅衬底，半导体结构还包括金属硅化物层(图中未示出)，金属硅化物层位于导热结构18与疏松区域19之间。金属硅化物与导热金属类似，也具有高导热能力，可以与导热结构18一起加快对导电结构15产生的热量进行传导和散发，减少热量聚集。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“实施例”、“示例性的实施例”、“一些实施方式”、“示意性实施方式”、“示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或 多个实施方式或示例中以合适的方式结合。
在本申请的描述中，需要说明的是，术语“中心”、“上”、“下”、“左”、“右”、“竖直”、“水平”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
可以理解的是，本申请所使用的术语“第一”、“第二”等可在本申请中用于描述各种结构，但这些结构不受这些术语的限制。这些术语仅用于将第一个结构与另一个结构区分。
在一个或多个附图中，相同的元件采用类似的附图标记来表示。为了清楚起见，附图中的多个部分没有按比例绘制。此外，可能未示出某些公知的部分。为了简明起见，可以在一幅图中描述经过数个步骤后获得的结构。在下文中描述了本申请的许多特定的细节，例如器件的结构、材料、尺寸、处理工艺和技术，以便更清楚地理解本申请。但正如本领域技术人员能够理解的那样，可以不按照这些特定的细节来实现本申请。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。
工业实用性
本申请实施例所提供的半导体结构及其制备方法中，通过将填充孔的侧壁制备为台阶状，使得填充孔内形成的导热结构也呈台阶状，台阶状的导热结构有利于导电结构的热量向上扩散，避免热量聚集造成器件温度过高，影响半导体结构中有源区的元件特性。通过提高硅通孔结构的散热能力，可以提高硅通孔结构的可靠性和稳定性。

Claims (15)

  1. 一种半导体结构的制备方法，包括：
    提供基底，所述基底包括衬底及位于所述衬底上的第一介质层；
    于所述基底内形成硅通孔，所述硅通孔贯穿所述第一介质层并延伸至所述衬底内，且所述硅通孔的深度小于所述基底的厚度；
    于所述硅通孔内形成导电结构；
    于所述第一介质层和所述衬底内形成填充孔，所述填充孔环绕所述导电结构，且暴露出所述导电结构的侧壁及部分所述衬底，所述填充孔的侧壁呈台阶状；
    于所述填充孔内形成导热结构。
  2. 根据权利要求1所述的半导体结构的制备方法，所述导电结构包括金属阻挡层和导电层，所述于所述硅通孔内形成导电结构之前还包括：
    于所述硅通孔的侧壁及底部形成第二介质层；
    于所述第二介质层表面形成第一金属层。
  3. 根据权利要求2所述的半导体结构的制备方法，其中，所述于所述第一介质层和所述衬底内形成填充孔，包括：
    刻蚀所述第一介质层，以于所述第一介质层内形成填充通孔；
    去除部分所述第二介质层，使得保留的所述第二介质层的上表面低于所述衬底的上表面，以于所述衬底内形成填充间隙，所述填充间隙与所述填充通孔共同构成所述填充孔。
  4. 根据权利要求3所述的半导体结构的制备方法，其中，所述填充孔的直径自底部至顶部呈阶梯型增大。
  5. 根据权利要求3所述的半导体结构的制备方法，其中，所述于所述填充孔内形成导热结构，包括：
    于所述填充孔内填充导热金属作为所述导热结构，所述导热结构填满所述填充孔。
  6. 根据权利要求5所述的半导体结构的制备方法，所述衬底包括硅衬底，所述于所述填充孔内形成导热结构，还包括：
    将所得导热结构进行退火处理，所述导热结构与所述衬底反应形成金属 硅化物层。
  7. 根据权利要求5所述的半导体结构的制备方法，其中，所述第二介质层包括二氧化硅层；所述第一金属层包括钴层、铝层、氮化钛层或钌层；所述金属阻挡层包括钽层或氮化钽层；所述导热金属包括钨、银、铂、铝、镍、钌或钴。
  8. 根据权利要求1至7中任一项所述的半导体结构的制备方法，于所述第一介质层内形成填充孔之后，且于所述填充孔内形成导热结构之前，还包括：
    对暴露出的所述衬底进行离子轰击，以于所述衬底内形成疏松区域，所述疏松区域环绕所述导电结构。
  9. 一种半导体结构，包括：
    基底，所述基底包括衬底及位于所述衬底上表面的第一介质层；
    导电结构，贯穿所述第一介质层并延伸至所述衬底内，所述导电结构的深度小于所述基底的厚度；
    导热结构，位于所述基底内，且环绕所述导电结构，所述导热结构的侧壁呈台阶状。
  10. 根据权利要求9所述的半导体结构，还包括：
    第一金属层，位于所述导电结构的侧壁和底部；
    第二介质层，位于所述衬底内，覆盖所述第一金属层的底部及部分侧壁。
  11. 根据权利要求10所述的半导体结构，其中，所述导电结构包括金属阻挡层和导电层；所述金属阻挡层位于所述导电层与所述第一金属层之间。
  12. 根据权利要求9所述的半导体结构，其中，所述导热结构的直径自底部至顶部呈阶梯型增大。
  13. 根据权利要求9所述的半导体结构，其中，所述导热结构包括导热金属。
  14. 根据权利要求9所述的半导体结构，其中，所述衬底包括疏松区域，所述疏松区域位于所述衬底内，且环绕所述导电结构。
  15. 根据权利要求14所述的半导体结构，其中，所述衬底包括硅衬 底，所述半导体结构还包括金属硅化物层，所述金属硅化物层位于所述导热结构与所述疏松区域之间。
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