WO2022241962A1 - 芯片、存储器及芯片的制备方法 - Google Patents

芯片、存储器及芯片的制备方法 Download PDF

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Publication number
WO2022241962A1
WO2022241962A1 PCT/CN2021/113127 CN2021113127W WO2022241962A1 WO 2022241962 A1 WO2022241962 A1 WO 2022241962A1 CN 2021113127 W CN2021113127 W CN 2021113127W WO 2022241962 A1 WO2022241962 A1 WO 2022241962A1
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Prior art keywords
conductive structure
layer
dielectric layer
substrate
chip
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PCT/CN2021/113127
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English (en)
French (fr)
Inventor
刘志拯
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长鑫存储技术有限公司
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Priority to US17/647,883 priority Critical patent/US20220375824A1/en
Publication of WO2022241962A1 publication Critical patent/WO2022241962A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a chip, a memory and a method for preparing the chip.
  • Stacked chip packaging technology also known as three-dimensional packaging technology, refers to the packaging technology of stacking two or more chips in the vertical direction in the same package.
  • DRAM Dynamic Random Access Memory
  • multiple chips are vertically stacked and connected to each other through three-dimensional packaging technology to increase the storage capacity of DRAM.
  • each chip usually includes a substrate and an interconnection structure layer arranged on the substrate, wherein, through silicon via technology (Through Silicon Via, TSV for short) is used to make corresponding through holes on each chip.
  • TSV Through Silicon Via
  • Fill the conductive material, such as copper, to form a TSV structure one end of the TSV structure is connected to the interconnection structure layer, and the other end of the TSV structure is used to connect with the chip adjacent to the chip, so as to realize conduction between adjacent chips.
  • the first aspect of the embodiments of the present application provides a chip, which includes:
  • an interconnect structure layer is disposed on the substrate;
  • the conductive structure includes a first conductive structure and a second conductive structure connected to the first conductive structure, the first conductive structure is connected to the interconnect structure layer, the The coefficient of thermal expansion of the first conductive structure is smaller than that of copper.
  • the second aspect of the embodiment of the present application provides a memory, which includes a plurality of chips as described above, and the plurality of chips are stacked in sequence, and two adjacent layers of chips are connected through the interconnection structure layer.
  • a third aspect of the embodiments of the present application provides a method for preparing a chip, including the following steps:
  • a substrate is provided, an intermetal dielectric layer is disposed on the substrate, and an etching stop layer is disposed in the intermetal dielectric layer;
  • first conductive structure in the intermetal dielectric layer, the bottom of the first conductive structure is in contact with the etch stop layer, the thermal expansion coefficient of the first conductive structure is smaller than that of copper;
  • interconnection structure layer on the intermetal dielectric layer, the interconnection structure layer being connected to an end of the first conductive structure away from the substrate;
  • a second conductive structure is formed in the substrate, the second conductive structure extends into the inter-metal dielectric layer, and is connected to the first conductive structure.
  • the conductive structure as a first conductive structure and a second conductive structure, and making the thermal expansion coefficient of the first conductive structure smaller than that of copper, the The thermal expansion coefficient of the contact position between the conductive structure and the interconnection structure layer, in this way, in the process of forming the conductive structure or the process of chip operation, the formation of gaps between the substrate and the interconnection structure layer is avoided, and the performance of the chip is improved.
  • FIG. 1 is a schematic structural diagram of a chip provided by an embodiment of the present application.
  • FIG. 2 is a structural schematic diagram 1 of the conductive structure provided by the embodiment of the present application.
  • FIG. 3 is the second structural schematic diagram of the conductive structure provided by the embodiment of the present application.
  • Fig. 4 is a structural schematic diagram III of the conductive structure provided by the embodiment of the present application.
  • FIG. 5 is a process flow diagram of a method for preparing a chip provided in an embodiment of the present application.
  • FIG. 6 is a schematic structural view of the substrate in the method for preparing the chip provided in the embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of filling regions formed in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 8 is a structural schematic diagram 1 of forming a first conductive structure in the chip manufacturing method provided by the embodiment of the present application;
  • FIG. 9 is a schematic structural view of filling holes formed in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 10 is a schematic diagram 2 of forming a first conductive structure in the chip manufacturing method provided by the embodiment of the present application;
  • FIG. 11 is a schematic structural view of forming a first filling groove and a second filling groove in the chip manufacturing method provided by the embodiment of the present application;
  • FIG. 12 is a schematic diagram 3 of forming a first conductive structure in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 13 is a structural schematic diagram 1 of forming an interconnection structure layer in the chip manufacturing method provided by the embodiment of the present application;
  • FIG. 14 is a second structural schematic diagram of forming an interconnection structure layer in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 15 is a process flow chart of forming a second conductive structure in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 16 is a schematic structural view of forming the first intermediate hole in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 17 is a schematic diagram of forming an initial oxide layer and an initial barrier layer in the chip manufacturing method provided by the embodiment of the present application.
  • FIG. 18 is a schematic diagram of forming an oxide layer and a barrier layer in the chip preparation method provided by the embodiment of the present application.
  • FIG. 19 is a schematic diagram of forming a third intermediate hole in the chip preparation method provided in the embodiment of the present application.
  • 10 substrate; 11: isolation structure; 12: intermetal dielectric layer; 13: etch stop layer; 14: filling area; 15: filling hole; 16: first middle hole; 17: second middle hole; 18: The third middle hole; 20: interconnect structure layer; 30: conductive structure; 31: first conductive structure; 311: columnar body; 312: first strip-shaped body; 313: second strip-shaped body; 32: second conductive structure; 40: initial oxide layer; 41: oxide layer; 50: initial barrier layer; 51: barrier layer; 60: first filled groove; 70: second filled groove.
  • DRAM generally includes a plurality of chips stacked in sequence along the vertical direction, and adjacent chips are connected by conductive structures. For example, before stacking, through holes are usually formed on each chip by plasma etching. Finally, a deposition process is used to form copper in the through hole to form a TSV structure in each chip, wherein one end of the conductive structure is connected to the interconnect structure layer of the chip, and the other end of the TSV structure is connected to another adjacent chip. The interconnect structure layer of the chip is connected.
  • the embodiment of the present application provides a method for preparing a chip, a memory, and a chip.
  • the embodiment of the present application provides a chip, including a substrate 10, the substrate 10 is used as a supporting component of the chip for supporting other components arranged thereon, wherein the substrate 10 can be made of a semiconductor material,
  • the semiconductor material may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.
  • the substrate 10 may include an array area and a peripheral circuit area connected to the array area.
  • a plurality of capacitors arranged in an array may be arranged in the array area, and transistors for controlling the capacitors are arranged in the peripheral circuit area.
  • An interconnection structure layer 20 is provided on the substrate 10, wherein a wire can be arranged in the interconnection structure layer 20, one end of the wire can be connected to a transistor, and the other end can be connected to a capacitor, and the connection between the transistor and the capacitor is realized through the interconnection structure layer.
  • the wires in the interconnection structure layer may be the entire conductive layer, or may be a plurality of conductive blocks arranged at intervals, which is not specifically limited in this embodiment.
  • the conductive structure 30 is disposed in the substrate 10 , one end of the conductive structure 30 can be connected to the interconnection structure layer 20 , and the other end can be connected to the interconnection structure layer 20 of a chip adjacent to the chip.
  • an oxide layer 41 and a barrier layer 51 are further provided between the conductive structure 30 and the substrate 10, wherein the material of the oxide layer 41 generally includes silicon oxide, and the barrier layer 51
  • the material of the layer 51 usually includes tantalum, and the thickness of the barrier layer 51 is between 2000-5000A.
  • the tantalum not only prevents penetration between the conductive material and the substrate in the conductive structure, but also has conductivity, ensuring the performance of the chip.
  • the shape of the conductive structure 30 can be selected in many ways, for example, the conductive structure 30 can be a cylinder, wherein the diameter of the conductive structure can be 2-10 ⁇ m, and the height of the conductive structure can be 5-100 ⁇ m.
  • the conductive structure 30 may include a first conductive structure 31 and a second conductive structure 32 connected to the first conductive structure 31, wherein the first conductive structure 31 is connected to the interconnect structure layer 20, and the first conductive structure 31
  • the coefficient of thermal expansion is smaller than that of copper.
  • the thermal expansion coefficient of the second conductive structure may be smaller than that of copper, or may be the same as that of copper.
  • the material of the second conductive structure is the same as that of the first conductive structure, both of which are tungsten.
  • the material of the second conductive structure is different from that of the first conductive structure, wherein the material of the first conductive structure includes tungsten, and the material of the second conductive structure includes copper, which can reduce the cost of the conductive structure, thereby reducing the cost of the chip. the cost of.
  • the conductive structure is usually made of copper, which has a large coefficient of thermal expansion.
  • the conductive structure or other functional devices will generate a large amount of heat, causing the conductive structure to expand due to heat.
  • the surface in contact with the interconnection structure layer will protrude toward the interconnection structure layer, causing the interconnection structure layer to shift away from the conductive structure, resulting in separation between the interconnection structure layer and the conductive structure, reducing the performance and good quality of the chip. Rate.
  • this embodiment improves the material of the conductive structure.
  • the thermal expansion coefficient of the first conductive structure smaller than the thermal expansion coefficient of copper, the thermal expansion coefficient of the contact position between the conductive structure and the interconnection structure layer is reduced, so that in the process of forming the conductive structure In the middle or during the working process of the chip, the formation of gaps between the substrate and the interconnection structure layer is avoided, and the performance of the chip is improved.
  • an intermetallic dielectric layer 12 is generally disposed between the substrate 10 and the interconnect structure layer 20, wherein the intermetal dielectric layer
  • the material of 12 includes silicon oxide.
  • the first conductive structure 31 is located in the intermetal dielectric layer 12
  • a part of the second conductive structure 32 is located in the intermetal dielectric layer 12
  • Another part is located in the base 10 .
  • connection mode of the first conductive structure 31 and the second conductive structure 32 can be described through the following two implementation modes. It should be noted that the following two implementation modes are only examples of two feasible implementation modes. , rather than limiting the arrangement of the first conductive structure and the second conductive structure.
  • the first conductive structure 31 and the second conductive structure 32 are stacked, that is, the first conductive structure 31 is arranged above the second conductive structure 32, and the material of the first conductive structure 31 includes tungsten.
  • the thermal expansion coefficient of tungsten is smaller than that of copper, which reduces the expansion coefficient of the connection between the conductive structure and the interconnection structure layer, avoids the formation of gaps between the substrate and the interconnection structure layer, and improves the performance of the chip.
  • the first conductive structure 31 is disposed in the second conductive structure 32, the top surface of the first conductive structure 31 is flush with the top surface of the second conductive structure 32, the first conductive structure
  • the material of the structure 31 includes tungsten, and the material of the second conductive structure 32 includes copper.
  • the second conductive structure 32 is wrapped outside the first conductive structure 31, which can not only reduce the thermal expansion coefficient of the conductive structure connected to the interconnection structure layer, but also reduce the volume of the first conductive structure, thereby reducing the first conductive structure.
  • the cost of making the structure can not only reduce the thermal expansion coefficient of the conductive structure connected to the interconnection structure layer, but also reduce the volume of the first conductive structure, thereby reducing the first conductive structure.
  • the first conductive structure may be a single piece, or may be a separate piece, that is, the first conductive structure includes multiple substructures.
  • the first conductive structure 31 may include a plurality of columns 311 arranged at intervals, and the plurality of columns 311 are embedded in the second conductive structure.
  • the axis of the columnar body 311 is perpendicular to the base.
  • a plurality of columnar bodies 311 can be arranged in the base 10 at intervals, and the second conductive structure 32 is wrapped outside the columnar bodies.
  • the cost of the first conductive structure can be reduced. volume, so as to reduce the amount of metal tungsten used, thereby reducing the manufacturing cost of the first conductive structure.
  • the plurality of columns 311 can be arranged in a regular array, that is, the plurality of columns 311 are arranged in multiple rows and columns, wherein the columns 311 in adjacent rows
  • the numbers can be equal or unequal. For example, as shown in FIG. 2, along the radial direction of the conductive structure 30, that is, the Y direction shown in FIG. 2, the number of columns 311 in each row can be increased first.
  • the number of pillars 311 in the second row is greater than the number of pillars 311 in the first row
  • the number of pillars 311 in the third row is greater than the number of pillars 311 in the second row
  • the number of pillars 311 in the fourth row is equal to the number of pillars 311 in the third row
  • the number of pillars 311 in the fifth row is greater than the number of pillars 311 in the fourth row
  • the sixth to tenth rows The number of columnar bodies 311 in the row shows a downward trend again.
  • the cross-sectional shape of the columnar body 311 can be circular, that is, the shape of the columnar body 311 can be a cylinder; or the cross-sectional shape of the columnar body 311 can be polygonal, wherein the polygonal Can include quadrilateral, pentagonal or hexagonal, etc.
  • the width of the columns 311 is between 0.07 ⁇ m and 0.2 ⁇ m, which not only ensures that the thermal expansion coefficient of the conductive structure can be reduced, but also reduces the manufacturing cost of the first conductive structure.
  • the first conductive structure 31 includes a first strip 312 and a second strip 313 intersecting the first strip 312. Both the strips 312 and the second strips 313 are embedded in the second conductive structure 32 , and the depth directions of the first strips 312 and the second strips 313 are both perpendicular to the substrate 10 .
  • the first strip-shaped body can be in a regular shape, such as a rectangle, or a broken line shape.
  • the first strip-shaped body 312 can extend along the first direction
  • the second strip-shaped body 313 can extend along the second direction. The first direction and the second direction intersect.
  • first direction and the X direction can be parallel to each other or have a certain angle, for example, as shown in Figure 3, the first strip 312 can extend along the X direction, and the second strip 313 can extend along the Y The direction extends so that the extension directions of the first strip-shaped body 312 and the second strip-shaped body 313 are perpendicular to each other, which is convenient for the preparation of the first strip-shaped body and the second strip-shaped body.
  • an acute angle is formed between the first direction M and the X direction
  • an obtuse angle is formed between the second direction N and the X direction, so that the first strip-shaped body 312 and the second strip-shaped body 313 are inclined relative to the X direction set, and the first direction and the second direction may or may not be perpendicular to each other, preferably, the first direction and the second direction are perpendicular to each other.
  • the number of the first strip-shaped body 312 and the second strip-shaped body 313 can be one or multiple, for example, as shown in Figure 3 and Figure 4, the number of the first strip-shaped body 312 is multiple, The plurality of first bar-shaped bodies 312 are arranged at intervals along the second direction; the number of second bar-shaped bodies 313 is multiple, and the plurality of second bar-shaped bodies 313 are arranged at intervals along the first direction.
  • the proportion of the first conductive structure in the conductive structure can be increased, the thermal expansion coefficient of the conductive structure can be sufficiently reduced, and the substrate and the interconnection are avoided. Gaps are formed between the structural layers, improving the performance of the chip.
  • the longitudinal section of the first strip-shaped body 312 and the second strip-shaped body 313 is rectangular, taking the plane perpendicular to the base 10 as the longitudinal section.
  • the embodiment of the present application also provides a memory, which includes a plurality of chips in the above embodiments, and the plurality of chips are stacked in sequence, and two adjacent layers of chips are connected through a conductive structure.
  • the memory provided in this embodiment has the conductive structure in the above embodiment, so the memory can reduce the thermal expansion coefficient of the contact position between the conductive structure and the interconnection structure layer, so that in the process of forming the conductive structure or the process of chip operation , the expansion rate of the conductive structure is reduced, avoiding the formation of gaps between the substrate of each chip and the interconnection structure layer, improving the performance of each chip, and further improving the performance of the memory.
  • the embodiment of the present application also provides a method for preparing a chip, as shown in Figure 5, including the following steps:
  • Step S100 providing a substrate, an intermetal dielectric layer is disposed on the substrate, and an etching stop layer is disposed in the intermetal dielectric layer.
  • the substrate 10 may be a semiconductor substrate, such as a silicon (Si) substrate.
  • the substrate can also be germanium (Ge) substrate, silicon on insulator (Silicon on Insulator, SOI for short), silicon germanium (SiGe) substrate, silicon carbide (SiC) or gallium nitride (GaN) substrates, etc.
  • An isolation structure 11 may be disposed in the substrate 10, and the isolation structure 11 is used to divide the substrate 10 into a plurality of active regions distributed in an array. It should be noted that FIG. 6 only shows part of the isolation structure and part of the substrate, and Please note that the entire base and all the isolation structures set in the base are not shown.
  • the intermetal dielectric layer 12 can be formed on the substrate 10 by a physical vapor deposition process or a chemical vapor deposition process, wherein an etch stop layer 13 is formed in the intermetal dielectric layer 12, wherein the material of the etch stop layer can include Tungsten, the etch stop layer 13 is used to prevent over-etching when the fill region is subsequently formed, ensuring the performance of the chip.
  • the material of the etch stop layer is set to tungsten in this embodiment, which is different from that of the etch stop layer in the related art. Compared with copper as the material, the thermal expansion coefficient of the first conductive structure can be sufficiently reduced, preventing the formation of gaps between the substrate and the interconnection structure layer, and improving the performance of the chip.
  • the etching stop layer 13 may have a whole layer structure, or may be a plurality of etching stop blocks arranged at intervals, which is not specifically limited in this embodiment.
  • Step S200 forming a first conductive structure in the intermetal dielectric layer, the bottom of the first conductive structure is in contact with the etch stop layer, and the thermal expansion coefficient of the first conductive structure is smaller than that of copper.
  • a filling region is formed in the intermetal dielectric layer 12 , and the bottom surface of the filling region is flush with the top surface of the etch stop layer.
  • a first conductive structure is formed in the filling area, and the material of the first conductive structure includes tungsten.
  • first conductive structure may be integrated or split.
  • process of forming the first conductive structure may refer to the following description:
  • a first photoresist layer may be formed on the intermetal dielectric layer 12 and patterned so that the first photoresist layer has a first opening.
  • the part of the intermetal dielectric layer 12 exposed in the first opening can be removed by using etching gas or etching solution, so as to form a filling in the intermetal dielectric layer 12.
  • Region 14 the bottom surface of the filled region 14 is flush with the top surface of the etch stop layer 13 , that is, the filled region 14 exposes the top surface of the etch stop layer 13 .
  • a first conductive structure 31 is formed in the filling region 14, and the material of the first conductive structure 31 includes tungsten.
  • tungsten can be deposited in the filling region 14 by a physical vapor deposition process or a chemical vapor deposition process, so that the first conductive structure 31 forms an integrated structure.
  • the degree of heat deformation can prevent the formation of gaps between the substrate and the interconnection structure layer, which improves the performance of the chip, and the first conductive structure 31 adopts an integrated structure, which can simplify the preparation process of the first conductive structure.
  • the first conductive structure 31 can be described through the following two implementation modes. It should be noted that the following two implementation modes are only examples of two possible implementations. way, rather than limiting the structure of the first conductive structure.
  • a plurality of filling holes 15 arranged at intervals are formed in the intermetallic dielectric layer 12, the axis of each filling hole 15 is perpendicular to the substrate 10, and the filling holes 15 expose the etched On the top surface of the stop layer 13 , a plurality of filling holes 15 constitute a filling region 14 .
  • a second photoresist layer may be formed on the intermetal dielectric layer 12, and the second photoresist layer is patterned so that the second photoresist layer has a plurality of second openings arranged at intervals, wherein, in this embodiment, if the etch stop layer has a full-surface structure, correspondingly, the second opening exposes a portion of the top surface of the etch stop layer; if the etch stop layer includes a plurality of etch stop blocks arranged at intervals, Correspondingly, the number of etching stoppers is set in one-to-one correspondence with the number and position of the second openings.
  • a plurality of filling holes 15 arranged at intervals are formed in the intermetallic dielectric layer 12 by using etching solution or etching gas, and the axis of each filling hole 15 is perpendicular to the substrate 10. , and the filling hole 15 exposes the top surface of the etch stop layer 13 , that is, the bottom of the filling hole 15 is the top surface of the etch stop layer 13 .
  • the setting of the etching stop layer 13 can prevent the base from being over-etched when the filling hole 15 is formed, thereby improving the performance of the chip.
  • tungsten is deposited in each filling hole 15 by a physical vapor deposition process or a chemical vapor deposition process, so as to form a columnar body 311 in each filling hole 15, and a plurality of The columnar bodies 311 arranged at intervals constitute the first conductive structure 31 .
  • the process steps are as follows:
  • a first filled trench 60 extending along a first direction and a second filled trench 70 extending along a second direction are formed in the intermetal dielectric layer 12 , the first direction and the second direction intersect, and the first Both the bottom of the filled trench 60 and the bottom of the second filled trench 70 are top surfaces of the etch stop layer 13 .
  • the process of forming the first filling groove and the second filling groove is similar to the process steps of forming the filling groove, and will not be repeated here in this embodiment.
  • tungsten is deposited in the first filled groove to form a first strip 312, and the first strip 312 extends along the first direction, and in the second filled groove Tungsten is deposited inside to form a second strip 313 extending along the second direction.
  • the first strip 312 and the second strip 313 constitute the first conductive structure 31 .
  • the number of the first filling groove 60 and the number of the second filling groove 70 can be one or more.
  • a plurality of first filling grooves 60 are formed in the intermetal dielectric layer 12 and the plurality of second filling grooves 70 , the plurality of first filling grooves 60 are arranged at intervals along the second direction, the plurality of second filling grooves 70 are arranged at intervals along the first direction, and the first direction and the second direction are perpendicular to each other.
  • the number of the first strip-shaped body 312 and the number of the second strip-shaped body 313 are multiple, and this embodiment utilizes the setting of a plurality of first strip-shaped bodies and second strip-shaped bodies, which can reduce the first strip-shaped body to the greatest extent.
  • the thermal expansion coefficient of the conductive structure prevents separation between the conductive structure and the interconnection structure layer, improving the performance of the chip.
  • Step 300 forming an interconnection structure layer on the intermetallic dielectric layer, the interconnection structure layer being connected to an end of the first conductive structure away from the substrate.
  • an interconnection structure layer 20 may be formed on the intermetal dielectric layer 12 by using a physical vapor deposition process or a chemical vapor deposition process, wherein the interconnection structure layer 20 covers at least the second On the top surface of a conductive structure 31 .
  • a wire can be arranged in the interconnect structure layer 20, one end of the wire can be connected to a transistor (not shown in the figure) arranged in the substrate, and the other end can be connected to a capacitor (not shown in the figure) arranged in the substrate,
  • the connection of transistors and capacitors is realized through the interconnect structure layer.
  • Step 400 forming a second conductive structure in the substrate, the second conductive structure extends into the IMD layer, and is connected to the first conductive structure.
  • step S410 forming a first middle hole in the base, the bottom wall of the first middle hole being the top surface of the base.
  • a first intermediate hole 16 is formed in the substrate 10, and the bottom wall of the first intermediate hole 16 is the top surface of the substrate 10, that is, the first intermediate hole 16 can be formed in the substrate 10 by using an etching solution or an etching gas.
  • the middle hole 16, the first middle hole 16 exposes the bottom surface of the intermetal dielectric layer 12, that is to say, on the surface of the substrate 10 away from the intermetal dielectric layer 12, an etching solution or an etching gas is passed through to form a second A middle hole 16.
  • Step S420 forming an initial oxide layer and an initial barrier layer stacked on the sidewall and bottom wall of the first intermediate hole, and the initial barrier layer located in the first intermediate hole encloses the second intermediate hole.
  • an initial oxide layer 40 and an initial barrier layer 50 stacked on the sidewall and bottom wall of the first intermediate hole 16 are formed.
  • the initial barrier layer 50 surrounds the second intermediate hole 17, that is, the initial oxide layer 40 and the initial barrier layer 50 are sequentially formed on the sidewall of the first intermediate hole 16 by using an atomic layer deposition process, wherein the material of the initial oxide layer 40 includes Silicon oxide, and the material of the initial barrier layer 50 includes tantalum.
  • Step S430 removing the initial oxide layer and the initial barrier layer located on the bottom wall of the second intermediate hole, and removing the intermetallic dielectric layer exposed in the second intermediate hole, so as to form a third intermediate layer in the intermetallic dielectric layer holes, the third middle hole exposes the first conductive structure and the outer surface of the etch stop layer, and the retained initial oxide layer constitutes an oxide layer, and the retained initial barrier layer constitutes a barrier layer.
  • the initial oxide layer 40 and the initial barrier layer 50 located on the bottom wall of the second intermediate hole 17 are removed by using etching gas, and the retained initial oxide layer 40 forms an oxide layer 41, and the retained The initial barrier layer 50 constitutes a barrier layer 51 .
  • the third intermediate hole 18 exposes the first conductive structure 31 and the etch stop
  • the structure of the outer surface of layer 13 is shown in FIG. 19 .
  • Step S440 forming a second conductive structure in the second middle hole and the third middle hole, where the material of the second conductive structure includes copper.
  • Copper is deposited in the second middle hole 17 and the third middle hole 18 by a chemical vapor deposition process or a physical vapor deposition process, and the copper fills the second middle hole 17 and the third middle hole 18 to form a second conductive structure 32 , that is, the second conductive structure 32 wraps on the outer surfaces of the first conductive structure 31 and the etch stop layer 13 .
  • the process of forming the second conductive structure is the same as the above-mentioned process, which will not be repeated here in this embodiment.

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Abstract

本申请提供一种芯片、存储器及芯片的制备方法，涉及半导体技术领域，该芯片包括具有互连结构层的基底和导电结构，导电结构包括第一导电结构以及与第一导电结构连接的第二导电结构，第一导电结构与互连结构层连接，第一导电结构的热膨胀系数小于铜的热膨胀系数。本申请通过使将导电结构设置成第一导电结构和第二导电结构，并使第一导电结构的热膨胀系数小于铜的热膨胀系数，降低导电结构与互连结构层接触位置的热膨胀系数，这样在形成导电结构的过程或者是芯片工作的过程中，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。

Description

芯片、存储器及芯片的制备方法
本申请要求于2021年05月19日提交中国专利局、申请号为202110547018.3、申请名称为“芯片、存储器及芯片的制备方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及半导体技术领域，尤其涉及一种芯片、存储器及芯片的制备方法。
背景技术
随着集成电路的设计和制造水平的不断发展，电子产品趋向小型化、高度集成化，叠层芯片封装技术应运而生。叠层芯片封装技术也称为三维封装技术，是指在同一个封装体内的垂直方向叠放两个以上芯片的封装技术。例如，动态随机存储器(Dynamic Random Access Memory，简称DRAM)中，通过三维封装技术将多个芯片垂直堆叠并相互连通，以提高DRAM的存储容量。
叠层芯片中，每个芯片通常包括基底以及设置在基底上的互连结构层，其中，利用硅通孔技术(Through Silicon Via，简称TSV)在各芯片上制作相对应的通孔，通孔中填充导电材料，例如铜，以形成TSV结构，TSV结构的一端与互连结构层连接，TSV结构的另一端用于与该芯片相邻的芯片连接，以实现相邻芯片之间导通。
但是，基底与互连结构层之间易形成缝隙，降低芯片的性能。
发明内容
本申请实施例的第一方面提供一种芯片，其包括：
基底，所述基底上设置有互连结构层；
设置在所述基底内的导电结构，所述导电结构包括第一导电结构以及与所述第一导电结构连接的第二导电结构，所述第一导电结构与所述互连结构层连接，所述第一导电结构的热膨胀系数小于铜的热膨胀系数。
本申请实施例第二方面提供了一种存储器，包括多个如上所述的芯片，多个所述芯片依次堆叠设置，相邻的两层芯片之间通过所述互连结构层连接。
本申请实施例的第三方面提供一种芯片的制备方法，包括如下的步骤：
提供基底，所述基底上设置有金属间介电层，所述金属间介电层内设置有刻蚀停止层；
在所述金属间介电层内形成第一导电结构，所述第一导电结构的底部与所述刻蚀停止层接触，所述第一导电结构的热膨胀系数小于铜的热膨胀系数；
在所述金属间介电层上形成互连结构层，所述互连结构层与所述第一导电结构背离所述基底的一端连接；
在所述基底内形成第二导电结构，所述第二导电结构延伸至所述金属间介电层内，并与所述第一导电结构连接。
本申请实施例所提供的芯片、存储器及芯片的制备方法中，通过使将导电结构设置成第一导电结构和第二导电结构，并使第一导电结构的热膨胀系数小于铜的热膨胀系数，降低导电结构与互连结构层接触位置的热膨胀系数，这样在形成导电结构的过程或者是芯片工作的过程中，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。
除了上面所描述的本申请实施例解决的技术问题、构成技术方案的技术特征以及由这些技术方案的技术特征所带来的有益效果外，本申请实施例提供的芯片、存储器及芯片的制备方法所能解决的其他技术问题、技术方案中包含的其他技术特征以及这些技术特征带来的有益效果，将在具体实施方式中作出进一步详细的说明。
附图说明
图1为本申请实施例提供的芯片的结构示意图；
图2为本申请实施例提供的导电结构的结构示意图一；
图3为本申请实施例提供的导电结构的结构示意图二；
图4为本申请实施例提供的导电结构的结构示意图三；
图5为本申请实施例提供的芯片的制备方法的工艺流程图；
图6为本申请实施例提供的芯片的制备方法中基底的结构示意图；
图7为本申请实施例提供的芯片的制备方法中形成填充区的结构示意图；
图8为本申请实施例提供的芯片的制备方法中形成第一导电结构的结构示意图一；
图9为本申请实施例提供的芯片的制备方法中形成填充孔的结构示意图；
图10为本申请实施例提供的芯片的制备方法中形成第一导电结构的示意图二；
图11为本申请实施例提供的芯片的制备方法中形成第一填充槽和第二填充槽的结构示意图；
图12为本申请实施例提供的芯片的制备方法中形成第一导电结构的示意图三；
图13为本申请实施例提供的芯片的制备方法中形成互连结构层的结构示意图一；
图14为本申请实施例提供的芯片的制备方法中形成互连结构层的结构示意图二；
图15为本申请实施例提供的芯片的制备方法中形成第二导电结构的工艺流程图；
图16为本申请实施例提供的芯片的制备方法中形成第一中间孔的结构示意图；
图17为本申请实施例提供的芯片的制备方法中形成初始氧化层和初始阻挡层的示意图；
图18为本申请实施例提供的芯片的制备方法形成氧化层和阻挡层的示意图；
图19为本申请实施例提供的芯片的制备方法形成第三中间孔的示意图。
附图标记：
10：基底；11：隔离结构；12：金属间介电层；13：刻蚀停止层；14：填充区；15：填充孔；16：第一中间孔；17：第二中间孔；18：第三中间孔；20：互连结构层；30：导电结构；31：第一导电结构；311：柱状体；312：第一条形体；313：第二条形体；32：第二导电结构；40：初始氧化层；41：氧化层；50：初始阻挡层；51：阻挡层；60：第一填充槽；70：第二填充槽。
具体实施方式
动态随机存储器通常包括沿垂直方向依次层叠设置的多个芯片，相邻的芯片通过导电结构连接，例如，在层叠之前，通常先利用等离子体刻蚀在各芯片上形成通孔，待形成通孔后，采用沉积工艺在通孔内形成铜，以在各芯片内形成TSV结构，其中，导电结构的一端与该芯片的互连结构层连接，TSV结构的另一端与该芯片相邻的另一个芯片的互连结构层连接。
在键合过程中，铜容易受热膨胀，致使TSV结构背离基底的一端向互连结构层凸出，使得互连结构层沿着垂直于基底的方向发生偏移，进而造成基底与互连结构层之间发生分离，降低芯片的性能。
发明人发现已有的芯片具有基底和互连结构层的偏移的缺陷，但是这一缺陷并不为人所注意，基于此，本申请实施例提供了一种芯片、存储器及芯片的制备方法，通过将导电结构设置成第一导电结构和第二导电结构，并使第一导电结构的热膨胀系数小于铜的热膨胀系数，降低导电结构与互连结构层接触位置的热膨胀系数，这样在形成导电结构的过程或者是芯片工作的过程中，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。
为了使本申请实施例的上述目的、特征和优点能够更加明显易懂，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。显然，所描述的实施例仅仅是本申请的一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动的前提下所获得的所有其它实施例，均属于本申请保护的范围。
如图1所示，本申请实施例提供了一种芯片，包括基底10，基底10 作为芯片的支撑部件，用于支撑设在其上的其他部件，其中，基底10可以由半导体材料制成，半导体材料可以为硅、锗、硅锗化合物以及硅碳化合物中的一种或者多种。
基底10中可以设置有功能器件，比如，基底10可以包括阵列区以及与阵列区连接的外围电路区。其中，阵列区中可以设置有阵列排布的多个电容器，外围电路区中设置有用于控制电容器的晶体管。
基底10上设置有互连结构层20，其中，互连结构层20内可以设置导线，导线的一端可以与晶体管连接，另一端可以与电容器连接，通过互连结构层实现晶体管与电容器的连接。
需要说明的是，互连结构层中的导线可以是整层的导电层，也可以是间隔设置的多个导电块，本实施例在此不做具体的限定。
为了增加存储器的存储容量，通常需要将多个芯片沿垂直方向堆叠到一起，相应地，也就需要在每个芯片上设置导电结构30，利用导电结构30实现多个芯片沿垂直方向的导通。
换而言之，导电结构30设置在基底10内，导电结构30的一端可以与互连结构层20连接，另一端可以与该芯片相邻的芯片的互连结构层20连接。
为了保证导电结构与基底的有源区之间电连接，导电结构30与基底10之间还设置有层叠设置的氧化层41和阻挡层51，其中，氧化层41的材质通常包括氧化硅，阻挡层51的材质通常包括钽，且阻挡层51的厚度位于2000-5000A之间，钽在阻止导电结构中导电材料与基底之间发生渗透的同时，也同时具备导电性，保证了芯片的性能。
导电结构30的形状可以有多种选择，比如，导电结构30可以为圆柱体，其中，导电结构的直径可以为2-10μm，导电结构的高度为5-100μm。
示例性地，导电结构30可以包括第一导电结构31以及与第一导电结构31连接的第二导电结构32，其中，第一导电结构31与互连结构层20连接，第一导电结构31的热膨胀系数小于铜的热膨胀系数。
需要说明的是，第二导电结构的热膨胀系数可以小于铜的热膨胀系数，也可以与铜的热膨胀系数相同，比如，第二导电结构的材质与第一导电结构的材质相同，其材质均为钨；又比如，第二导电结构的材质与第一导电结构的材质不同，其中，第一导电结构的材质包括钨，第二导电结构的材 质包括铜，这样可以降低导电结构的成本，进而降低芯片的成本。
在相关技术中，导电结构的材质通常为铜，铜的热膨胀系数较大，芯片在工作的过程中，导电结构或者其他的功能器件会产生较大的热量，使得导电结构受热膨胀，导电结构与互连结构层接触的表面会朝向互连结构层凸出，致使互连结构层沿背离导电结构的方向发生偏移，进而导致互连结构层与导电结构之间发生分离，降低芯片的性能和良率。
因此，本实施例对导电结构的材质进行了改进，通过使第一导电结构的热膨胀系数小于铜的热膨胀系数，降低导电结构与互连结构层接触位置的热膨胀系数，这样在形成导电结构的过程中或者是芯片工作的过程中，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。
在一些实施例中，为了避免互连结构层与基底中的有源区产生电连接，通常在基底10与互连结构层20之间设置金属间介电层12，其中，金属间介电层12的材质包括氧化硅。
当芯片包括金属间介电层时，以图1所示的结构为例，第一导电结构31位于金属间介电层12内，第二导电结构32的一部分位于金属间介电层12内，另一部分位于基底10内。
第一导电结构31和第二导电结构32的连接方式，可以通过下述的两种实施方式进行描述，需要说明的，下面的两种实施方式仅是示例性地给出两种可行的实施方式，而不是对第一导电结构和第二导电结构的设置方式进行限定。
在一种实施方式中，第一导电结构31与第二导电结构32层叠设置，即，第一导电结构31设置在第二导电结构32的上方，且第一导电结构31的材质包括钨，利用钨的热膨胀系数小于铜的热膨胀系数，降低导电结构与互连结构层连接的位置的膨胀系数，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。
在另一种实施方式中，继续参考图1，第一导电结构31设置在第二导电结构32内，第一导电结构31的顶面与第二导电结构32的顶面平齐，第一导电结构31的材质包括钨，第二导电结构32的材质包括铜。
也就是说，第二导电结构32包裹在第一导电结构31外，这样既可以降低与互连结构层连接的导电结构的热膨胀系数，也可以降低第一导电结 构的体积，进而降低第一导电结构的制作成本。
需要说明的是，在本实施例中，第一导电结构可以为一体件，也可以为分体件，即，第一导电结构包括多个子结构。
示例性地，如图2所示，作为第一导电结构的一种可行的实施方式，第一导电结构31可以包括间隔设置的多个柱状体311，多个柱状体311嵌设于第二导电结构32内，其中，柱状体311的轴线垂直于基底。
继续参考图1，多个柱状体311可以间隔设置在基底10内，第二导电结构32包裹在柱状体的外部，本实施例通过多个独立的柱状体的设置，可以降低第一导电结构的体积，以降低金属钨的用量，进而降低第一导电结构的制作成本。
需要说明的是，在本实施例中，多个柱状体311可以呈规则的阵列排布，即，多个柱状体311呈多行多列进行排布，其中，相邻行中的柱状体311的个数可以相等，也可以不等，比如，如图2所示，沿导电结构30的径向，也就是图2中所示Y方向，每行中的柱状体311的个数可以先增加后减少的趋势，即第二行中柱状体311的个数大于第一行中柱状体311的个数，第三行中柱状体311的个数大于第二行中柱状体311的个数，第四行中柱状体311的个数与第三行中柱状体311的个数相等，第五行中柱状体311的个数大于第四行中柱状体311的个数，第六行至第十行中柱状体311的个数又呈下降的趋势。
以平行于基底10的平面为横截面，柱状体311的横截面形状可以为圆形，即，柱状体311的形状可以为圆柱体；或者柱状体311的横截面形状可以为多边形，其中，多边形可以包括四边形、五边形或者六边形等。
沿垂直于导电结构30的轴线方向，柱状体311的宽度位于0.07μm～0.2μm之间，既要保证能够降低导电结构的热膨胀系数，也要能够降低第一导电结构的制作成本。
如图3和图4所示，作为第一导电结构31的另一种实施方式，第一导电结构31包括第一条形体312以及与第一条形体312交叉设置的第二条形体313，第一条形体312和第二条形体313均嵌设于第二导电结构32内，且第一条形体312的深度方向和第二条形体313的深度方向均垂直于基底10。
在本实施例中，第一条形体可以为规则形状，比如长方形，或者折线 形状，示例性地，第一条形体312可以沿第一方向延伸，第二条形体313可以沿第二方向延伸，第一方向和第二方向相交。
需要说明的是，第一方向与X方向可以相互平行或者具有一定的夹角，例如，如图3所示，第一条形体312可以沿着X方向延伸，第二条形体313可以沿着Y方向延伸，使得第一条形体312和第二条形体313的延伸方向相互垂直，这样便于第一条形体和第二条形体的制备。
又比如，如图4所示，第一方向M与X方向之间为锐角，第二方向N与X方向之间呈钝角，使得第一条形体312和第二条形体313相对于X方向倾斜设置，而第一方向与第二方向可以相互垂直，也可以不垂直，优选地，第一方向与第二方向相互垂直。
第一条形体312和第二条形体313的个数为可以为一个，也可以为多个，示例性地，如图3和图4所示，第一条形体312的个数为多个，多个第一条形体312沿第二方向间隔设置；第二条形体313的个数均为多个，多个第二条形体313沿第一方向间隔设置。
本实施例通过多个第一条形体和多个第二条形体的设置，可以增大第一导电结构在导电结构内所占的比例，充分地降低导电结构的热膨胀系数，避免基底与互连结构层之间形成缝隙，提高了芯片的性能。
为了便于第一条形体和第二条形体的制备，以垂直于基底10的平面为纵截面，第一条形体312和第二条形体313的纵截面形状均为矩形。
本申请实施例还提供了一种存储器，包括多个上述实施例中的芯片，多个芯片依次堆叠设置，相邻的两层芯片之间通过导电结构连接。
在本实施例中提供的存储器，由于具备上述实施例中导电结构，因此，存储器可以降低导电结构与互连结构层接触位置的热膨胀系数，这样在形成导电结构的过程或者是芯片工作的过程中，导电结构的膨胀率降低，避免每个芯片的基底与互连结构层之间形成缝隙，提高了每个芯片的性能，进而提高了存储器的性能。
本申请实施例还提供了一种芯片的制备方法，如图5所示，包括如下的步骤：
步骤S100：提供基底，基底上设置有金属间介电层，且金属间介电层内设置有刻蚀停止层。
如图6所示，基底10可以为半导体基底，例如硅(Si)基底。当然本申请实施例中的并不是限定的，示例性的，基底还可以为锗(Ge)衬底、绝缘体上硅(Silicon on Insulator，简称SOI)、锗化硅(SiGe)衬底、碳化硅(SiC)或者氮化镓(GaN)基底等。
基底10内可以设置有隔离结构11，隔离结构11用于将基底10划分成多个呈阵列分布的有源区，需要说明的是，图6只是示出部分的隔离结构和部分的基底，并未画成整个基底以及设置在基底内隔离结构的全部，请知悉。
金属间介电层12可以通过物理气相沉积工艺或者化学气相沉积工艺形成在基底10上，其中，金属间介电层12内形成有刻蚀停止层13，其中，刻蚀停止层的材质可以包括钨，刻蚀停止层13用于防止后续形成填充区时发生过刻蚀，保证了芯片的性能，此外，本实施例将刻蚀停止层材质设置为钨，与相关技术中刻蚀停止层的材质为铜相比，可以充分地降低第一导电结构的热膨胀系数，防止基底与互连结构层之间形成缝隙，提高了芯片的性能。
需要说明的是，刻蚀停止层13可以整层结构，也可以是间隔设置的多个刻蚀停止块，本实施例在此不做具体的限定。
步骤S200：在金属间介电层内形成第一导电结构，第一导电结构的底部与刻蚀停止层接触，第一导电结构的热膨胀系数小于铜的热膨胀系数。
示例性地，在金属间介电层12内形成填充区，填充区的底面与刻蚀停止层的顶面平齐。
在填充区内形成第一导电结构，第一导电结构的材质包括钨。
需要说明的是，第一导电结构可以为一体式，也可以为分体式的，当第一导电结构为一体式，形成第一导电结构的工艺可以参见如下描述：
可以在金属间介电层12上形成第一光刻胶层，图形化第一光刻胶层，使得第一光刻胶层具有第一开口。
如图7所示，待形成第一开口之后，可以利用刻蚀气体或者刻蚀液，去除暴露在第一开口内的部分金属间介电层12，以在金属间介电层12内形成填充区14，填充区14的底面与刻蚀停止层13的顶面平齐，即，填充区14暴露出刻蚀停止层13的顶面。
如图8所示，待形成填充区14后，在填充区14内形成第一导电结构 31，第一导电结构31的材质包括钨。
即，可以通过物理气相沉积工艺或者化学气相沉积工艺在填充区14内沉积钨，以使得第一导电结构31形成一体结构，本实施例利用钨的热膨胀系数小于铜的热膨胀系数，以降低导电结构的受热的变形度，防止基底与互连结构层之间形成缝隙，提高了芯片的性能，且第一导电结构31采用一体结构，可以简化第一导电结构的制备工艺。
当第一导电结构为分体结构时，第一导电结构31可以通过下述的两种实施方式进行描述，需要说明的，下面的两种实施方式仅是示例性地给出两种可行的实施方式，而不是对第一导电结构的结构进行限定。
作为第一导电结构的一种可行地实施方式，在金属间介电层12内形成间隔设置的多个填充孔15，每个填充孔15的轴线垂直于基底10，填充孔15暴露出刻蚀停止层13的顶面，其中，多个填充孔15构成填充区14。
示例性地，可以在金属间介电层12上形成第二光刻胶层，图形化第二光刻胶层，使得第二光刻胶层具有多个间隔设置的第二开口，其中，在本实施例中，若刻蚀停止层为整面结构，相应地，第二开口就暴露出刻蚀停止层的顶面的部分；若刻蚀停止层包括多个间隔设置的刻蚀停止块，相应地，刻蚀停止块的个数与第二开口的个数及位置一一对应设置。
如图9所示，待形成第二开口之后，采用刻蚀液或者刻蚀气体在金属间介电层12内形成间隔设置的多个填充孔15，每个填充孔15的轴线垂直于基底10，且填充孔15暴露出刻蚀停止层13的顶面，即填充孔15的孔底为刻蚀停止层13的顶面。
本实施例通过刻蚀停止层13的设置，可以防止形成填充孔15时对基底造成过刻蚀，提高了芯片的性能。
如图10所示，待形成填充孔15之后，通过物理气相沉积工艺或者化学气相沉积工艺，在每个填充孔15内沉积钨，以在每个填充孔15内形成一个柱状体311，多个间隔设置的柱状体311构成第一导电结构31。
作为第一导电结构的另一种可行地实施方式，其工艺步骤如下：
如图11所示，在金属间介电层12内形成沿第一方向延伸的第一填充槽60和沿第二方向延伸的第二填充槽70，第一方向和第二方向相交，第一填充槽60的槽底和第二填充槽70的槽底均为刻蚀停止层13的顶面。
在形成第一填充槽和第二填充槽的过程与形成填充槽的工艺步骤相似， 本实施例在此不再多加赘述。
如图12所示，通过物理气相沉积工艺或者化学气相沉积工艺，在第一填充槽内沉积钨，以形成第一条形体312，第一条形体312沿第一方向延伸，在第二填充槽内沉积钨，以形成第二条形体313，第二条形体313沿第二方向延伸，第一条形体312和第二条形体313构成第一导电结构31。
第一填充槽60的个数和第二填充槽70的个数可以为一个，也可以为多个，例如，继续参考图11，在金属间介电层12内形成多个第一填充槽60和多个第二填充槽70，多个第一填充槽60沿第二方向间隔设置，多个第二填充槽70沿第一方向间隔设置，且第一方向与第二方向相互垂直。
相应地，第一条形体312的个数和第二条形体313的个数均为多个，本实施例利用多个第一条形体和第二条形体的设置，可以最大程度地降低第一导电结构的热膨胀系数，防止导电结构与互连结构层之间发生分离，提高了芯片的性能。
步骤300：在金属间介电层上形成互连结构层，互连结构层与第一导电结构背离基底的一端连接。
示例性地，如图13和图14所示，可以利用物理气相沉积工艺或者化学气相沉积工艺在金属间介电层12上形成互连结构层20，其中，互连结构层20至少覆盖在第一导电结构31的顶面上。
其中，互连结构层20内可以设置导线，导线的一端可以与设置在基底中晶体管(图中未示出)连接，另一端可以与设置在基底中的电容器(图中未示出)连接，通过互连结构层实现晶体管与电容器的连接。
步骤400：在基底内形成第二导电结构，第二导电结构延伸至金属间介电层内，并与第一导电结构连接。
示例性地，如图15所示，步骤S410：在基底内形成第一中间孔，第一中间孔的底壁为基底的顶面。
如图16所示，在基底10内形成第一中间孔16，第一中间孔16的底壁为基底10的顶面，即可以利用刻蚀液或者刻蚀气体，在基底10内形成第一中间孔16，第一中间孔16暴露出金属间介电层12的底面，也就是说，向基底10背离金属间介电层12的表面上，通入刻蚀液或者刻蚀气体以形成第一中间孔16。
步骤S420：在第一中间孔的侧壁和底壁上形成层叠设置的初始氧化层 和初始阻挡层，位于第一中间孔内的初始阻挡层围成第二中间孔。
如图17所示，在形成第一中间孔16之后，在第一中间孔16的侧壁和底壁上形成层叠设置的初始氧化层40和初始阻挡层50，位于第一中间孔16内的初始阻挡层50围成第二中间孔17，即，利用原子层沉积工艺在第一中间孔16的侧壁上依次形成初始氧化层40和初始阻挡层50，其中，初始氧化层40的材质包括氧化硅，初始阻挡层50的材质包括钽。
步骤S430：去除位于第二中间孔的底壁上的初始氧化层和初始阻挡层，以及去除暴露在第二中间孔内的金属间介电层，以在金属间介电层内形成第三中间孔，第三中间孔暴露出第一导电结构和刻蚀停止层的外表面，且被保留下来的初始氧化层构成氧化层，被保留下来的初始阻挡层构成阻挡层。
如图18所示，利用刻蚀气体，去除位于第二中间孔17的底壁上的初始氧化层40和初始阻挡层50，被保留下来的初始氧化层40构成氧化层41，被保留下来的初始阻挡层50构成阻挡层51。
以及去除暴露在第二中间孔17内的金属间介电层12，以在金属间介电层12内形成第三中间孔18，第三中间孔18暴露出第一导电结构31和刻蚀停止层13的外表面，其结构如图19所示。
需要说明的是，在图19中，位于虚线上方的区域为第三中间孔18，在虚线下方的区域为第二中间孔17。
步骤S440：在第二中间孔和第三中间孔内形成第二导电结构，第二导电结构的材质包括铜。
通过化学气相沉积工艺或者物理气相沉积工艺，在第二中间孔17和第三中间孔18内沉积铜，该铜填充满第二中间孔17和第三中间孔18，以形成第二导电结构32，即，第二导电结构32包裹在第一导电结构31和刻蚀停止层13的外表面上。
需要说明的是，当第一导电结构31为一体结构时，形成第二导电结构的工艺与上述工艺相同，本实施例在此就不再多加赘述了。
本说明书中各实施例或实施方式采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似部分相互参见即可。
在本说明书的描述中，参考术语“一个实施方式”、“一些实施方式”、 “示意性实施方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合实施方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施方式或示例中。
在本说明书中，对上述术语的示意性表述不一定指的是相同的实施方式或示例。而且，描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施方式或示例中以合适的方式结合。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (19)

  1. 一种芯片，包括：
    基底，所述基底上设置有互连结构层；
    设置在所述基底内的导电结构，所述导电结构包括第一导电结构以及与第一导电结构连接的第二导电结构，所述第一导电结构与所述互连结构层连接，所述第一导电结构的热膨胀系数小于铜的热膨胀系数。
  2. 根据权利要求1所述的芯片，其中，所述第一导电结构设置在所述第二导电结构内，所述第一导电结构的顶面与所述第二导电结构的顶面平齐，所述第一导电结构的材质包括钨，所述第二导电结构的材质包括铜。
  3. 根据权利要求2所述的芯片，其中，所述第一导电结构包括间隔设置的多个柱状体，所述柱状体的轴线垂直于所述基底。
  4. 根据权利要求3所述的芯片，其中，以平行于所述基底的平面为横截面，所述柱状体的横截面形状包括圆形或者多边形。
  5. 根据权利要求2所述的芯片，其中，所述第一导电结构包括第一条形体以及与所述第一条形体交叉设置的第二条形体，所述第一条形体的深度方向和所述第二条形体的深度方向均垂直于所述基底。
  6. 根据权利要求5所述的芯片，其中，所述第一条形体沿第一方向延伸，所述第二条形体沿第二方向延伸，所述第一方向与所述第二方向相交。
  7. 根据权利要求6所述的芯片，其中，所述第一方向与所述第二方向相互垂直。
  8. 根据权利要求7所述的芯片，其中，所述第一条形体的个数为多个，多个所述第一条形体沿所述第二方向间隔设置；
    所述第二条形体的个数均为多个，多个所述第二条形体沿所述第一方向间隔设置。
  9. 根据权利要求8所述的芯片，其中，以垂直于所述基底的平面为纵截面，所述第一条形体和所述第二条形体的纵截面形状均为矩形。
  10. 根据权利要求1-9任一项所述的芯片，其中，所述基底上还设置有金属间介电层，所述第一导电结构设置在所述金属间介电层内，所述第二导电结构的一部分设置在所述基底内，所述第二导电结构的另一部分设置在所述金属间介电层内。
  11. 一种存储器，包括多个如权利要求1-10任一项所述的芯片，多个所述芯片依次堆叠设置，相邻的两层芯片之间通过所述互连结构层连接。
  12. 一种芯片的制备方法，包括如下的步骤：
    提供基底，所述基底上设置有金属间介电层，所述金属间介电层内设置有刻蚀停止层；
    在所述金属间介电层内形成第一导电结构，所述第一导电结构的底部与所述刻蚀停止层接触，所述第一导电结构的热膨胀系数小于铜的热膨胀系数；
    在所述金属间介电层上形成互连结构层，所述互连结构层与所述第一导电结构背离所述基底的一端连接；
    在所述基底内形成第二导电结构，所述第二导电结构延伸至所述金属间介电层内，并与所述第一导电结构连接。
  13. 根据权利要求12所述的芯片的制备方法，其中，在所述金属间介电层内形成第一导电结构的步骤中，包括：
    在所述金属间介电层内形成填充区，所述填充区的底面与所述刻蚀停止层的顶面平齐；
    在所述填充区内形成第一导电结构，所述第一导电结构的材质包括钨。
  14. 根据权利要求13所述的芯片的制备方法，其中，在所述金属间介电层内形成填充区的步骤中，包括：
    在所述金属间介电层内形成间隔设置的多个填充孔，每个填充孔的轴线垂直于所述基底，所述填充孔暴露出刻蚀停止层的顶面，其中，多个所述填充孔构成所述填充区。
  15. 根据权利要求14所述的芯片的制备方法，其中，在所述填充区内形成第一导电结构的步骤中，包括：
    在每个所述填充孔内形成柱状体，多个所述柱状体构成所述第一导电结构。
  16. 根据权利要求13所述的芯片的制备方法，其中，在所述金属间介电层内形成填充区的步骤中，包括：
    在所述金属间介电层内形成沿第一方向延伸的第一填充槽和沿第二方向延伸的第二填充槽，所述第一方向和所述第二方向相交，所述第一填充槽的槽底和所述第二填充槽的槽底均为所述刻蚀停止层的顶面，其中第一 填充槽和所述第二填充槽构成所述填充区。
  17. 根据权利要求16所述的芯片的制备方法，其中，在所述金属间介电层内形成沿第一方向延伸的第一填充槽和沿第二方向延伸的第二填充槽的步骤中，包括：
    在所述金属间介电层内形成多个第一填充槽和多个第二填充槽，多个所述第一填充槽沿第二方向间隔设置，多个所述第二填充槽沿第一方向间隔设置。
  18. 根据权利要求17所述的芯片的制备方法，其中，在所述填充区内形成第一导电结构的步骤中，包括：
    在所述第一填充槽和所述第二填充槽内分别形成第一条形体和第二条形体，所述第一条形体和所述第二条形体构成所述第一导电结构。
  19. 根据权利要求12-18任一项所述的芯片的制备方法，其中，在所述基底内形成第二导电结构的步骤中，包括：
    在所述基底内形成第一中间孔，所述第一中间孔的底壁为所述基底的顶面；
    在所述第一中间孔的侧壁和底壁上形成层叠设置的初始氧化层和初始阻挡层，位于所述第一中间孔内的初始阻挡层围成第二中间孔；
    去除位于所述第二中间孔的底壁上的初始氧化层和初始阻挡层，以及去除暴露在所述第二中间孔内的所述金属间介电层，以在所述金属间介电层内形成第三中间孔，所述第三中间孔暴露出所述第一导电结构和所述刻蚀停止层的外表面，且被保留下来的初始氧化层构成氧化层，被保留下来的初始阻挡层构成阻挡层；
    在所述第二中间孔和所述第三中间孔内形成第二导电结构，所述第二导电结构的材质包括铜。
PCT/CN2021/113127 2021-05-19 2021-08-17 芯片、存储器及芯片的制备方法 WO2022241962A1 (zh)

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