CN102007825B - 一种线路板及其制造方法 - Google Patents

一种线路板及其制造方法 Download PDF

Info

Publication number
CN102007825B
CN102007825B CN2009801134848A CN200980113484A CN102007825B CN 102007825 B CN102007825 B CN 102007825B CN 2009801134848 A CN2009801134848 A CN 2009801134848A CN 200980113484 A CN200980113484 A CN 200980113484A CN 102007825 B CN102007825 B CN 102007825B
Authority
CN
China
Prior art keywords
electric device
auxiliary equipment
plane
binding appts
interim binding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2009801134848A
Other languages
English (en)
Other versions
CN102007825A (zh
Inventor
P·帕姆
A·库贾拉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Imberatec Co., Ltd
Original Assignee
Imbera Electronics Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imbera Electronics Oy filed Critical Imbera Electronics Oy
Publication of CN102007825A publication Critical patent/CN102007825A/zh
Application granted granted Critical
Publication of CN102007825B publication Critical patent/CN102007825B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0097Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/2919Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92142Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/90Methods for connecting semiconductor or solid state bodies using means for bonding not being attached to, or not being formed on, the body surface to be connected, e.g. pressure contacts using springs or clips
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12041LED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/146Mixed devices
    • H01L2924/1461MEMS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/189Printed circuits structurally associated with non-printed electric components characterised by the use of a flexible or folded printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10674Flip chip
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14Related to the order of processing steps
    • H05K2203/1461Applying or finishing the circuit pattern after another process, e.g. after filling of vias with conductive paste, after making printed resistors
    • H05K2203/1469Circuit made after mounting or encapsulation of the components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/15Position of the PCB during processing
    • H05K2203/1536Temporarily stacked PCBs
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49146Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

本发明涉及一种线路板的制造方法,包括以下步骤:安装至少一个结构辅助设备(10)于平面临时粘合设备(2)各侧面、在平面临时粘合设备(2)各侧面的至少一个结构辅助设备(10)上设置槽(3)、埋嵌电元件(4)于槽(3)内,使得电元件(4)的终端(6)背对平面临时粘合设备(2)、安装至少一个电元件(4)于元件箔(5)上,使得电元件(4)的终端(6)面对元件箔(5)、将元件箔(5)至少部分安装于平面临时粘合设备(2)各侧面的至少一个结构辅助设备(10)上。

Description

一种线路板及其制造方法
技术领域
本发明涉及一种线路板技术。本发明特别涉及一种线路板及使用平面临时粘合设备制造具有电元件的线路板的方法。
背景技术
当前技术线路板及其制造方法的重要方面包括密集安装半导体芯片,实现较小横向和纵向尺寸、包括可靠电触点的稳健性与光刻处理期间确保部件良好校准的平坦度。另外,制造线路板的生产工序应尽可能具成本效益,尤其是在批量生产中。成本效益也与线路板上元件的封装密度有关。
线路板的常见问题是制造工序引起的翘曲。例如,线路板热处理期间,因线路板结构内不同材料层的热膨胀系数不同,可能产生翘曲。为减少线路板的翘曲,已提出了各种方法和结构。例如,US20060021791提出在线路板上使用元件的特殊布置,以及JP1248685公开了结构内具附加层以处理其热膨胀特性的线路板结构。
现有技术方法,包括上述公开方法,在减少线路板翘曲中的问题,在于其对线路板的设计强加了限制。这些限制可能涉及如绝缘层和导电层的相对布置、线路板的最小厚度及线路板上集成元件的布置。现有技术解决方法的另一问题在于,制造工序复杂化,因而降低了生产能力和成本效益。线路板设计的灵活性降低也损害了线路板电连接的可靠性。
发明目的
本发明的目的是,通过提供一种新类型线路板和一种新类型线路板制造方法,减少现有技术的前述技术问题。
发明内容
根据本发明的方法,其特征如独立权利要求1所述。
根据本发明的产品,其特征如独立权利要求9所述。
根据本发明的线路板制造方法,包括以下步骤:安装至少一个结构辅助设备于平面临时粘合设备各侧面、在平面临时粘合设备各侧面的至少一个结构辅助设备上设置电元件的槽、埋嵌电元件于槽内使得电元件终端背对平面临时粘合设备、安装至少一个电元件于元件箔上使得电元件终端面对元件箔、将元件箔至少部分安装于平面临时粘合设备各侧面的至少一个结构辅助设备上、以及相互分离平面临时粘合设备各侧面的至少一个结构辅助设备。
根据本发明的线路板包括至少一个电元件、第一结构辅助设备和第二结构辅助设备。线路板进一步包括第一结构辅助设备和第二结构辅助设备间的平面临时粘合设备及安装于埋嵌于电元件槽内的该至少一个电元件上的元件箔,其中槽使用结构辅助设备形成于平面临时粘合设备各侧面上,且元件箔至少部分覆盖远离平面临时粘合设备的侧面的结构辅助设备,且电元件的终端背对平面临时粘合设备。
根据本发明的制造方法能够制造基本对称的线路板双面结构。在此方法中,电元件可埋嵌于线路板结构内,同时在基本对称的双面结构上可进行结构各侧面的布线图制造,之后进行分离结构辅助设备的步骤,即,之后分离双面结构的各个侧面。像这样的对称结构经过热处理或退火时,可最小化结构的翘曲,因为对称平面各侧面的热膨胀系数基本相同。这使得制造工序相对简单,并产生可靠、机械上和电气上稳健的线路板结构。另外,本发明的方法对线路板结构设计未强加限制;只要单个双面结构各侧面的热膨胀系数相似,就可获得该方法和结构的益处。根据本发明的双面产品可用作例如基底结构,且特定布线配置可加工于该基底结构各侧面上,如通过使用传统光刻和沉积技术诸如激光图案形成、化学蚀刻、无电涂覆、电解沉积或各种薄膜沉积技术诸如化学气相沉积(CVD)或等离子体增强化学气相沉积法(PECVD)。该结构各侧面布线图的制造可在分离结构辅助设备步骤前完成,即在分离双面结构各个侧面前完成。
本发明的一个实施方式中,结构辅助设备是模塑树脂片,以埋嵌电元件至模塑树脂片的槽内。模塑树脂片用作结构辅助设备时,电元件可埋嵌于符合元件形状的槽内。这样,元件周围的环绕电元件的材料基本相同,且可使线路板结构非常均质,使得如热膨胀系数非常一致。这进一步有助于最小化线路板结构的翘曲。使用模塑树脂片作为结构辅助设备的其它优势在于,减少了因结构中可能的温度变化引起的机械应力,以及使用小的元件与元件间距离的能力,这可以用于减少线路板模块的宽度和厚度。模塑树脂片也使得能简化线路板结构,并简化了线路板的制造工序流程。
本发明的一个实施方式中,平面临时粘合设备可为箔。
本发明的一个实施方式中,该方法包括在至少一个结构辅助设备和平面临时粘合设备之间于平面临时粘合设备的各侧面上安装结构层。
本发明的另一个实施方式中,平面临时粘合设备的表面积小于安装于平面临时粘合设备各侧面的结构层的表面积,使得平面临时粘合设备各侧面上的结构层在结构层外周部分相互直接接触。
本发明的又一个实施方式中,根据本发明的方法包括在结构层外周部分将平面临时粘合设备各侧面上的结构层粘合在一起。
将平面临时粘合设备各侧面结构层的粘结限制于粘合装置的外周部分(区域),有助于结构层的相互分离以及平面临时粘合设备各侧面结构辅助设备的相互分离。
本发明的一个实施方式中,结构层和/或该至少一个结构辅助设备是聚合物或聚合物复合材料。
本发明的另一个实施方式中,根据本发明的方法包括,通过热处理其中埋嵌有至少一个电元件的结构层和/或至少一个结构辅助设备,至少部分封装该至少一个电元件于填充材料内的步骤。
根据本发明的方法能够制造一种线路板,其中电元件埋嵌于结构层或该至少一个结构辅助设备形成的结构内,并电连接至结构表面上的导体。该埋嵌结构提高了线路板的机械稳定性,并保护埋嵌的电元件不受环境损害。埋嵌结构进一步能够降低组装线路板结构的最终厚度。根据本发明的方法的另一优势在于,该方法不要求开发新的加工设备,而可通过对硬件进行较小改进在许多现有生产线中实施。
本文前述本发明实施方式可以任何相互组合使用。几个实施方式可组合在一起形成本发明的进一步实施方式。本发明相关方法或产品可包括本文前述至少一个实施方式。
附图说明
下文中,将参照附图更详细地说明本发明,其中:
图1是根据本发明第一个实施方式的方法的第一示意图,
图2是根据本发明第一个实施方式的方法的第二示意图,
图3是根据本发明第一个实施方式的方法的第三示意图,
图4是根据本发明第一个实施方式的方法的第四示意图,
图5是根据本发明第一个实施方式的方法的第五示意图,
图6是根据本发明第一个实施方式的方法的第六示意图,
图7是根据本发明第一个实施方式的方法的第七示意图,
图8是根据本发明第一个实施方式的方法的第八示意图,
图9是根据本发明第一个实施方式的方法的第九示意图,
图10是根据本发明第二实施方式的方法的第一示意图,
图11是根据本发明第二实施方式的方法的第二示意图,
图12是根据本发明第二实施方式的方法的第三示意图,
图13是根据本发明第二实施方式的方法的第四示意图,
图14是根据本发明第二实施方式的方法的第五示意图,
图15是根据本发明第二实施方式的方法的第六示意图,
图16是根据本发明第二实施方式的方法的第七示意图,
图17是根据本发明第二实施方式的方法的第八示意图,
图18是根据本发明第二实施方式的方法的第九示意图,
图19a是根据本发明第三实施方式的方法的第一示意图,
图19b是根据本发明第四实施方式的方法的第一示意图,
图20a是根据本发明第三实施方式的方法的第二示意图,
图20b是根据本发明第四实施方式的方法的第二示意图,
图21a是根据本发明第三实施方式的方法的第三示意图,
图21b是根据本发明第四实施方式的方法的第三示意图,
图22是根据本发明第四实施方式的方法的第四示意图,
图23是根据本发明第四实施方式的方法的第五示意图,
图24是根据本发明第四实施方式的方法的第六示意图,
图25是根据本发明第四实施方式的方法的第七示意图,
图26是根据本发明第四实施方式的方法的第八示意图,以及
图27是根据本发明第四实施方式的方法的第九示意图。
为简便起见,在下文示例性实施方式中在重复元件的情况下使用相同项目编号。
应注意,公开的线路板结构仅具有两侧面,因此表述“各侧面”应理解为并非指结构边缘处的侧面。
具体实施方式
图1至9示意性示出了根据本发明第一个实施方式的线路板结构的制造工序。各个图示出了制造工序的一个步骤中线路板的横剖视图。图的顺序对应于制造工序中加工步骤的顺序。
图1和2示出了如何放置电元件4于绝缘元件箔5上。涂覆环氧树脂8于绝缘元件箔5上电元件4将被粘合或另行放置于箔5的位置。电元件4置于绝缘元件箔5上,使得电元件4的终端6面对绝缘元件箔5。电元件4下方的环氧树脂8固化且芯片4的位置在绝缘元件箔5上固定后,选择性移除绝缘元件箔5,使得电元件4的终端6露出。可通过例如光刻后化学蚀刻或激光图案形成,移除终端6下方的绝缘元件箔5,形成终端6下方的旁路孔(via)9。
图3中,包括粘合的电元件4的两片绝缘元件箔5置于平面临时粘合设备2的相对侧,使得电元件4的终端6背对平面临时粘合设备2。在此制造工序阶段中,对称双面结构各侧面的绝缘元件箔5覆盖该结构。平面临时粘合设备2的各侧面具有结构层1,可由如半固化片材料或其它固化或未固化聚合物复合材料制成,包括环氧树脂和增强纤维或聚合物。结构层1的表面积可大于平面临时粘合设备2的表面积,使得结构层1的外周部分伸出平面临时粘合设备2。本发明的该实施方式中,平面临时粘合设备2是适当粘附或不粘附至结构层1的箔。与结构层1的粘附可弱或甚至接近零,以允许制造工序后期相对容易分离该对称双面结构的两侧。
图3示出了线路板结构的几何形状,其中槽3是为将埋嵌于结构内的电元件4设置的。可通过适当放置结构辅助设备10于电元件4周围,为例如单个元件或元件组设置槽3。结构辅助设备10可由例如与结构层1相同材料制成。也应注意,本发明示例性实施方式中所示结构辅助设备10可进一步由几个更小结构实体如薄层制成。
加热图3所示分层结构且将结构置于纵向压力下时,图3所示线路板结构的各个元件,包括聚合物复合材料即结构层1和结构辅助设备10(包括第一结构辅助设备16和第二结构辅助设备17),可组合形成图4所示固体线路板结构。在图4所示结构中,在伸出平面临时粘合设备2的结构层1的外周部分7处,平面临时粘合设备2各侧面上的结构层1相互粘合。电元件4埋嵌于结构层1和结构辅助设备10形成的槽3内。压缩性纵向加压加热期间,结构层1和/或结构辅助设备10的聚合物复合材料内的环氧树脂或其它适当填充材料至少部分填充其中埋嵌有电元件4的槽3,并至少部分封装电元件4于环氧或其它适当填充材料内。这进一步增强并提高了线路板结构的机械稳定性。该工艺步骤期间,结构辅助设备10和结构层1可完全粘合在一起,形成该结构的固体内部。
堆叠并粘合图3所示各个部件于一起以形成图4所示组合结构的确切方式可变化。本发明一个实施方式中,堆叠在一起时,由半固化片材料制成的结构层1和结构辅助设备10均可未固化。之后加热加压至整个堆叠结构以制成结构辅助设备10,结构层1和结构的其它部件相互粘合并将它们固化在一起。本发明的另一个实施方式中,由半固化片材料制成的结构层1可以首先以未固化状态堆叠于平面临时粘合设备2的各侧面。之后加热加压于图4所示结构的该“芯”,以一起粘合并固化结构层1于平面临时粘合设备2各侧面上。仅在形成该“芯”结构后,图4所示结构辅助设备10和该结构其它部件堆叠在一起,压缩并加热,以使结构辅助设备10固化并粘合“芯”即结构层1和平面临时粘合设备2(包括如剥离膜)至元件箔5和至图4所示结构的电元件4。
图5所示结构中,电触点11制造为电元件4的露出的终端6。这已经通过使用导电层例如铜从各侧面涂覆图4的结构,并在导电层制作布线图案以形成指定布线图案和/或电触点11于绝缘元件箔5上而完成。导电层可通过例如无电涂覆、电解沉积或各种薄膜沉积技术如CVD或PECVD制成。例如可使用激光图案形成或光刻后化学蚀刻,执行导电层的布线图案形成。电触点11的制造期间,导电层填充绝缘元件箔5内形成的旁路孔9。导电层沉积前,接触区12表面可通过例如激光处理和/或化学蚀刻进行清理并涂覆不同材料(如钯)的薄层,以减少接触电阻,和增强电触点11的粘附,并提高其稳定性。
为提供附加布线图案,并提高线路板走线性能,可在电触点11上方制造另一绝缘层,即积层13,如图6所示。积层13可例如通过压制聚合物复合材料层于结构(自然地各侧面上)或通过使用诸如PECVD、CVD或原子层沉积(ALD)的薄膜沉积技术制造。为如图7所示在积层13上形成另一布线图案,执行在绝缘元件箔5上形成电触点11的相似步骤。即,通过如激光图案形成和/或光刻后化学蚀刻首先在积层13中形成旁路孔,以选择性暴露电触点11。所得结构由例如铜的导电材料从各侧面涂覆。接着制作该导电涂层图案,以形成指定布线图案14于积层13上。可通过无电涂覆、电解沉积或上述各种薄膜沉积技术制成,或将例如树脂涂覆的铜用作箔,制成导电涂层。可使用如激光图案形成或光刻后化学蚀刻进行导电涂层的图案形成。制作导电涂层时,其填充积层13中形成的旁路孔。电触点11和附加布线图案14间的接触区15的表面可在导电涂层沉积前通过例如激光处理和/或化学蚀刻进行清理并涂覆不同材料(如钯)的薄层,以减少电触点11和附加布线图案14间的接触电阻,并提高接触区15的稳定性。
当图7所示双面对称线路板结构已制成时,可分离该结构的两面,如图8和9所示。分隔双面线路板结构两面的平面临时粘合设备2有助于该分离。实际中,执行该分离使外周部分7首先从整个结构移除。可使用如激光切割和/或机械走线执行外周部分7的移除。外周部分7的移除,去除了结构两面间的紧密粘合,因平面临时粘合设备2的材料选择为避免线路板制造期间结构层1强力粘合至平面临时粘合设备2。移除双面结构的外周部分7后,可例如手动执行线路板两面的分离。图9所示的所得两块线路板可独立使用。
图10至18示意性示出了根据本发明第二实施方式的线路板结构的制造工序。各个图示出了制造工序的一个步骤中线路板结构的横剖视图。图的顺序对应于制造工序中加工步骤的顺序。
图10和11示出了如何放置电元件4于导电元件箔5上。涂覆环氧树脂8于导电元件箔5上电元件将被粘合或另行放置于箔5的位置。电元件4置于导电元件箔5上,使得电元件4的终端6面对导电元件箔5。选择性移除导电元件箔5,使得电元件4的终端6通过旁路孔9露出。导电元件箔5内的旁路孔9可在定位电元件4于元件箔5前或甚至涂覆环氧树脂8于元件箔5前形成。这改善旁路孔9的校准,因其可在同一布线图案形成步骤期间使用校准标记制成,且可少使用一个布线图案形成步骤。可通过如光刻后化学蚀刻或激光图案形成移除终端6下方的导电元件箔5,形成终端6下方的旁路孔9。
图12中,包括粘合的电元件4的两片导电元件箔5置于平面临时粘合设备2的相对侧,使得电元件4的终端6背对平面临时粘合设备2。在此制造工序阶段中,对称双面结构各侧面的导电元件箔5覆盖该结构。本发明的该实施方式中,平面临时粘合设备2是平面结构,其中两片箔边缘粘合如胶粘在一起,同时平面临时粘合设备2中部具有分离两片箔的气隙18。
图12示出了线路板结构的几何形状,其中槽3是为将埋嵌于结构内的电元件4设置的。可通过适当放置结构辅助设备10于电元件4周围,为例如单个元件或元件组设置槽3。结构辅助设备10可由例如聚合物复合材料或聚合物制成。根据第二实施方式的封装结构中,电元件4未整体封装,但其面对平面临时粘合设备2的背面保持露出。因此该封装结构有利于例如应以某种形式保持与环境相通的电元件4。这些元件4可包括如发光二极管(LED)和激光器的光电子装置、各种传感器以及微机电系统(MEMS)元件。
加热图12所示分层结构且将结构置于纵向压力下时,图12所示线路板结构的各个元件,包括聚合物复合材料如结构辅助设备10(包括第一结构辅助设备16和第二结构辅助设备17),可通过平面临时粘合设备2粘合在一起,形成图13所示固体线路板结构。电元件4埋嵌于结构辅助设备10形成的槽3内。纵向加压加热期间,在例如结构辅助设备10的聚合物复合材料内的环氧树脂或其它适当填充材料至少部分填充其中埋嵌有电元件4的槽3,并至少部分封装电元件4于环氧或其它适当填充材料内。这进一步增强并提高了线路板结构的机械稳定性。该工艺步骤期间,结构辅助设备10与平面临时粘合设备2完全或部分粘合。如果电元件4不要求完全封装,所谓的不流动半固化片材料可用于例如结构辅助设备10和/或结构层1。当例如电元件4(如LED、激光器、传感器和MEMS装置的情况下)需暴露于环境时,可能是这样的情况。这些不流动材料不掺和热处理及加压期间流入槽3的材料。
图14所示结构中,电触点11制造为电元件4的露出的终端6。这可通过使用导电层如铜从各侧面涂覆图13的结构,并对导电层和导电元件箔5制作图案以形成指定布线图案和/或电触点11而完成。可使用产生电触点11的相同光刻掩模,对导电元件箔5和导电元件箔5上方导电层的进行布线图案形成。导电层可沉积于线路板结构的整个表面上,通过例如无电铜产生电触点11。
本发明的另一个实施方式中,对本发明的第二实施方式进行了修改,第二导电层可接着沉积于用于电触点11图案形成的阻绝层上。在此实施方式中,前述阻绝层用作积层13,且可在第二导电层制作图案以产生对应于布线图案14的布线图案。在此情况下,布线图案与电触点11间的接触在电触点11纵侧形成。
导电层电连接电元件4的终端6至导电元件箔5。导电层可通过无电涂覆、电解沉积或诸如CVD或PECVD的各种薄膜沉积技术制成。可使用例如激光图案形成、图案电镀或光刻后化学蚀刻,执行导电层和导电元件箔5的图案形成。电触点11的制造期间,导电层填充导电元件箔5内形成的旁路孔9。导电层沉积前,接触区12表面可通过例如激光处理和/或化学蚀刻进行清理并涂覆不同材料(如钯)的薄层,以减少接触电阻,和增强电触点11的粘附,并提高其稳定性。
为提供附加布线图案,并提高线路板走线性能,可在电触点11上方制造另一绝缘层,即积层13,如图15所示。积层13可例如通过压制聚合物复合材料层于结构(自然地在各侧面上)或通过诸如PECVD、CVD或ALD的薄膜沉积技术制造。
为如图16所示在积层13上形成另一布线图案,执行在导电元件箔5上制成电触点11的相似步骤。即,通过如激光图案形成和/或光刻后化学蚀刻首先在积层13中形成旁路孔,以选择性暴露电触点11。所得结构由导电材料如铜(自然地从各侧面)涂覆。接着制作该导电涂层的图案,以形成指定的布线图案14于积层13。可通过无电涂覆、电解沉积或上述各种薄膜沉积技术,或通过将树脂涂覆的铜用作箔,制成导电涂层。可使用如激光图案形成或光刻后化学蚀刻进行导电涂层的图案形成。制作导电涂层时,其填充积层13中形成的旁路孔。电触点11和附加布线图案14间的接触区15的表面可在导电涂层沉积前通过例如激光处理和/或化学蚀刻进行清理并涂覆不同材料(如钯)的薄层,以减少电触点11和附加布线图案14间的接触电阻,并提高接触区15的稳定性。
当图16所示双面对称线路板结构已制成时,可分离该结构的两面,如图17和18所示。通过分隔双面线路板结构两面的平面临时粘合设备2,使得该分离成为可能。可例如手动完成线路板两面的分离。图18所示的所得两块线路板可独立使用。
当执行分离时,从侧面分裂分层临时粘合设备2内两片箔的相互粘合,而箔可仍保持粘附于各侧线路板结构,如图17所示。接着,可从两块线路板移除箔,以使电元件4的表面暴露于环境中,如图18所示。
本发明的另一个实施方式中,如果不需要露出埋嵌的电元件4,例如图12所示平面分层临时粘合设备2的两片箔可保持作为线路板结构的一部分,如图17所示。在此情况下,分层平面临时粘合设备2的两片箔在结构上与例如图3所示第一个实施方式中的结构层1相同,且平面临时粘合设备2可简单视为从侧面胶合在一起的两个结构层1之间的空隙18。在此类似结构中,结构层1可由硬塑料材料或金属制成,两个结构层1的相互粘附通过例如从侧面胶合结构层1实现。
图19a、20a和21a示意性示出了根据本发明第三实施方式的线路板结构制造工序的第一阶段。本发明第三实施方式的工艺流程可继续例如对应于图23-27。对于本领域技术人员,根据本公开内容,这将是显而易见的。图19b、20b、21b和22-27示意性示出了根据本发明第四实施方式的线路板结构的制造工序。各图示出了制造工序的一个步骤中线路板结构的横剖视图。除示出本发明可选实施方式的图19a-21a和19b-21b外,附图顺序对应于制造工序中加工步骤的顺序。
图19-27所示本发明第三和第四实施方式中,平面临时粘合设备2各侧面上仅使用一个结构辅助设备10。这通过使用模塑树脂片作为结构辅助设备10而成为可能。在这些实施方式中,可通过简单地将电元件4压于结构辅助设备10内并例如热处理结构辅助设备(模塑树脂片)10,埋嵌电元件4于槽3内。这样,结构辅助设备10内形成形状符合电元件4形状的电元件4的槽3。加热模塑树脂片且将包括该树脂片的结构置于纵向(垂直于板状结构平面的方向)压力下时,线路板结构的各种元件可结合在一起,以形成固体结构。热使得模塑树脂片内的环氧材料变成流体,且整个树脂片软化。当现将电元件4压在结构辅助设备10上时,模塑树脂片符合元件形状,从而形成电元件4的槽3。这至少部分封装槽3内的电元件4于模塑树脂片的环氧树脂内。环氧树脂固化时,获得固体结构。
模塑树脂片包括具热塑材料如环氧树脂的聚合物复合材料。模塑树脂片材料的准确成分可变化,只要材料允许按照电元件4的形状成形。
如图19a所示,与本发明第二实施方式的图10和图11相似,本发明第三实施方式中,电元件4首先安装于导电元件箔5上,电元件4的终端6面对元件箔5。使用环氧树脂8粘附电元件4于元件箔5,且元件箔5内形成旁路孔以露出终端6。模塑树脂片的结构辅助设备10最初具有层压在其表面上的保护性聚酯(PET)膜19。埋嵌电元件4于结构辅助设备10后,剥除该PET膜19,如图20a所示。通过将元件箔压在结构辅助设备10上同时加热结构辅助设备10,埋嵌电元件4于结构辅助设备10的槽3内,如上所述。
图21a中,包括埋嵌于结构辅助设备10的槽3内的电元件4的两片导电元件箔5置于平面临时粘合设备2的相对侧,使得电元件4的终端6背对平面临时粘合设备2。这两个结构,如图20a所示,在平面临时粘合设备2各侧面加压并退火,以获得基本对称的双面结构。在此制造工序阶段,该基本对称双面结构各侧面的导电元件箔5覆盖该结构。如图21a和图22所示。
获得对应于图22所示结构的对称双面结构的另一可选方式如图19b、20b、21b、和22所示。在本发明的该第四实施方式中,两个结构辅助设备10(模塑树脂片)压在平面临时粘合设备2上,各面一个(图19b),以形成基本对称双面结构。之后,将电元件4压在结构辅助设备10上,电元件4的终端6背对平面临时粘合设备2,以埋嵌电元件4于结构辅助设备10内(如20b和图21b),如上所述。在此埋嵌步骤期间,电元件可如图20b所示独立埋嵌,或它们可粘附于埋嵌步骤后从电元件4移除的支承膜。在已埋嵌电元件4并移除可能使用的支承膜后,使用导电膜即导电元件箔5涂覆图21b所示结构,且元件箔5内形成旁路孔9,以露出终端6。形成元件箔5的导电涂层可通过例如无电涂覆、电解沉积或诸如CVD或PECVD的各种薄膜沉积技术沉积于电元件4及其终端6;获得图22所示结构。旁路孔9可按上述形成。
第三和第四实施方式中的结构辅助设备10(即模塑树脂片)的表面积大于平面临时粘合设备2的表面积,使得结构辅助设备10的外周部分伸出平面临时粘合设备2。本发明的这些实施方式中,平面临时粘合设备2可为适当粘附或不粘附于结构辅助设备10的箔。与结构辅助设备10的粘附可弱或甚至接近零,以允许制造工序后期相对容易分离该基本对称双面结构的两侧。
图23所示结构中,电触点11制造为电元件4的露出的终端6。这可通过使用导电层如铜从各侧面涂覆图22所示结构,并在导电层和导电元件箔5进行图案形成以形成指定的布线图案和/或电触点11而完成。可使用产生电触点11的相同光刻掩模,执行导电元件箔5和导电元件箔5上方导电层的图案形成。导电层可通过例如无电镀铜沉积于线路板结构的整个表面上。为了提供附加布线图案,并提高线路板走线性能,可在电触点11上方制造另一绝缘层,即积层13,如图24所示。
第四实施方式中用于形成布线图案和/或与电元件4终端6的电触点的加工步骤,与例如第二实施方式的相应加工步骤相同。图14-16所示第二实施方式的这些加工步骤与图23-25所示第四实施方式相对应。
当图25所示双面对称线路板结构已制成时,可分离该结构的两面,如图26和27所示。通过分隔双面线路板结构两面的平面临时粘合设备2,使得能够轻松进行该分离。移除第一和第二结构辅助设备16、17粘合在一起(图26)的结构外周部分后,可例如手动完成线路板两面的分离。图27所示的所得两块线路板可独立使用。
上述实施方式中,平面临时粘合设备2的确切结构可变化。粘合装置2可例如为第一个实施方式中的简易箔,或第二实施方式中的分层结构。平面临时粘合设备2设计为有助于分离对称双面线路板结构2的两侧。粘合装置2可进一步设计为通过平面结构中部周围的一个或多个点将基本对称的双面结构两侧临时粘合在一起。简易箔的所需粘附特性可根据线路板结构和制造工序从不粘附至完全粘附变化。箔也可例如完全粘合周围结构,但适当热处理可分裂箔,以使双面结构的侧面相互剥离。本发明的一个实施方式中,平面临时粘合设备2可通过在按压在一起前固化由未固化片材料制成的结构层1实现。在此实施方式中,结构层1之间不需要剥离箔(或其它结构),因为非固化片材料内已固化的树脂未使结构层1在后续加工步骤中相互粘合。在此情况下,结构辅助设备10可成形,使其通过结构外周部分临时粘合双面结构的两侧在一起,以用于进一步加工。
上述本发明实施方式的线路板结构在要求大量热处理的那些工艺步骤中保持基本对称。这样可最小化埋嵌结构的翘曲。这对于电元件位于线路板结构内且因而对结构形状的变化非常敏感的埋嵌结构非常重要。通过保持双面结构各侧面的热膨胀系数相似,可最小化翘曲。这并不一定意味着各侧布线图案应完全相同。因此,在结构的不同侧面可设计不同布线图案。除减少翘曲外,图1-27所示本发明实施方式可用于基本加倍生产线的生产量,因为单个双面结构可获得两个线路板。埋嵌结构进一步提高了线路板的机械和电稳定性,并增加了线路板内电元件4的封装密度。
对于本领域技术人员很明显地,本发明不限于上述示例,而是实施方式可在权利要求的范围内自由变化。

Claims (10)

1.一种线路板的制造方法,其特征在于该方法包括下述步骤:
-安装至少一个结构辅助设备(10)于平面临时粘合设备(2)各侧面上,
-在所述平面临时粘合设备(2)各侧面的所述至少一个结构辅助设备(10)上设置用于电元件(4)的槽(3),
-埋嵌所述电元件(4)于槽(3)内,使得所述电元件(4)的终端(6)背对所述平面临时粘合设备(2),
-安装至少一个电元件(4)于元件箔(5)上,使得所述电元件(4)的终端(6)面对所述元件箔(5),
-将所述元件箔(5)至少部分安装在所述平面临时粘合设备(2)各侧面的所述至少一个结构辅助设备(10)上,以及
-将所述平面临时粘合设备(2)各侧面的所述至少一个结构辅助设备(10)相互分离。
2.根据权利要求1所述的方法,其特征在于所述结构辅助设备(10)是模塑树脂片,以埋嵌所述电元件(4)于所述模塑树脂片的所述槽(3)内。
3.根据权利要求1-2任一项所述的方法,其特征在于所述平面临时粘合设备(2)是箔。
4.根据权利要求1或2所述的方法,其特征在于该方法包括下述步骤:
-在所述至少一个结构辅助设备(10)和所述平面临时粘合设备(2)之间于所述平面临时粘合设备(2)的各侧面上安装结构层(1)。
5.根据权利要求4所述的方法,其特征在于所述平面临时粘合设备(2)的表面积小于安装于所述平面临时粘合设备(2)各侧面的所述结构层(1)的表面积,使得所述平面临时粘合设备(2)各侧面上的所述结构层(1)在所述结构层(1)的外周部分(7)相互直接接触。
6.根据权利要求5所述的方法,其特征在于该方法包括下述步骤:
-在所述结构层(1)的外周部分(7)将所述平面临时粘合设备(2)各侧面的结构层(1)粘合在一起。
7.根据权利要求4所述的方法,其特征在于所述结构层(1)和/或所述至少一个结构辅助设备(10)是聚合物或聚合物复合材料。
8.根据权利要求4所述的方法,其特征在于该方法包括以下步骤:
-通过热处理其中埋嵌有所述至少一个电元件(4)的结构层(1)和/或至少一个结构辅助设备(10),至少部分封装所述至少一个电元件(4)于填充材料内。
9.一种线路板,包括至少一个电元件(4)、第一结构辅助设备(16)和第二结构辅助设备(17),其特征在于线路板包括所述第一结构辅助设备(16)和所述第二结构辅助设备(17)间的平面临时粘合设备(2)、以及安装于埋嵌于用于电元件(4)的槽(3)内的所述至少一个电元件(4)上的元件箔(5),其中槽(3)使用结构辅助设备(16、17)形成于所述平面临时粘合设备(2)各侧面上,且所述元件箔(5)至少部分覆盖远离所述平面临时粘合设备(2)的侧面的所述结构辅助设备(16、17),且所述电元件(4)的终端(6)背对所述平面临时粘合设备(2)。
10.根据权利要求9所述的线路板,其特征在于所述结构辅助设备(16、17)是模塑树脂片,以埋嵌所述电元件(4)于所述模塑树脂片的所述槽(3)内。
CN2009801134848A 2008-04-18 2009-04-06 一种线路板及其制造方法 Active CN102007825B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI20085332 2008-04-18
FI20085332A FI121909B (fi) 2008-04-18 2008-04-18 Piirilevy ja menetelmä sen valmistamiseksi
PCT/FI2009/050256 WO2009127780A1 (en) 2008-04-18 2009-04-06 Wiring board and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN102007825A CN102007825A (zh) 2011-04-06
CN102007825B true CN102007825B (zh) 2013-05-08

Family

ID=39385957

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009801134848A Active CN102007825B (zh) 2008-04-18 2009-04-06 一种线路板及其制造方法

Country Status (7)

Country Link
US (1) US8286341B2 (zh)
EP (1) EP2274962B1 (zh)
JP (1) JP5551680B2 (zh)
KR (1) KR101260908B1 (zh)
CN (1) CN102007825B (zh)
FI (1) FI121909B (zh)
WO (1) WO2009127780A1 (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796522B1 (ko) 2006-09-05 2008-01-21 삼성전기주식회사 전자소자 내장형 인쇄회로기판의 제조방법
WO2009145727A1 (en) * 2008-05-28 2009-12-03 Agency For Science, Technology And Research A semiconductor structure and a method of manufacturing a semiconductor structure
DE102009058764A1 (de) 2009-12-15 2011-06-16 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung einer elektronischen Baugruppe und elektronische Baugruppe
KR101055462B1 (ko) 2010-01-07 2011-08-08 삼성전기주식회사 인쇄회로기판 제조용 캐리어와 그 제조방법 및 이를 이용한 인쇄회로기판의 제조방법
US8735735B2 (en) 2010-07-23 2014-05-27 Ge Embedded Electronics Oy Electronic module with embedded jumper conductor
TWI446497B (zh) * 2010-08-13 2014-07-21 Unimicron Technology Corp 嵌埋被動元件之封裝基板及其製法
KR101417264B1 (ko) * 2012-04-25 2014-07-08 엘지이노텍 주식회사 인쇄회로기판 및 그의 제조 방법
TWI463620B (zh) * 2012-08-22 2014-12-01 矽品精密工業股份有限公司 封裝基板之製法
JP2014130856A (ja) * 2012-12-28 2014-07-10 Kyocer Slc Technologies Corp 配線基板の製造方法
DE102013102542A1 (de) * 2013-03-13 2014-09-18 Schweizer Electronic Ag Elektronisches Bauteil und Verfahren zum Herstellen eines elektronischen Bauteils
US9941229B2 (en) * 2013-10-31 2018-04-10 Infineon Technologies Ag Device including semiconductor chips and method for producing such device
US9922844B2 (en) 2014-03-12 2018-03-20 Mediatek Inc. Semiconductor package and method for fabricating base for semiconductor package
CN104103529A (zh) * 2014-07-22 2014-10-15 华进半导体封装先导技术研发中心有限公司 一种扇出型方片级半导体三维芯片封装工艺
CN104103527B (zh) * 2014-07-22 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种改进的扇出型方片级半导体芯片封装工艺
CN104103528A (zh) * 2014-07-22 2014-10-15 华进半导体封装先导技术研发中心有限公司 一种扇出型方片级半导体芯片封装工艺
CN104103526B (zh) * 2014-07-22 2017-10-24 华进半导体封装先导技术研发中心有限公司 一种改进的扇出型方片级三维半导体芯片封装工艺
WO2017026195A1 (ja) * 2015-08-11 2017-02-16 株式会社村田製作所 キャパシタ内蔵基板の製造方法
EP3206229B1 (en) 2016-02-09 2020-10-07 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Methods of manufacturing flexible electronic devices
EP3255665B1 (en) * 2016-06-08 2022-01-12 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Electronic device with component carrier and method for producing it
CN109637981B (zh) * 2018-11-20 2021-10-12 奥特斯科技(重庆)有限公司 制造部件承载件的方法、部件承载件以及半制成产品
WO2021146894A1 (zh) * 2020-01-21 2021-07-29 鹏鼎控股(深圳)股份有限公司 内埋电子元件的电路板及制作方法
CN111315158A (zh) * 2020-03-27 2020-06-19 深圳市景旺电子股份有限公司 线路板制造方法及线路板

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3739438A (en) * 1970-02-25 1973-06-19 Union Carbide Corp System for molding electronic components

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3650648A (en) * 1970-02-25 1972-03-21 Union Carbide Corp System for molding electronic components
JPH01248685A (ja) 1988-03-30 1989-10-04 Shin Kobe Electric Mach Co Ltd 片面金属箔張積層板の製造法および片面印刷回路板の製造法
JPH07273424A (ja) * 1994-03-29 1995-10-20 Ibiden Co Ltd 片面プリント配線板の製造方法
KR100302652B1 (ko) 1998-09-11 2001-11-30 구자홍 플렉시블인쇄회로기판의제조방법및그방법으로생산한플렉시블인쇄회로기판
US6838750B2 (en) 2001-07-12 2005-01-04 Custom One Design, Inc. Interconnect circuitry, multichip module, and methods of manufacturing thereof
JP2004335641A (ja) * 2003-05-06 2004-11-25 Canon Inc 半導体素子内蔵基板の製造方法
CN100524734C (zh) 2003-09-09 2009-08-05 三洋电机株式会社 含有电路元件和绝缘膜的半导体模块及其制造方法以及其应用
JP4541763B2 (ja) 2004-01-19 2010-09-08 新光電気工業株式会社 回路基板の製造方法
JP4575071B2 (ja) 2004-08-02 2010-11-04 新光電気工業株式会社 電子部品内蔵基板の製造方法
JP4334005B2 (ja) * 2005-12-07 2009-09-16 新光電気工業株式会社 配線基板の製造方法及び電子部品実装構造体の製造方法
JP2007173727A (ja) * 2005-12-26 2007-07-05 Shinko Electric Ind Co Ltd 配線基板の製造方法
US7353591B2 (en) * 2006-04-18 2008-04-08 Kinsus Interconnect Technology Corp. Method of manufacturing coreless substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3739438A (en) * 1970-02-25 1973-06-19 Union Carbide Corp System for molding electronic components

Also Published As

Publication number Publication date
WO2009127780A1 (en) 2009-10-22
EP2274962A4 (en) 2017-06-28
FI121909B (fi) 2011-05-31
JP2011517858A (ja) 2011-06-16
JP5551680B2 (ja) 2014-07-16
FI20085332A0 (zh) 2008-04-18
EP2274962A1 (en) 2011-01-19
US20090260866A1 (en) 2009-10-22
EP2274962B1 (en) 2018-07-11
US8286341B2 (en) 2012-10-16
KR101260908B1 (ko) 2013-05-07
KR20090110790A (ko) 2009-10-22
CN102007825A (zh) 2011-04-06

Similar Documents

Publication Publication Date Title
CN102007825B (zh) 一种线路板及其制造方法
CN103167727B (zh) 电路板及其制造方法
CN102479762B (zh) 散热增益型半导体组件
CN102119588B (zh) 元器件内置模块的制造方法及元器件内置模块
CN104756611A (zh) 用于制造集成在基底中的或施加在基底上的线圈的方法以及电子装置
JP5289832B2 (ja) 半導体装置および半導体装置の製造方法
EP3355666B1 (en) Semifinished product and method of manufacturing a component carrier
CN104299919B (zh) 无芯层封装结构及其制造方法
TW201424501A (zh) 封裝結構及其製作方法
CN107295746A (zh) 器件载体及其制造方法
CN104768318B (zh) 软硬结合电路板及其制作方法
KR101701380B1 (ko) 소자 내장형 연성회로기판 및 이의 제조방법
EP2141973A1 (en) Method of providing conductive structures in a multi-foil system and multi-foil system comprising same
KR101417264B1 (ko) 인쇄회로기판 및 그의 제조 방법
US20210358883A1 (en) Fan-out packaging method employing combined process
CN101299905B (zh) 电路板及其制作方法
JP5221682B2 (ja) プリント回路基板及びその製造方法
CN205546200U (zh) 刚柔结合板装置和半成品刚柔结合板装置
CN215187581U (zh) 散热型封装基板
CN108260304B (zh) 复合电路板及其制造方法
US20240155765A1 (en) Electronic component embedded substrate and manufacturing method therefor
CN106504999A (zh) 具内建金属块及防潮盖的散热增益型线路板及其制备方法
JP6711245B2 (ja) プリント基板の製造方法および電子装置の製造方法
CN115623679A (zh) 散热型封装基板及其制备方法
KR101051959B1 (ko) 반도체 패키지용 기판 및 그 제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP03 Change of name, title or address

Address after: Helsinki

Patentee after: GE Embedded Electronics OY

Address before: Espoo, Finland

Patentee before: IMBERA ELECTRONICS OY

CP03 Change of name, title or address
TR01 Transfer of patent right

Effective date of registration: 20200908

Address after: Virginia

Patentee after: Imberatec Co., Ltd

Address before: Helsinki

Patentee before: GE Embedded Electronics OY

TR01 Transfer of patent right