CN101952960B - 低温加压烧结的方法 - Google Patents

低温加压烧结的方法 Download PDF

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CN101952960B
CN101952960B CN2009801051597A CN200980105159A CN101952960B CN 101952960 B CN101952960 B CN 101952960B CN 2009801051597 A CN2009801051597 A CN 2009801051597A CN 200980105159 A CN200980105159 A CN 200980105159A CN 101952960 B CN101952960 B CN 101952960B
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heat sink
sink plate
substrate
sintering
pressure sintering
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R·艾泽勒
M·科克
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Danfoss Silicon Power GmbH
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Abstract

一种用于低温加压烧结至少一个待热接触并且机械固定连接的电子组件(3)的方法,这些电子组件位于衬底(4)上,该方法具有步骤:在用于热沉连接的衬底的连接平面暴露的情况下利用模型包封矩阵对电子组件进行模压,提供热沉板(6),将烧结连接层(5)施加在连接平面的暴露的区域上和/或施加在为了接触而设置的热沉板的区域上,以及借助银低温加压烧结技术将热沉板在连接平面的区域中材料锁定地连接到电子组件的衬底。

Description

低温加压烧结的方法
技术领域
本发明涉及一种用于加压烧结的方法。
背景技术
具有一个或多个半导体元件的功率电子电路的电子组件典型地借助胶粘结合、焊接或银加压烧结技术将未保护的半导体设置在主要电路载体上来制造。在该过程中,优选采用陶瓷电路载体(所谓的DCB衬底,即direct copper bonded(直接铜接合)衬底)。
这种衬底由膨胀系数为7-8ppm/K和大约4ppm/K的铝氧化物或铝氮化物构成的核组成。该衬底还可以是以薄层混合载体形式存在的纯陶瓷解决方案,并具有金属化的或敷设的印刷线路,该薄层混合载体由铝氧化物或铝氮化物构成。还可以将一个或多个半导体直接安装在作为电路载体的金属引线框架(Stanzgitter)上。US2004-026778A1展示了在没有绝缘衬底的情况下将半导体直接安装在引线框架的片段上。
借助超声线接合(Drahtbondung),这些半导体相互电连接并且与衬底的金属印刷线路或与引线框架电连接。为了提高(动态情况和静止情况的)损耗功率输出,所配备的衬底或引线框架通常用连接层(胶粘结合,用热导膏压力接触,焊接或加压烧结)构建在热沉板上(例如本申请人的实用新型20005746U1)。典型地,对于功率强大的模块来说还通过焊接或加压烧结在一个共用的热沉板上安装多个衬底组件(以串联和并联电路的形式)。在加压烧结的情况下,首先衬底板和半导体与该共用的热沉板连接,然后才通过将所有参与的所配备的衬底板进行线接合而进行电接触。
该热沉板在动态热流的情况下利用所选择的材料(优选铜)的热容量来提供优化的能量缓冲。尤其是在该电路的脉冲运行情况下,热沉板降低了动态热阻(Zth)。相反,在通过半导体的损耗功率的热流的静止情况下,该放热
Figure BPA00001201277400011
功能是有意义的。在此,放热板的导热能力以及其相对于衬底被扩大的尺寸是决定性的。这导致有利的热阻(Rth)。
为了在携带电位的部件(接合线
Figure BPA00001201277400021
,半导体和印刷线路)之间实现高度的电绝缘以及达到非常高的机械强度和鲁棒性,存在这些组件被热固性塑料包封的产品。这种制造技术由通过模压(传递模塑)来用热固性塑料的、硬的、玻璃状的聚合物材料(例如Henkel LoctiteHysol)来根据体积完全包封模块体组成。这是利用单个半导体元件(例如以ST微电子公司IRF-540的TO220包装形式)以及例如US2005/0067719A1的晶体管组来实现的。
几种产品除了包封衬底组件之外还包封了所安装的热沉板,例如Mitsubishi公司的DIP-IPM(“A New Version Intelligent Power Modulefor High Performance Motor Control”;M.Iwasaki等人;PowerSemiconductor Device Division,Mitsubishi,Japan)。
1.1现有技术的缺点和改进
缺点1:在加压烧结时由于未经测试的衬底组件造成出产量损耗
在仅一个热沉板上设置由多个衬底组件(多衬底模块)组成的串联或并联电路的情况下,特别不利的是,由于需要经济地产出,只能在一个共用的热沉板上安装经过良好测试的电的单个组件。这种节省成本的制造和检验步骤在借助银加压烧结进行安装时是不可能的,因为在烧结过程中对这些组件的几乎均衡的压制可能破坏电连接的组件的接合线。
为了改进该现有技术,建议通过模压按照所描述的方式首先将事先经过测试的衬底组件形成为鲁棒的、可机械负荷的组件(模型模块(Mold-Modul))。
这样的经过模压的组件可以借助加压烧结通过单轴或几乎均衡的压制与热沉板通过银烧结连接。因此,按照这种设计仅对经过良好测试的衬底组件作进一步处理。该烧结过程可以用至少一个模型模块执行,但是也可以用多个模型模块在仅一个热沉板上同时进行。
缺点2:被包封的组件与集成的热沉板由于膨胀差异很大而变形
a)所描述的模压(传递模塑)的过程对全部组件来说具有以下缺点:要重新加热到大约170℃-200℃(聚合物络合的热启动)。在此,已经连接的以及由热沉板材料、连接层、衬底、连接层和半导体组成的叠层相应于它们的个体热膨胀系数而变形。这些连接层的层附着和抗切强度导致永久的叠加的总变形。
优选的热沉材料是铜,铜的高膨胀系数(18ppm/K)导致材料叠层相对于平坦的冷却器平面存在空心变形,在该冷却器平面上将在终端用户那里安装以后的组件。
通过模压在热变形阶段(在175℃到200℃的过程温度下)对该元件的包封导致强烈地阻止了空心变形的恢复。部分地,材料层和包封的热固性塑料之间的机械切变应力很大,以至于包封和叠层之间和/或热叠层的各个层之间发生破坏性的分层(Delamination)。
即使不发生分层,在该过程之后也会留下引起干扰的空心变形。功率电子组件相对于平坦冷却器的这种空心变形必须被无条件地避免,因为不能再保证对晶体管散热所需要的热流。
b)热沉板通过放热以及依据材料以及总热容量的提高等实现其功能。为此,热沉板必须比该热沉板上面所连接的衬底板具有更大的表面。热固性塑料的包封由于所追求的强度而必须以鲁棒的壁厚度包围热沉板,从而该热沉板在该包封的一侧看起来是平面等齐的。但是,热固性塑料的成型料(Formmasse)的成本相对较高,从而所需要的热沉板的热尺寸一般被不容许地减小了。在这种产品的公知结构中,放热板通过胶合层安装。
c)热沉板有时候还从外部借助导热膏安装在衬底模块的下方(模型包封地或者基于框架的)。但是,这种形状连贯(formschlüssig)的安装由于膏体的导热性能很低(1-5W/mK)以及膏体的长时间稳定性及其功能(抽空效应)而存在缺点。
下面的过程步骤根据本发明应当避免所描述的缺点,并且一方面清楚地导致热沉板相对于平坦的冷却器具有可重现的凸状变形,另一方面在热沉板具有正确尺寸的同时对成型料实现很大的节省。
发明内容
本发明的方法利用独立权利要求的特征解决上述问题。
在此,改变制造过程链,使得在没有热沉板(以及没有用于热沉板的烧结连接层)的情况下用热固性塑料的包封料来模压出所述电子组件。模型包封料的膨胀系数现在仅与热主导的陶瓷衬底(4至6ppm/K)匹配,并且明显低于例如由铜制成的热沉板的热膨胀系数(18ppm/K)。
现在,由于热固性塑料和配备的衬底之间没有匹配而导致的变形不再存在。被包封的衬底的体积明显更小,并且材料和能量消耗相应更经济也更生态(参见图1a,1b和图2a,2b)。
此外,可以在一次烧结过程中为热沉板配备多个电并联的单个包封的组件。
附图说明
本方法的其它优点和特征从以下对优选实施例的描述中得出。
图1a示出根据现有技术的热沉板集成在模型包封体中,其缺点是该体积相对于从外部设置的热沉板较大,而且热沉板不再具有扩展功能,
图1b示出图1a的热沉板,但是是热沉板的侧面视图,
图2a示出热沉板从外部材料锁定地(stoffschlüssig)安装在完成的模型包封体上,其缺点是热固性塑料体积相对于图1的体积较小,而且连接层是高导热的经过烧结的银层,
图2b示出表面增大的热沉板从外部材料锁定地安装在完成的模型包封体上,其优点是热固性塑料体积相对于图1的体积较小,连接层是高导热的经过烧结的银层,放热被进一步优化(相对于图2a)并且通过例如螺丝来实现到冷却器的简单安装可能,
图3示出表面增大的热沉板从外部材料锁定地安装在已完成的模型包封体上,具有以下额外优点:热沉板被分段,并且由于很小的绝对大小还可以将绝对膨胀系数保持得更小。更小的膨胀系数意味着更小的切变应力并且由此相对于温度变化负荷具有更长的寿命,
图4示出表面增大的热沉板从外部材料锁定地安装在多个模型包封体上,优点是现在由各个经过测试的模块组成的多衬底模块也可以借助加压烧结技术材料锁定地安装在一个共用的热沉板上(在此利用多种旋紧方式以提供作用在冷却器上的最佳压制力),
图5a示出图4的热沉板,加上扩大表面的结构,如用于冷却空气的飞边或图中所示的管脚,以及
图5b示出图4的用于直接冷却水的热沉板,具有由金属或塑料组成的附加的槽,水将被引入该槽中。
具体实施方式
热沉板现在在另一个连接过程中,也就是银烧结压制技术,与电组件的已完成的模型包封体材料锁定(而且长时间稳定)地连接(图2a,2b)。所烧结的银连接层典型地具有大约250W/mK的导热性,由此与任何导热膏以及任何粘合剂和焊剂进一步热地和机械地叠加。
a.现在可以选择具有足够的大小、也就是至少与衬底大小一致地(主要功能;高的热容量)或与模型包封体一致地、或者优选还大于模型包封体(放热和热容量提高)的热沉板。
b.加压烧结技术通过温度和压力关联起来。该压力将热沉板按压在具有比完成连接后在冷却之后设置的更小半径的底板(=压制下冲头)中。热沉板弹回到下冲头的半径;通过连接层与衬底连接,在冷却之后变成最终的形状。现在可以通过加压烧结压力机的下冲头的半径来有针对性地影响所期望的凸状模型。
该布置可以用以下改进措施来优化:
c.如果热沉大于模型包封体,则超出该模型包封体的平面具有用于安装螺丝的孔。
d.在衬底板下面的热沉可以被分段。优选的,在衬底上的散发任何热量的元件(晶体管,二极管)下方应当设置子热沉,该子热沉的大小分别至少与该元件的面积需要相同。各个子热沉具有比完整的热沉板未分割时更小的对角线。这些子热沉板的更小的热沉板对角线相对于衬底来说具有更小的切变应力(由于更小的绝对热差扩展),这导致达到比完整的热沉板更大的抗温度变化能力。
e.对于更大的运行流,多个模型包封的组件还可以通过加压烧结固定在一个热沉板上并且并联连接。还可以通过这种方式模拟常用的电路,例如B-6桥,并且共同地通过加压烧结技术固定在一个热沉板上。
f.但是如前所述,热沉板是管子或优化冷却的中空体,该管子或中空体可以由冷却介质流过,并且通过这种方式提高排热效率。必要时必须通过可取出的支撑体(例如方形管形式的方形杆)在加压烧结过程中防止主体的中空空间出现变形。
g.但是如f所述,热沉体的多个规划侧面,优选相对的平面被模型包封的组件根据加压烧结原理包围。从而例如方形管可以在两个相对的侧面上承载功率模块。
h.此外,一个共用的热沉板在一次烧结中可以配备多个组件,例如电并联的多个包封的功率电子器件。
附图标记列表
Figure BPA00001201277400071

Claims (7)

1.一种用于低温加压烧结至少一个待热接触并且机械固定连接的电子组件的方法,这些电子组件位于衬底上,该方法具有以下步骤:
-在用于热沉连接的衬底的连接平面暴露的情况下利用模型包封基体对电子组件进行模压,模型包封料的膨胀系数与热主导的陶瓷衬底匹配,
-提供热沉板,
-将烧结连接层施加在连接平面的暴露的区域上和/或施加在为了接触而设置的热沉板的区域上,以及
-借助银低温加压烧结技术将热沉板在连接平面的区域中材料锁定地连接到电子组件所位于的衬底,
其特征在于
为了产生可重现的凸状变形,在施加压力以扭曲热沉板时采用具有比热沉板更小的半径/外形尺寸的压制下冲头,使得在冷却了烧结连接之后热沉板的凸状的扭曲被最小化。
2.根据权利要求1所述的方法,其特征在于,为了将热沉板固定在突出衬底的区域中设置用于安装螺丝的通口,以便将边缘机械固定在其它散热的部件上。
3.根据上述权利要求之一所述的方法,其特征在于,多个单独的包封组件在一个共同的烧结步骤中烧结到一个共用的热沉板上。
4.根据权利要求1或2所述的方法,其特征在于,所述热沉板在所述衬底下面被分段。
5.根据权利要求1或2所述的方法,其特征在于,所述热沉板是管子或冷却中空体,冷却介质通过该管子或冷却中空体流动。
6.根据权利要求1或2所述的方法,其特征在于,形成热沉板并且有冷却介质流动的冷却中空体被支撑体防止在加压烧结过程中变形。
7.根据权利要求1或2所述的方法,其特征在于,形成热沉板并且有冷却介质流动的冷却中空体在其两个相对的侧面上承载功率模块。
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Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5996435B2 (ja) * 2010-11-22 2016-09-21 株式会社東芝 半導体モジュールおよび半導体モジュールの製造方法
DE102011076774A1 (de) * 2011-05-31 2012-12-06 Continental Automotive Gmbh Baugruppe mit einem Träger und einem Kühlkörper
DE102012208767A1 (de) * 2011-06-17 2012-12-20 Robert Bosch Gmbh Elektronische Schaltungsanordnung mit Verlustwärme abgebenden Komponenten
DE102011083911A1 (de) 2011-09-30 2013-04-04 Robert Bosch Gmbh Elektronische Baugruppe mit hochtemperaturstabilem Substratgrundwerkstoff
DE102012216401A1 (de) * 2012-09-14 2014-04-10 Powersem GmbH Halbleiterbauelement
US9295184B2 (en) * 2012-12-14 2016-03-22 GM Global Technology Operations LLC Scalable and modular approach for power electronic building block design in automotive applications
DE102013220591A1 (de) * 2013-10-11 2015-04-16 Robert Bosch Gmbh Leistungsmodul mit Kühlkörper
CN104867918A (zh) * 2014-02-26 2015-08-26 西安永电电气有限责任公司 塑封式ipm模块及其dbc板的固定结构
DE102014114093B4 (de) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh Verfahren zum Niedertemperatur-Drucksintern
DE102014114096A1 (de) 2014-09-29 2016-03-31 Danfoss Silicon Power Gmbh Sinterwerkzeug für den Unterstempel einer Sintervorrichtung
DE102014114097B4 (de) 2014-09-29 2017-06-01 Danfoss Silicon Power Gmbh Sinterwerkzeug und Verfahren zum Sintern einer elektronischen Baugruppe
DE102014114095B4 (de) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh Sintervorrichtung
DE102016107287A1 (de) * 2016-04-20 2017-11-09 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitereinrichtung und Verfahren zum Betrieb einer Leistungshalbleitereinrichtung
DE102019204683A1 (de) * 2019-04-02 2020-10-08 Volkswagen Aktiengesellschaft Verfahren und Vorrichtung zum stoffschlüssigen Verbinden mindestens eines Halbleitermoduls mit mindestens einem Gehäuseteil eines Kühlmoduls
JP7486234B2 (ja) 2020-05-15 2024-05-17 ピンク ゲーエムベーハー テルモジステーメ 電子アセンブリを接続するためのシステム
CN114608311A (zh) * 2022-01-24 2022-06-10 快克智能装备股份有限公司 烧结设备及其气氛可控的压力烧结机构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675474A (en) * 1994-07-15 1997-10-07 Mitsubishi Materials Corporation Highly heat-radiating ceramic package
CN1163962C (zh) * 1996-12-16 2004-08-25 国际商业机器公司 电子封装、封装组件及其制作方法和导热结构的制作方法
DE102005061772A1 (de) * 2005-12-23 2007-07-05 Danfoss Silicon Power Gmbh Leistungshalbleitermodul
DE102006009159A1 (de) * 2006-02-21 2007-08-23 Curamik Electronics Gmbh Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3780795A (en) * 1972-06-19 1973-12-25 Rca Corp Multilayer heat sink
EP0275433B1 (de) * 1986-12-22 1992-04-01 Siemens Aktiengesellschaft Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat, Folie zur Durchführung des Verfahrens und Verfahren zur Herstellung der Folie
EP0460286A3 (en) * 1990-06-06 1992-02-26 Siemens Aktiengesellschaft Method and arrangement for bonding a semiconductor component to a substrate or for finishing a semiconductor/substrate connection by contactless pressing
DE4233073A1 (de) * 1992-10-01 1994-04-07 Siemens Ag Verfahren zum Herstellen eines Halbleiter-Modulaufbaus
US6324069B1 (en) * 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US6784541B2 (en) * 2000-01-27 2004-08-31 Hitachi, Ltd. Semiconductor module and mounting method for same
JP3526788B2 (ja) * 1999-07-01 2004-05-17 沖電気工業株式会社 半導体装置の製造方法
JP3919398B2 (ja) * 1999-10-27 2007-05-23 三菱電機株式会社 半導体モジュール
DE10101086B4 (de) * 2000-01-12 2007-11-08 International Rectifier Corp., El Segundo Leistungs-Moduleinheit
DE20005746U1 (de) * 2000-03-28 2000-08-03 Danfoss Silicon Power Gmbh Leistungshalbleitermodul
DE10016129A1 (de) * 2000-03-31 2001-10-18 Siemens Ag Verfahren zum Herstellen einer wärmeleitenden Verbindung zwischen zwei Werkstücken
DE10062108B4 (de) 2000-12-13 2010-04-15 Infineon Technologies Ag Leistungsmodul mit verbessertem transienten Wärmewiderstand
DE10200372A1 (de) 2002-01-08 2003-07-24 Siemens Ag Leistungshalbleitermodul
JP2005109100A (ja) * 2003-09-30 2005-04-21 Mitsubishi Electric Corp 半導体装置およびその製造方法
DE102004019567B3 (de) * 2004-04-22 2006-01-12 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Befestigung von elektronischen Bauelementen auf einem Substrat
US7205177B2 (en) * 2004-07-01 2007-04-17 Interuniversitair Microelektronica Centrum (Imec) Methods of bonding two semiconductor devices
EP1950767B1 (en) * 2005-09-21 2012-08-22 Nihon Handa Co., Ltd. Pasty silver particle composition, process for producing solid silver, solid silver, joining method, and process for producing printed wiring board
DE102005061773B3 (de) * 2005-12-23 2007-05-16 Danfoss Silicon Power Gmbh Verfahren zum Herstellen eines Leistungshalbleitermoduls und Leistungshalbleitermodul
US7821130B2 (en) * 2008-03-31 2010-10-26 Infineon Technologies Ag Module including a rough solder joint

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5675474A (en) * 1994-07-15 1997-10-07 Mitsubishi Materials Corporation Highly heat-radiating ceramic package
CN1163962C (zh) * 1996-12-16 2004-08-25 国际商业机器公司 电子封装、封装组件及其制作方法和导热结构的制作方法
DE102005061772A1 (de) * 2005-12-23 2007-07-05 Danfoss Silicon Power Gmbh Leistungshalbleitermodul
DE102006009159A1 (de) * 2006-02-21 2007-08-23 Curamik Electronics Gmbh Verfahren zum Herstellen eines Verbundsubstrates sowie Verbundsubstrat

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特表2004-525503A 2004.08.19

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