CN101785098A - 微电子封装及其形成方法 - Google Patents

微电子封装及其形成方法 Download PDF

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CN101785098A
CN101785098A CN200880104459A CN200880104459A CN101785098A CN 101785098 A CN101785098 A CN 101785098A CN 200880104459 A CN200880104459 A CN 200880104459A CN 200880104459 A CN200880104459 A CN 200880104459A CN 101785098 A CN101785098 A CN 101785098A
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tube core
carrier
microelectronics packaging
encapsulant
radiator
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J·S·古扎克
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Intel Corp
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Abstract

一种微电子封装包括：载体(110，210，410，1110)，所述载体具有第一表面(111，211，411，1111)和相反的第二表面(112，212，412，1112)；粘合层(120，220，221，520，1220，1221)，所述粘合层位于所述载体的第一表面处；管芯(130，230，231，530，531，1230，1231)，通过所述粘合层将所述管芯附接到所述载体的第一表面；密封材料(140，240，640，1340)，所述密封材料位于所述载体的第一表面处且至少部分地围绕着所述管芯和所述粘合层；以及叠加层(150，250，750，1450)，所述叠加层与所述密封材料相邻，其中，所述管芯与所述叠加层彼此直接物理接触。在一个实施方式中，所述载体是散热器，所述散热器具有第一表面和第二表面，所述第二表面是所述微电子封装的顶部表面。

Description

微电子封装及其形成方法
技术领域
本发明的实施方式一般涉及微电子器件的封装，尤其涉及微电子器件的无凸块式叠加层(Bumpless Build-Up Layer，BBUL)封装。
背景技术
微电子封装技术(包括以机械或电的方式将硅管芯附接到基片或其它载体的方法)随时间的推移继续在改进和完善。目前广泛使用的封装技术被称为倒装芯片(或C4-可控坍塌芯片连接)技术，其中使用一组C4焊料凸块将管芯连接到其封装。然而，倒装芯片技术具有许多麻烦的问题，这些问题随着器件缩放的继续而越来越成问题。
无凸块式叠加层(BBUL)技术是解决这些问题中的某些问题的一种封装体系结构的方案。BBUL至少具有如下优点：BBUL不再需要组装；BBUL消除了倒装芯片互连(会产生更高的性能和更高的可靠性)；BBUL减小了因管芯-基片热膨胀系数(CTE)失配所导致的低k夹层电介质(ILD)上的应力；并且BBUL显著减小了封装电感(通过消除芯与倒装芯片互连而实现这一点)从而改进了输入/输出(I/O)和供电性能。
附图说明
结合附图来阅读下面的详细描述，会更好地理解所揭示的实施方式，在附图中：
图1是根据本发明一实施方式的微电子封装的横截面图；
图2是根据本发明另一实施方式的微电子封装的横截面图；
图3是根据本发明一实施方式的微电子封装的形成方法的流程图；
图4-9是根据本发明一实施方式在制造过程中各个特定点的微电子封装的横截面图；
图10是根据本发明一实施方式的微电子封装的形成方法的流程图；以及
图11-15是根据本发明一实施方式在制造过程中各个特定点的微电子封装的横截面图。
为了简单且清晰，附图示出了一般的构造方式，并且省去了公知的特征与技术的诸多描述和细节，为的是避免不必要地使本发明各实施方式变得模糊。另外，附图中的诸多元件并不必然按比例画出。例如，图中有些元件的大小可能相对于其它元件被夸大，为的是帮助理解本发明的各实施方式。在不同的图中，同一标号指代相同的元件。
在说明书和权利要求书中，术语“第一”、“第二”、“第三”、“第四”等被用于区分相似的元件，而并非必然地描述特定的序列或时间顺序。应该理解，如此使用的术语在合适的情况下是可互换的，使得本文所描述的各实施方式能够以不同于本文所描述或所示出的其它序列进行操作。相似的是，如果本文描述一种方法包括一系列步骤，则这些步骤所呈现的顺序并不必然是执行这些步骤的唯一顺序，某些申明的步骤有可能被省去，某些本文没有描述的步骤有可能被加入该方法。此外，术语“包括”、“具有”等旨在涵盖非排他性的包括，使得一种包括一系列元素的工艺、方法、物件或装置并不必然限于那些元素，而是可以包括未明确列出的或这种工艺、方法、物件或装置所固有的其它元素。
在说明书和权利要求书中，术语“左”、“右”、“前”、“后”、“顶部”、“底部”、“之上”、“之下”等都是用于描述目的，并不必然地描述相对的位置。应该理解，如此使用的术语在合适的情况下是可互换的，使得本文所描述的各实施方式能够以不同于本文所描述或所示出的其它序列进行操作。在本文中，术语“耦合”被定义为以电或非电的方式直接地或间接地连接。被描述成彼此“相邻”的物体可能是彼此物理接触的，彼此靠近的，或处于同一区域中，只要在其上下文中合适就可以。“在一个实施方式中”这一表述并不必然全是指同一实施方式。
具体实施方式
在本发明的一个实施方式中，一种微电子封装包括：具有第一表面和相反的第二表面的载体；在所述载体的第一表面处的粘合层；通过所述粘合层附接到所述载体的第一表面的管芯；在所述载体的第一表面处且至少部分地围绕着所述管芯和所述粘合层的密封材料；以及与所述密封材料相邻的叠加层，其中，所述管芯与所述叠加层彼此直接物理接触。
在相同的或另一个实施方式中，一种微电子封装包括：具有第一表面和第二表面的散热器(其中所述第二表面是所述微电子封装的顶部表面)；附接到所述散热器的第一表面的管芯；在所述散热器的第一表面处且至少部分地围绕着所述管芯的密封材料；以及叠加层，所述叠加层以物理的方式接触所述密封材料并且以物理和电学方式接触所述管芯。
本发明的各实施方式可以用倒装芯片封装的整体可缩放性解决某些当前问题以及预期的将来的问题，为的是满足将来CPU和芯片组性能与成本的诸多要求。本发明的各实施方式可以按照各种方式增强BBUL技术，其中包括：通过加入集成散热器(IHS)和/或薄管芯薄热界面材料(TIM)(常常缩写为TDTT)技术来增强热性能；通过集成无源组件(比如电容器、电阻器等)来增强电性能；通过使用注模密封剂来提高制造生产率；以及通过组合能提供更精细的电路形成设计规则的多个管芯与图案化技术来提高设计可缩放性。
现在参照附图，图1是根据本发明一实施方式的微电子封装100的横截面图。如图1所示，微电子封装100包括：载体110，所述载体110具有表面111和相反的表面112；粘合层120，所述粘合层120在所述载体110的表面111处；以及管芯130，通过所述粘合层120将所述管芯130附接到所述载体110的表面111。在至少一个实施方式中，表面112是微电子封装100的顶部表面。作为一个示例，管芯130可以是硅管芯等，其厚度约为400微米。作为另一个示例，管芯130可以是硅管芯等，其已被薄化处理到大约150微米厚，甚至大约75微米厚。其它厚度当然也是可能的。
微电子封装100还包括密封材料140，所述密封材料140在载体110的表面111处并且至少部分地围绕着管芯130和粘合层120，微电子封装100还包括与密封材料140相邻的至少一个叠加层150。像所有BBUL封装的情况一样，管芯130和叠加层150彼此直接物理接触。在至少一个实施方式中，微电子封装100包括多个叠加层150，这些叠加层150包括金属与电介质层(用通孔等连接)，能提供到管芯的连接(电能、接地、输入/输出等)。
在一个实施方式中，载体110包括导热材料和/或导电材料。在特定的实施方式中，载体110包括铜或其它材料制成的薄板，该薄板既导热有导电并且用作安装微电子封装100的载体。在相同的或另一个实施方式中，载体110也是微电子封装100的散热器。
在一个实施方式中，粘合层120包括热界面材料(TIM)，比如热油脂、弹性垫、相变材料、聚合物凝胶、焊料等。在另一个实施方式中，粘合层120包括可移除的粘合膜。作为示例，本实施方式中的粘合层120可以是由双轴取向聚对苯二甲酸乙二醇酯(boPET)聚酯膜(例如，可以从DuPont Teijin Films公司买到，名称是Melinex
Figure GPA00001035479200041
和Mylar
Figure GPA00001035479200042
)等制成的膜，这种膜响应于某些刺激会分解或失去粘合性，下文会对此作进一步的解释。可以施加这种膜以覆盖载体110的表面111的全部(或基本上全部)或仅仅覆盖一部分。应该理解，在后一种情况的实施方式中，在制造过程的某一时刻之后，粘合层120可能不存在于微电子封装100中(尽管图1中它还存在)。这种制造细节及其相应的结构方面的结果将在下文中更详细地讨论。
在一个实施方式中，多个管芯存在于微电子封装之内。在相同的或另一个实施方式中，一个或多个无源组件存在于微电子封装之内。图2是根据本发明的这一实施方式的微电子封装200的横截面图。如图2所示，微电子封装200包括：具有表面211和相反的表面212的载体210；在表面211处的粘合层220和221；分别通过粘合层220和221附接到表面211的管芯230和231；密封材料240，所述密封材料240在表面211处并且至少部分地围绕着管芯230和231以及粘合层220和221；以及与密封材料240相邻的至少一个叠加层250。作为示例，载体210、表面211、表面212、粘合层220和221、管芯230和231、密封材料240以及叠加层250可以分别相似于载体110、表面111、表面112、粘合层120、管芯130、密封材料140和叠加层150。
尽管图2仅描绘了两个管芯(管芯230和231)，但是在其它实施方式中，微电子封装200(或另一个微电子封装)可以包括不止两个管芯。微电子封装200还包括至少一个无源组件260，也如图2所示那样。如图所示，无源组件260(可以是电容器、电阻器、电感器等)可以被附接到表面211，并且至少部分地被密封材料240围绕着。除了无源组件260以外，微电子封装200(或另一个微电子封装)可以包括在叠加层250中的集成的薄膜电容器等(未示出)。
图3是根据本发明一实施方式的微电子封装的形成方法300的流程图。方法300的步骤310是提供载体。作为示例，该载体可以与图1所示载体110相似。作为另一个示例，该载体可以与图4第一次所示载体410相似，图4是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图。在一个实施方式中，图4描绘了可以在执行步骤310之后出现的微电子封装400。如图4所示，载体410具有表面411和相反的表面412。
方法300的步骤320是将管芯附接到所述载体。作为示例，该管芯可以与图1所示管芯130相似。作为另一个示例，该管芯可以与图5第一次所示管芯530相似，图5是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图。在一个实施方式中，图5描绘了可以在执行步骤320之后出现的微电子封装400。
在一个实施方式中，步骤320包括：将粘合膜加到管芯或载体上(或同时加到管芯和载体上)；然后，使管芯和载体彼此物理接触，使得在管芯和载体之间形成粘合键。作为示例，该粘合膜可以是这样一种膜，它分解或者可以弱化到足以剥落或者从它所附接的管芯和/或载体上剥离。如图5所示，已用粘合膜520将管芯530附接到载体410上，粘合膜520可以相似于上文结合步骤320提及的粘合膜。图5也描绘了管芯531，它可以相似于管芯530，由此示出了可以在单个封装中同时处理两个(或不止两个)管芯。这些管芯可以随后被分离成单个的，以提高制造生产率。在不同的实施方式中，一次可以处理一个管芯。
方法300的步骤330是用密封材料来密封管芯的至少一部分。作为一个示例，密封材料可以相似于图1所示的密封材料140。作为另一个示例，该密封材料可以与图6第一次所示密封材料640相似，图6是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图。在一个实施方式中，图6描绘了可以在执行步骤330之后出现的微电子封装400。
方法300的步骤340是形成与密封材料相邻的至少一个叠加层。作为一个示例，叠加层可以相似于图1所示的叠加层150。作为另一个示例，该叠加层可以与图7第一次所示叠加层750相似，图7是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图。在一个实施方式中，图7描绘了可以在执行步骤340之后出现的微电子封装400。在一个实施方式中，作为叠加过程的一部分，步骤340包括在叠加层中形成集成薄膜电容器(未示出)。
方法300的步骤350是除去载体，由此形成露出管芯的封装。相应地，方法300可以被用于最终产品不需要散热器的实施方式中。或者，该工艺流程可以与后-分离IHS附接一起使用，如果以这种方式制造产品有优点的话。
在一个实施方式中，步骤350包括除去在管芯与载体之间的粘合键。作为一个示例，除去粘合键可以包括向粘合键施加热辐射、紫外辐射等，直到粘合键被剥离。图8是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图，图8描绘了可以在执行步骤350之后出现的微电子封装400。应该理解，产生粘合键的粘合膜相对于管芯而言是非常薄的，使得管芯背面与密封材料之间的实际间隙是很小的。该间隙应该很容易被下一层热界面材料填充。然而，上述工艺流程中可以包括任选的平整化步骤，为的是确保这两个表面的平整性。
方法300的步骤360是将散热器附接到管芯的表面，如果需要或想要散热器的话。在一个实施方式中，通过使用管芯背面的TIM(焊料、聚合物等)，并且通过使用在管芯之外的区域中的密封材料顶部与散热器之间的非导电粘合剂，来附接散热器。作为一个示例，该散热器可以与图9第一次所示散热器970相似，图9是根据本发明一实施方式的制造过程中特定时刻的微电子封装400的横截面图。在一个实施方式中，步骤360可以省去，使得微电子封装400不包括散热器，适用于不需要或不想要散热器的应用。
方法300的步骤370是将无源组件附接到载体上，使得无源组件与管芯一起被密封材料至少部分地密封住。作为一个示例，无源组件可以相似于图2所示的无源组件260。作为另一个示例，无源组件可以相似于图9第一次所示的无源组件960。在一个实施方式中，图9描绘了可以在执行步骤370之后出现的微电子封装400。作为一个示例，可以用与粘合层120中的粘合剂相似的粘合剂(未示出)将无源组件960附接到散热器970。
如果在所示的实施方式中同时处理多个管芯，则步骤370之后可以跟着一个用于将这些多管芯面板分离成单个单元的处理过程。这些部件可以接下来经历合适的后端处理步骤，以使它们成为球栅格阵列(BGA)、平面栅格阵列(LGA)或引脚栅格阵列(PGA)组件。
图10是根据本发明一实施方式的微电子封装的形成方法1000的流程图。方法1000的步骤1010是提供散热器。作为示例，该散热器可以与图1所示载体110相似。作为另一个示例，该散热器可以与图11第一次所示散热器1110相似，图11是根据本发明一实施方式的制造过程中特定时刻的微电子封装1100的横截面图。在一个实施方式中，图11描绘了可以在执行步骤1010之后出现的微电子封装1100。如图11所示，散热器1110具有表面1111和相反的表面1112。
方法1000的步骤1020是将管芯附接到所述散热器。作为示例，该管芯可以与图1所示管芯130相似。作为另一个示例，该管芯可以与图12第一次所示管芯1230相似，图12是根据本发明一实施方式的制造过程中特定时刻的微电子封装1100的横截面图。在一个实施方式中，图12描绘了可以在执行步骤1020之后出现的微电子封装1100。图12也描绘了管芯1231，它可以相似于管芯1230，由此示出了可以在单个封装中同时处理两个(或不止两个)管芯。这些管芯可以随后被分离成单个的，以提高制造生产率。在不同的实施方式中，一次可以处理一个管芯。
在一个实施方式中，步骤1020包括：将TIM加到管芯与散热器中的至少一个上；接下来使管芯与散热器彼此物理接触，使得在管芯与散热器之间形成粘合键。在其它实施方式中，以某种其它方式实现步骤1020，比如，通过使用热固化粘合剂、焊料等来实现步骤1020。作为一个示例，上述TIM可以相似于图12所示定位的TIM 1220，由此在散热器1110与管芯1230之间产生粘合键。
在特定的实施方式中，TIM 1220是TIM预成型坯。在相同的或另一个实施方式中，TIM 1220是薄TIM，在与上述类型的薄化管芯相结合时，形成了薄管芯/薄TIM(TDTT)封装环境的一部分。如图12所示，微电子封装1100还包括TIM 1221，它可以相似于TIM 1220，由此在散热器1110和管芯1231之间产生粘合键。
方法1000的步骤1030是用密封材料来密封管芯的至少一部分。作为一个示例，密封材料可以相似于图1所示的密封材料140。作为另一个示例，该密封材料可以与图13第一次所示密封材料1340相似，图13是根据本发明一实施方式的制造过程中特定时刻的微电子封装1100的横截面图。在一个实施方式中，图13描绘了可以在执行步骤1030之后出现的微电子封装1100。在一个实施方式中，步骤1030包括：通过使用传递模塑工艺、压缩模塑工艺、注射模塑工艺等中的一种，来施加上述密封材料。这些和其它模塑工艺中的一种或多种可以使微电子封装1100(以及根据本发明的其它微电子封装)的成本更低且生产率更高。
方法1000的步骤1040是形成与密封材料相邻的至少一个叠加层。作为一个示例，叠加层可以相似于图1所示的叠加层150。作为另一个示例，该叠加层可以与图14第一次所示叠加层1450相似，图14是根据本发明一实施方式的制造过程中特定时刻的微电子封装1100的横截面图。在一个实施方式中，图14描绘了可以在执行步骤1040之后出现的微电子封装1100。
在一个实施方式中，步骤1040包括通过使用下列工艺技术使叠加层图案化：半加成图案化工艺；激光投影图案化(LPP)工艺；等离子体蚀刻工艺；液体抗蚀工艺；溅射工艺；或其它先进的细线图案化技术。如果期望的话，可以使用不止一个这样的技术。在相同的或其它实施方式中，步骤1040包括将集成的薄膜电容器嵌入到微电子封装中。
方法1000的步骤1050是将无源组件附接到散热器上，使得无源组件与管芯一起被密封材料至少部分地密封住。作为一个示例，无源组件可以相似于图2所示的无源组件260。作为另一个示例，该无源组件可以与图15第一次所示无源组件1560相似，图15是根据本发明一实施方式的制造过程中特定时刻的微电子封装1100的横截面图。在一个实施方式中，图15描绘了可以在执行步骤1050之后出现的微电子封装1100。作为一个示例，可以用与粘合层120中的粘合剂相似的粘合剂(未示出)将无源组件1560附接到散热器1110。
如果在所示的实施方式中同时处理多个管芯，则步骤1050之后可以跟着一个用于将这些多管芯面板分离成单个单元的处理过程。这些部件可以接下来经历合适的后端处理步骤，以使它们成为球栅格阵列(BGA)、平面栅格阵列(LGA)或引脚栅格阵列(PGA)组件。
尽管已参照具体的实施方式对本发明进行了描述，但是本领域技术人员应该理解，在不背离本发明的精神和范围的情况下可以作出各种改变。相应地，本发明各实施方式的揭示旨在示出本发明的范围，而非用于限制。本发明的范围仅由权利要求书来限定。例如，对于本领域普通技术人员而言，很明显的是，本文所讨论的微电子封装和相关方法可以按各种实施方式进行实现，上文所讨论的这些实施方式并不必然代表完全描述了所有可能的实施方式。
另外，结合具体实施方式描述了诸多益处、其它优点和解决方案。然而，诸多益处、优点、解决方案以及可能导致任何益处、优点等的元素并不被解释为关键的、必需的或必不可少的特征或元素。
此外，本文所揭示的实施方式和限定特征在下列情况下不被公之于众：(1)该实施方式和/或限定特征没有被明确写入权利要求；以及(2)该实施方式和/或限定特征是权利要求书中的元素和/或限定特征的等价方案。

Claims (24)

1.一种微电子封装，包括：
具有第一表面和相反的第二表面的载体；
在所述载体的第一表面处的粘合层；
通过所述粘合层附接到所述载体的第一表面的管芯；
在所述载体的第一表面处且至少部分地围绕着所述管芯和所述粘合层的密封材料；以及
与所述密封材料相邻的叠加层，
其中，所述管芯与所述叠加层彼此直接物理接触。
2.如权利要求1所述的微电子封装，其特征在于，
所述载体包括导热材料。
3.如权利要求2所述的微电子封装，其特征在于，
所述载体包括导电材料。
4.如权利要求1所述的微电子封装，其特征在于，
所述粘合层包括热界面材料。
5.如权利要求4所述的微电子封装，其特征在于，
所述热界面材料包括热油脂、弹性垫、相变材料、聚合物凝胶和焊料之一。
6.如权利要求1所述的微电子封装，其特征在于，
所述粘合层包括可移除的粘合膜，所述可移除的粘合膜基本上覆盖所述载体的第一表面的全部。
7.如权利要求1所述的微电子封装，还包括：
无源组件，所述无源组件被附接到所述载体的第一表面并且至少部分地被所述密封材料围绕着。
8.如权利要求1所述的微电子封装，还包括：
位于所述叠加层中的集成薄膜电容器。
9.一种微电子封装，包括：
具有第一表面和第二表面的散热器，其中所述第二表面是所述微电子封装的顶部表面；
附接到所述散热器的第一表面的管芯；
位于所述散热器的第一表面处的密封材料，所述密封材料至少部分地围绕着所述管芯；以及
叠加层，所述叠加层以物理的方式接触所述密封材料并且以物理和电学方式接触所述管芯。
10.如权利要求9所述的微电子封装，还包括：
位于所述管芯和所述散热器的第一表面之间的热界面材料。
11.如权利要求10所述的微电子封装，还包括：
无源组件，所述无源组件被附接到所述散热器并且至少部分地被所述密封材料围绕着。
12.如权利要求11所述的微电子封装，还包括：
位于所述叠加层中的集成薄膜电容器。
13.一种用于形成微电子封装的方法，所述方法包括：
提供一载体；
将管芯附接到所述载体；
用密封材料将所述管芯的至少一部分密封住；
形成与所述密封材料相邻的叠加层；以及
除去所述载体。
14.如权利要求13所述的方法，其特征在于，
将所述管芯附接到所述载体包括：
将粘合膜加到所述管芯与所述载体中的至少一个上；以及
使所述管芯与所述载体彼此物理接触，使得在所述管芯和所述载体之间形成粘合键。
15.如权利要求14所述的方法，其特征在于，
除去所述载体包括除去所述管芯与所述载体之间的粘合键。
16.如权利要求15所述的方法，其特征在于，
除去所述粘合键包括向所述粘合键施加热辐射和紫外辐射之一。
17.如权利要求13所述的方法，还包括：
将散热器附接到所述管芯的表面。
18.如权利要求13所述的方法，还包括：
将无源组件附接到所述载体，使得所述无源组件与所述管芯一起被所述密封材料至少部分地密封住。
19.如权利要求13所述的方法，其特征在于，
形成叠加层包括在所述叠加层中形成集成薄膜电容器。
20.一种用于形成微电子封装的方法，所述方法包括：
提供散热器；
将管芯附接到所述散热器；
用密封材料将所述管芯的至少一部分密封住；以及
形成与所述密封材料相邻的叠加层。
21.如权利要求20所述的方法，其特征在于，
将所述管芯附接到所述散热器包括：
将热界面材料加到所述管芯与所述散热器中的至少一个上；以及
使所述管芯与所述散热器彼此物理接触，使得在所述管芯和所述散热器之间形成粘合键。
22.如权利要求21所述的方法，还包括：
将无源组件附接到所述散热器，使得所述无源组件与所述管芯一起被所述密封材料至少部分地密封住。
23.如权利要求20所述的方法，其特征在于，
将所述管芯的至少一部分密封住包括：
通过使用传递模塑工艺、压缩模塑工艺和注射模塑工艺之一，来施加所述密封材料。
24.如权利要求20所述的方法，其特征在于，
形成叠加层包括通过使用下列工艺中的至少一种使所述叠加层图案化：半加成图案化工艺；激光投影图案化工艺；等离子体蚀刻工艺；液体抗蚀工艺；以及溅射工艺。
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