CN101933129B - 电子元件装置的制造方法 - Google Patents

电子元件装置的制造方法 Download PDF

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Publication number
CN101933129B
CN101933129B CN2008801261410A CN200880126141A CN101933129B CN 101933129 B CN101933129 B CN 101933129B CN 2008801261410 A CN2008801261410 A CN 2008801261410A CN 200880126141 A CN200880126141 A CN 200880126141A CN 101933129 B CN101933129 B CN 101933129B
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electronic component
electrode
metal nanoparticle
resin
slurry
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CN101933129A (zh
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舟木达弥
久米宗一
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
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Abstract

提供一种制造将芯片元件等安装在布线基板上的电子元件装置的方法，该方法生产效率高、能够降低成本、具有稳定的产品质量。把金属纳米粒子浆(1)施加在基板侧电极(23)上；在布线基板(22)和芯片元件(26)对好位置的状态下，施加负荷(30)，由此使金属纳米粒子浆(1)一直压缩变形到压缩变形极限厚度(31)；接着，加热金属纳米粒子浆(1)，由此得到烧结好金属纳米粒子的接合烧结体(6)，从而将基板侧电极(23)与芯片侧电极(27)相互接合在一起。

Description

电子元件装置的制造方法
技术领域
本发明涉及由各个电极相互接合起来的多个电子元件构成的电子元件装置的制造方法，特别是涉及为了电极间的接合而使用含有金属纳米粒子的金属纳米粒子浆的电子元件装置的制造方法。
背景技术
近年来，随着电子机器的小型化，对半导体封装件的高集成化的要求越发强烈起来。把半导体封装件安装并固定到布线基板上实现电气导通的安装技术中，更需要高集成度且高密度的产品。
因此，在半导体封装件的整个背面上把锡珠排列成栅格状的所谓按照BGA(Ball GridArray)的接合方式受到关注，并且付诸实用。如上所述，由于该BGA方式的半导体封装件把电极配置在整个里面，所以能够容易地增加半导体封装件的单位面积的电极数，结果，对高密度安装或安装面积的缩小能够发挥很好的效果。
但是，在采用BGA方式的情况下，随着锡珠的排列节距的窄小化，搪锡时容易产生所谓锡桥，从而容易发生电极间的短路。可以说，在把焊锡加热暂时熔融并液化后再经冷凝的过程而进行接合的微焊中，这是不可避免的现象。
在把多个必要的电子元件接合起来制造一个电子元件装置时，每次重复进行电子元件的接合，都要顺次使用熔点更低的焊锡，也就是进行所谓分步焊接，在进行这种分步焊接的情况下，第一步焊接时必须用高温焊锡。作为这种高温焊锡的实用材料例如有Pb-5Sn系焊锡，但是随着当今环保的要求，对Pb使用的限制越来越严格，迫切需要开发替代材料。
为解决上述课题，例如在特开平9-326416号公报(专利文献1)和特开2004-128357号公报(专利文献2)中就提出了一种方案，使用图10示意性地示出了组分的金属纳米粒子浆来作为接合材料，以取代上述的焊锡。
参照图10，金属纳米粒子浆1包含平均粒径1～100nm的金属纳米粒子2、分散剂3和分散媒质4。更具体地说，金属纳米粒子2例如由Au、Ag、Cu之类的导电性金属构成；分散剂3是可与构成金属纳米粒子2的金属元素配位的材料，覆盖金属纳米粒子2，例如可以用胺类、醇类、硫醇类材料作为分散剂3；分散媒质4稳定地分散由分散剂3覆盖的金属纳米粒子2，例如可以采用甲苯、二甲苯、松油醇、矿质松节油、癸醇、十四烷等有机溶剂。虽未图示，但是金属纳米粒子浆1也可以包含特开2002-299833号公报(专利文献3)中记载的那种粘结剂成分或还原剂等添加物。
如果采用上述的金属纳米粒子浆，由于不是像使用焊锡的情况那样把焊锡暂时熔融后再凝固来进行焊接，所以不易再出现前述的随着锡珠的排列节距的窄小化而在搪锡时容易产生锡桥以及发生电极间短路的问题；如果采用金属纳米粒子浆，就不必使用不符合环保要求的Pb；如果采用金属纳米粒子浆，能够在100～300℃这样较低的温度下来烧结金属纳米粒子而形成接合部，在达到构成金属纳米粒子的金属的熔点之前，暂时烧结好的金属纳米粒子的烧结体一直保持其形态。
因此，如果使用金属纳米粒子浆，能够减轻环境负担，同时仅仅用一种金属纳米粒子浆就能够无放心地反复实施相当于所谓分步锡焊的电子元件的接合。
下面说明使用上述的金属纳米粒子浆实施倒装式接合所得到的电子元件的制造方法之一例。
首先，如图11(1)所示，准备布线基板11；在布线基板11上形成几个基板侧电极12和保护膜13。保护膜13的一部分搭在基板侧电极12的周缘部上，这样，就在基板侧电极12的周围形成围堰14。在基板侧电极12上施加金属纳米粒子浆1。
另一方面，如图11(2)所示，准备要倒装式接合在布线基板11上的芯片元件15。芯片元件15具有分别电气连接至前述的基板侧电极12上的几个芯片侧电极16，在芯片元件15的形成芯片侧电极16的面上形成钝化膜17。钝化膜17的一部分搭在芯片侧电极16的周缘部上，由此，在芯片侧电极16的周围形成围堰18。
然后，如图11(2)所示，在将金属纳米粒子浆1置入布线基板11与芯片元件15之间的状态下，使布线基板11与芯片元件15相互对好位置，从而使基板侧电极12和相关联的芯片侧电极16相互面对。
然后，如图11(3)所示，例如从芯片元件15侧施加负荷19。由此使金属纳米粒子浆1压缩变形。
接下来，实施加热工序。由此，把含在金属纳米粒子浆1内的分散剂3和分散媒质4等除掉，同时，烧结金属纳米粒子2(参照图10)。结果，如图11(4)所示，形成来自金属纳米粒子浆1的接合烧结体6，用该接合烧结体6把基板侧电极12与芯片侧电极16相互接合起来。
这样，就得到了要制造的电子元件装置20。
但是，在上述的电子元件装置20的制造方法中，存在如下要解决的课题。
首先，与使用锡珠的情况不同，为了调整电子元件装置20中的接合烧结体6的高度，在图11(3)的工序中必须调整金属纳米粒子浆1的高度。为了高精度地进行这样的接合烧结体6高度的调整，就必须高精度地控制负荷19。但是，提高负荷19的精度与提高芯片元件15的装载节奏存在权衡的关系，提高负荷19的精度时，会导致生产效率下降和成本提高。
在布线基板11上常常会产生弯曲起伏，在多个基板侧电极12之间有可能产生高度的离散。这种情况下，一旦金属纳米粒子浆1的施加厚度不够，在图11(3)的工序中，处于最高位置的基板侧电极12上能够得到良好的接合状态，而处于最低位置的基板侧电极12上就达不到充分的接合状态。
专利文献1：特开平9-326416号公报
专利文献2：特开2004-128357号公报
专利文献3：特开2002-299833号公报
发明内容
因此，本发明的目的在于提供一种能够解决上述课题的电子元件装置的制造方法。
本发明是一种电子元件装置的制造方法，具备如下工序：准备具有第一电极的第一电子元件和具有第二电极的第二电子元件；准备含有平均粒径1～100nm的金属纳米粒子、分散剂和分散媒质的金属纳米粒子浆；在第一电极和第二电极的至少一方上施加金属纳米粒子浆的赋浆工序；在将金属纳米粒子浆置入在第一电子元件和第二电子元件间的状态下，使第一电子元件和第二电子元件相互对好位置，从而使第一电极和第二电极相互面对；在使第一电子元件和第二电子元件相互接近的方向上施加负荷，从而使处于第一电极和第二电极间的金属纳米粒子浆压缩变形；然后，在高于能够除掉含在金属纳米粒子浆内的分散剂和分散媒质的温度而低于构成金属纳米粒子的金属的熔点温度下，进行加热，来烧结金属纳米粒子，由此使第一电极和第二电极相互接合。为了解决上述的技术课题，本发明的特征在于具备如下构成。
即，本发明在使处于第一电极和第二电极间的金属纳米粒子浆压缩变形的工序中，将金属纳米粒子浆一直压缩变形到压缩变形极限厚度。
第一电子元件具有多个第一电极；第二电子元件具有多个第二电极；在使第一电子元件和第二电子元件相互对好位置时，相互面对的各第一电极和第二电极的间隔不全相等的情况下，在赋浆工序中所施加的金属纳米粒子浆的厚度最好大于或等于压缩变形极限厚度加上间隔的最大值与最小值之差。
最好在第一电极的周围和/或第二电极的周围形成用来防止金属纳米粒子浆扩散的围堰。
本发明的电子元件装置的制造方法还具备如下工序：准备层压密封用的未硬化状态的片状树脂；在使第一电极和第二电极相互接合的工序后，用未硬化状态的片状树脂覆盖第一电子元件和第二电子元件的任一方；对未硬化状态的片状树脂朝第一电子元件和第二电子元件加压；使未硬化状态的片状树脂硬化。
上述的情况下，片状树脂含有粒径都等于或小于规定尺寸的填料，在对未硬化状态的片状树脂加压的工序中，最好对片状树脂控制加压，以使覆盖第一电子元件和第二电子元件的任一方的片状树脂的最薄部分的厚度取决于填料的粒径。
本发明的电子元件装置的制造方法还具备如下工序：准备底部填充密封用的未硬化状态的树脂；在使第一电极和第二电极相互接合的工序后，把未硬化状态的树脂施加到第一电子元件和第二电子元件中面积较小的一方的至少周围；使未硬化状态的树脂硬化。
发明的有益效果
按照本发明，在使第一电子元件和第二电子元件相互接近的方向上施加负荷，从而使处于第一电极和第二电极间的金属纳米粒子浆压缩变形的工序中，由于将金属纳米粒子浆一直压缩变形到压缩变形极限厚度，所以就不必进行高精度的负荷控制。因此，能够提高该压缩变形工序的效率，结果，能够提高电子元件装置的生产性，并能够降低成本。
在上述的压缩变形工序中，由于将金属纳米粒子浆一直压缩变形到压缩变形极限厚度，所以能够最大限度地降低烧结金属纳米粒子所得到的接合烧结体的高度。结果，能够实现电子元件装置的低高度化。
在压缩变形工序中，由于将金属纳米粒子浆一直压缩变形到压缩变形极限厚度，所以在该工序结束时，金属纳米粒子浆的密度就呈最高的状态。因此，能够把加热金属纳米粒子浆而得到的接合烧结体做得强度高且阻抗低。结果，能够得到在第一电极和第二电极间形成了强度高且阻抗低的接合部的电子元件装置。
在本发明中，即使像在装载芯片构件的布线基板侧存在弯曲或起伏那样，在使第一电子元件与第二电子元件相互对齐位置时，相互面对的各个第一电极与各个第二电极之间的各个间隔存在互不相等的情况下，如果在赋浆工序中施加的金属纳米粒子浆的厚度为压缩变形极限厚度加上上述间隔的最大值与最小值之差，在全部第一电极与第二电极之间就能够确实地得到良好的接合状态。
如果在第一电极的周围和/或第二电极的周围形成用来防止金属纳米粒子浆扩散的围堰，在压缩变形工序中，就能够容易且确实地把金属纳米粒子浆一直压缩变形到压缩变形极限厚度。
按照本发明，由于将金属纳米粒子浆一直压缩变形到压缩变形极限厚度，所以在该压缩变形时即使承受的负荷存在离散，这种离散也不会影响构成接合部的接合烧结体的高度，因此，能够使第一电子元件与第二电子元件的间隔无离散。
由于上述的优点提高了第一电子元件与第二电子元件之间的接合可靠性和耐湿性，所以在实施底部填充密封的情况下，上述的优点带来如下的优点。在实施底部填充密封的情况下，要求底部填充密封用的树脂挤出量更少。影响该树脂的挤出量的因素是第一电子元件与第二电子元件的间隔和树脂的供给量。按照本发明，如上所述，由于第一电子元件与第二电子元件的间隔稳定，所以为了减少树脂的挤出量，只要进行树脂的供给量的控制就可以，结果，容易减少树脂的挤出量。
在本发明中，在层压密封电子元件的情况下，对未硬化状态的片状树脂进行加压，但是如果控制对片状树脂的加压，以使覆盖第一电子元件和第二电子元件的任一方的片状树脂的最薄部分的厚度取决于包含在片状树脂内的填料的粒径，这就容易高精度控制在使片状树脂硬化阶段得到的电子元件的高度。
附图说明
图1是为说明本发明的第一实施方式而依次表示制造电子元件装置21的工序的说明图。
图2是用来说明构成本发明的特征的金属纳米粒子浆的压缩变形极限厚度而表示负荷与金属纳米粒子浆的高度的关系的示图。
图3与图2一样，是用来说明压缩变形极限厚度而表示金属纳米粒子浆的高度与直径的关系的示图。
图4表示本发明的第二实施方式的电子元件装置34，相当于图1(4)。
图5表示本发明的第三实施方式的电子元件装置38，相当于图1(4)。
图6是为了形成图5所示的电子元件装置38所具备的层压树脂39而实施的工序的示图。
图7是把相当于图5的部分A的部分放大的示图，是图解包含在构成为层压树脂39的未硬化状态的片状树脂40内的填料43的示图。
图8表示本发明的第四实施方式的电子元件装置46，相当于图1(4)。
图9是用来说明本发明的第五实施方式的相当于图1的示图。
图10是示意性表示本发明中所用的金属纳米粒子浆1的放大断面图。
图11是与本发明相关的现有的电子元件装置的制造方法的示图。
【符号的说明】
1…金属纳米粒子浆
2…金属纳米粒子
3…分散剂
4…分散媒质
6…接合烧结体
21、34、38、46、58…电子元件装置
22、51…布线基板(第一电子元件)
23、53a、53b、53c…基板侧电极(第一电极)
25、29…围堰
26、52…芯片元件(第二电子元件)
27、54a、54b、54c…芯片侧电极(第二电极)
30…负荷
31、57…压缩变形极限厚度
39…层压树脂
40…片状树脂
41…压辊
43…填料
47…底部填充树脂
55a、55b、55c…电极间的间隔
56…金属纳米粒子浆的施加厚度
具体实施方式
图1是本发明的第一实施方式的说明图。图1中示出电子元件装置的制造方法中包含的代表性的工序，图1(4)中表示所得到的电子元件装置21。
首先，如图1所示，准备作为第一电子元件的布线基板22。布线基板22例如由玻璃环氧树脂基板等树脂基板、氧化铝等烧结基板、Si基板等构成。在布线基板22的上表面形成有几个基板侧电极23，在布线基板22的上面大体整个面上形成有保护膜24。保护膜24的一部分搭在基板侧电极23的周缘部上，由此在基板侧电极23的周围形成围堰25。该围堰25用来防止后述的金属纳米粒子浆1的扩散。
基板侧电极23既可以是由如Au、Ag、Cu等构成的单层结构，也可以是由如Cu/Ni/Au等构成的多层结构。基板侧电极23的宽度方向尺寸约为10～150μm，厚度约为5～50μm。基板侧电极23也可以由沿布线基板22的厚度方向延伸的通路导体的端面露出来而构成。
另一方面，如图1(2)所示，准备作为第二电子元件的芯片元件26。芯片元件26例如是半导体元件或表面弹性波元件等小型元件。在该图中的下表面上，对应于各个基板侧电极23，形成有几个芯片侧电极27。芯片元件26的形成了芯片侧电极27的面的大体整个面形成有钝化膜28，钝化膜28的一部分搭在芯片侧电极27的周缘部上，由此在芯片侧电极27的周围形成围堰29。围堰29与前述的围堰25一样，用来防止金属纳米粒子浆1的扩散。
芯片侧电极27例如由Al、Al合金(含有90％以上的Al，也可以添加Cu或Si。)、Au、Cu构成，其厚度约为0.5～2μm。
另外，准备前述的图10所示的金属纳米粒子浆1。包含在金属纳米粒子浆1中的金属纳米粒子2例如由Au、Ag、Cu、Ni等金属构成，或者例如也可以由Cu核Au壳、Cu核Ag壳之类的两种以上的金属构成。作为分散剂3，只要是具有低于构成金属纳米粒子2的金属的熔点的低沸点且能够与金属接合的有机物就可以，例如，可以采用胺、醇、苯酚、硫醇等。作为分散媒质4，只要是具有低于构成金属纳米粒子2的金属的熔点的低沸点物质就可以，例如可以采用甲苯、二甲苯、松油醇、矿质松节油、癸醇、十四烷等有机溶剂。或者也可以采用水之类的水系物质作为分散媒质4。金属纳米粒子浆1还可以含有少量的有机粘合剂，为了加入分散剂3也可以含有酸酐那样的俘获材料，对于电极材料，也可以含有具有还原作用的物质。
如图1(1)所示，在基板侧电极23上施加金属纳米粒子浆1，可以采用喷墨或分配器的吐出供给、丝网印刷、复制等种种供给方法来供给金属纳米粒子浆。当然，金属纳米粒子浆1的供给量只要是超过埋住要相互接合的基板侧电极23与芯片侧电极27之间的间隙所必要的量、而少于基板侧电极23的各相邻电极之间以及芯片侧电极27的各相邻电极之间连起来的量就可以。
为了提高生产效率，布线基板22也可以先在集合基板的状态下实施上述的工序和以下的工序，该集合基板在后面将通过分割而能够得到多个布线基板22。如上所述，金属纳米粒子浆1既可以不施加在基板侧电极23上而施加在芯片侧电极27上，也可以在基板侧电极23上和芯片侧电极27上都施加金属纳米粒子浆1。
然后，如图1(2)所示，在将金属纳米粒子浆1置入在两者之间的状态下，使布线基板22与芯片元件26相互对好位置，以使基板侧电极23和与其对应的芯片侧电极27相互面对，可以使用与原来的倒装芯片式安装方法同样的方法来实施该对位工序。
接下来，如图1(3)所示，在使布线基板22与芯片元件26相互接近的方向上施加负荷30，由此来实施使处在基板侧电极23和芯片侧电极27之间的金属纳米粒子浆1压缩变形的工序。把该压缩变形工序中施加的负荷30的大小取为能使金属纳米粒子浆1的压缩变形达到极限的大小，由此，金属纳米粒子浆1就被一直压缩变形到压缩变形极限厚度31。以下更具体地说明该压缩变形极限厚度31。
就一处接合部而言，对金属纳米粒子浆施加的负荷与因负荷而压缩变形的金属纳米粒子浆的高度的关系示于图2和表1上。
[表1]
Figure BPA00001189009300081
在图2和表1中，例1、例2和例3是使金属纳米粒子浆的供给量不同的例子，供给量存在例1＜例2＜例3的关系。
由图2和表1所示的数据可知，负荷增大时，例1～例3的金属纳米粒子浆的高度都降低，其值饱和。例如，在例1的情况下，就一处金属纳米粒子浆而言，如果负荷达到或超过0.9N，金属纳米粒子浆的高度就为定值；在例2和例3的情况下，就一处金属纳米粒子浆而言，如果负荷达到或超过1.5N，金属纳米粒子浆的高度就为定值。由此可知，施加规定值以上的负荷，即使不控制负荷的上限值，也能够把金属纳米粒子浆的高度控制为定值。
这里，说明用规定值以上的负荷就能够使金属纳米粒子浆的高度为定值的原因，即压缩变形达到极限的原因。图3是所施加的金属纳米粒子浆的高度与直径的关系的示图。由图3可知，如果降低金属纳米粒子浆的高度，金属纳米粒子浆的直径就急剧增大。这种情况表示在增大负荷的过程中，直径随着金属纳米粒子浆的压缩变形而急剧增大，而压缩变形并不继续进展。
再参照图1(3)，例如采用原来的倒装芯片式安装器那样的一般的安装器来提供负荷30。通常是像图示的那样从芯片元件26侧施加负荷30，但是只要能够使金属纳米粒子浆1压缩变形，就既可以从布线基板22侧施加负荷，也可以从芯片元件26和布线基板22双方来施加。
然后实施加热工序。由于即使去除了负荷30也维持着使前述的金属纳米粒子浆1压缩变形后的状态，所以在该加热工序中就不必施加负荷30。在加热工序中，是在高于能够除掉金属纳米粒子浆1内含有的分散剂3和分散媒质4的温度而低于构成金属纳米粒子2的金属的熔点的温度下进行加热。例如，选择100～300℃的温度和1～60分钟的时间的加热条件。通过该加热来烧结金属纳米粒子2，如图1(4)所示，金属纳米粒子浆1形成接合烧结体6，结果，把基板侧电极23与芯片侧电极27相互接合起来。在加热工序中也可以施加负荷30，这种情况下，能够得到更加致密的接合烧结体6。
例如使用烘箱、回流炉、烧结炉等具有加热功能的设备来实施加热工序。也可以使用原来的热压或超声波焊接方式的设置在倒装芯片式装载设备内的加热装置。如果在含有大气压或大气压以上的氧气的气氛中实施加热工序，就能够促进分散剂3的去除，结果，能够提高接合可靠性。
按照如上工序，就得到了所要的电子元件装置21。
在以上说明的实施方式中，在各个基板侧电极23和芯片侧电极27的周围分别形成了围堰25和29。如前所述，这些围堰用来防止金属纳米粒子浆1的扩散。因此，例如在金属纳米粒子浆1因可润性的关系而不会扩散到布线基板22上的基板侧电极23以外的部分的情况下，就不特别需要围堰25。同样，在金属纳米粒子浆1不会扩散到芯片元件26上的芯片侧电极27以外的部分的情况下，就不特别需要围堰29。但是，尽管如此，在设置有围堰25和29的情况下，在图1(3)所示的压缩变形工序中能够更加确实且容易地使金属纳米粒子浆1压缩变形。在设置围堰25和29双方的情况下，上述的优点更加显著，即便是在仅仅设置某一方的情况下，也具备这种优点，仅仅程度的差别而已。
在上述的实施方式中形成的保护膜14和钝化膜28分别是用来保护布线基板22和芯片元件26的绝缘膜，但是可以根据需要来设置这些膜，不是必设的。
图4是表示本发明的第二实施方式的电子元件装置34的相当于图1(4)的示图。图4中，与图1(4)所示的要素相当的要素标注同样的参照符号，省略了重复的说明。
图4所示的电子元件装置34的特征在于在芯片侧电极27上形成有Au凸瘤35。因此，在制造该电子元件装置34时，在图1(2)所示的工序中，已经形成Au凸瘤35之后，把金属纳米粒子浆1施加在Au凸瘤35与基板侧电极23之间，再经Au凸瘤35和接合烧结体6把基板侧电极23与芯片侧电极27接合起来。
图5至图7是用来说明本发明的第三实施方式的示图。这里，图5是表示第三实施方式的电子元件装置38的相当于图1(4)的示图。图5中，与图1(4)所示的要素相当的要素标注同样的参照符号，省略了重复的说明。
图5所示的电子元件装置38的特征在于具备图1(4)所示的电子元件装置21所具备的全部要素，另外用层压树脂39把芯片元件26密封起来。为制造这样的电子元件装置38，实施图6所示的工序。
参照图6，准备层压密封用的未硬化状态的片状树脂40。另一方面，如图1(4)所示，在布线基板22和芯片元件26上的基板侧电极23和芯片侧电极27处于相互接合的状态。上述的未硬化状态的片状树脂40在压辊41的引导下覆盖住芯片元件26。压辊41相对于布线基板22沿箭头42方向移动，由此用片状树脂40依次把多个芯片元件26覆盖住。
上述的压辊41也用来对未硬化状态的片状树脂40朝布线基板22和芯片元件26方向施压，此时，如图5所示，片状树脂40的一部分进入到芯片元件26与布线基板22之间。为了容易地进入，最好一直加热到使片状树脂40的粘度达到最小的软化温度附近(通常为60～100℃)，来提高片状树脂40的流动性。为了使片状树脂40的上述进入更加容易，在例如数百至数千Pa左右的减压气氛下进行图6所示的工序也是有效的。
然后，使未硬化状态的片状树脂40硬化，由此形成图5所示的层压树脂39。
在对前述的片状树脂40施压的工序中，施加例如约0.1～5MPa的压力，由此使未硬化状态的片状树脂40的多余部分流动到芯片元件26的周围。此时，片状树脂40最薄部分的厚度即芯片元件26的上表面上的厚度最好没有离散。因此，在现有技术中实施图6所示的工序时，要严格控制压辊41的位置，然而，为了能够赋以均一的压力，通常压辊41具有柔性的材质，所以压辊41容易产生变形。因此，很难使片状树脂40的厚度即层压树脂39在芯片元件26的上表面上的厚度没有离散。
为解决该问题，在本实施方式中采取如下对策。
图7是相当于图5的A部分的部分的放大图。图7示出图5所示的层压树脂39处于未硬化状态的阶段即未硬化状态的片状树脂40的阶段。片状树脂40例如是环氧树脂那样的热硬化性或热可塑性树脂，如图7所示，包含粒径都等于或小于规定尺寸的填料43。填料43由例如二氧化硅构成，具有50体积％以上的含有率。
如上所述，由于片状树脂40含有填料43，所以在图6所示的压辊41的加压工序中，控制对片状树脂40的加压，以使片状树脂40的最薄部分的厚度取决于填料43的粒径。更具体地说，片状树脂40在芯片元件26的上表面上的厚度大体与填料43的最大粒径的粒子“43(A)”一致。结果，能够准确地控制片状树脂40在芯片元件26的上表面上的厚度。
图7中，虽然图示了片状树脂40的厚度大体与填料43的最大粒径的粒子“43(A)”一致，但是支配这样的厚度的填料43的粒径既可以是一次粒子的粒径，也可以是二次粒子的粒径。
图8是表示本发明的第四实施方式的电子元件装置46的相当于图1(4)的示图。图8中，与图1(4)所示的要素相当的要素标注同样的参照符号，省略了重复的说明。
图8所示的电子元件装置46的特征在于具备图1(4)所示的电子元件装置21所具备的全部要素，另外还具备底部填充树脂47。这样，为了形成底部填充树脂47，准备底部填充密封用的未硬化状态的树脂。另一方面，如图1(4)所示，实施把基板侧电极23与芯片侧电极27相互接合起来的工序。然后，在布线基板22和芯片元件26中的面积较小的一方的芯片元件26的至少周围施加上述的未硬化状态的树脂。由此，未硬化状态的树脂浸透到芯片元件26与布线基板22之间的间隙中。然后，使未硬化状态的树脂硬化就得到图8所示的电子元件装置46。
图9是用来说明本发明的第五实施方式的相当于图1的示图。图9中，与图1所示的要素相当的要素标注同样的参照符号，省略了重复的说明。
如图9(2)所示，该实施方式中，在布线基板51与芯片元件52相互对靠时包含相互面对的各个基板侧电极53a、53b、53c与各个芯片侧电极54a、54b、54c的间隔55a、55b、55c不相等的情况下，使用本实施方式最为有利。
上述的间隔55a～55c的不一致典型的情况是因布线基板51的制造过程中不可避免地产生的弯曲或起伏而导致的。即使芯片构件52侧也有可能产生不希望的变形。另外，间隔55a～55c的不一致不限于上述的不希望的事态引起的情况，也存在设计阶段已经预计到的情况。
该实施方式中，为了应对上述的间隔55a～55c的不一致，如图9(1)所示，在施加金属纳米粒子浆的工序中，将金属纳米粒子浆1的厚度56取为压缩变形极限厚度57(参照图9(3))加上间隔55a～55c中最大间隔55c与最小间隔55a之差的厚度以上。
如果说明具体数值的话，在图9(2)所示的已经对好位置的状态下，a.相互面对的基板侧电极53a与芯片侧电极54a的间隔为13μm、b.相互面对的基板侧电极53b与芯片侧电极54b的间隔为16μm、c.相互面对的基板侧电极53c与芯片侧电极54c的间隔为17μm，此时最大间隔为17μm，最小间隔为13μm，最大间隔与最小间隔之差为17μm-13μm＝4μm。
假设将在图9(3)所示的工序中压缩变形的金属纳米粒子浆1的压缩变形极限厚度为5μm。
这种情况下，在图9(1)所示的工序中施加的金属纳米粒子浆1的厚度56取为上述的差4μm加上压缩变形极限厚度5μm以上，即9μm以上。
施加具有上述的厚度56的金属纳米粒子浆1之后，在图9(3)所示的工序中，施以负荷30，位于基板侧电极53a与芯片侧电极54a之间的金属纳米粒子浆1被压缩变形直到压缩变形极限厚度57时，虽然分别位于其他基板侧电极53b和53c与芯片侧电极54b和54c之间的金属纳米粒子浆1还未达到压缩变形极限厚度57，但这样也能够可靠地使基板侧电极53b和53c与芯片侧电极54b和54c接触。因此，如图9(4)所示，经加热工序得到了所要的电子元件装置58时，基板侧电极53a～53c与芯片侧电极54a～54c之间的全部接合烧结体6都能够达到良好的接合状态。
以上结合图示的实施方式说明了本发明，但是在本发明的范围内可以有其他种种变形例。
例如，在图4所示的实施方式中展示的Au凸瘤35也可以分别用于图5、图8和图9所示的实施方式中。
在图示的实施方式中，第一电子元件是布线基板，第二电子元件是芯片元件，但是即便是其他电子元件的组合，也可以同等地使用本发明。

Claims (5)

1.一种电子元件装置的制造方法，具备如下工序：
准备具有第一电极的第一电子元件和具有第二电极的第二电子元件；
准备含有平均粒径1～100nm的金属纳米粒子、分散剂和分散媒质的金属纳米粒子浆；
在所述第一电极和所述第二电极的至少一方上施加所述金属纳米粒子浆的赋浆工序；
在将所述金属纳米粒子浆置入在所述第一电子元件和所述第二电子元件之间的状态下，使所述第一电子元件和所述第二电子元件相互对好位置，从而使所述第一电极和所述第二电极相互面对；
在使所述第一电子元件和所述第二电子元件相互接近的方向上施加负荷，从而使处于所述第一电极和所述第二电极间的所述金属纳米粒子浆压缩变形至其压缩变形极限厚度；
在等于或高于能够除掉含在所述金属纳米粒子浆内的所述分散剂和所述分散媒质的温度而低于构成所述金属纳米粒子的金属的熔点的温度下加热，由此来烧结所述金属纳米粒子，从而使所述第一电极和所述第二电极相互接合；
其特征在于，还具备如下工序：准备层压密封用的未硬化状态的片状树脂；在使所述第一电极和所述第二电极相互接合的工序后，用所述未硬化状态的片状树脂覆盖所述第一电子元件和所述第二电子元件的任一方；朝所述第一电子元件和所述第二电子元件方向对所述未硬化状态的片状树脂加压；使所述未硬化状态的片状树脂硬化；
所述片状树脂含有粒径都等于或小于规定尺寸的填料，在对所述未硬化状态的片状树脂加压的工序中，控制对所述片状树脂的加压，以使覆盖所述第一电子元件和所述第二电子元件的任一方的所述片状树脂的最薄部分的厚度取决于填料的粒径。
2.根据权利要求1所述的电子元件装置的制造方法，其特征在于所述第一电子元件具有多个所述第一电极，所述第二电子元件具有多个所述第二电极，在使所述第一电子元件和所述第二电子元件相互对好位置时，相互面对的各所述第一电极和所述第二电极的各个间隔存在互不相等的情况，在所述赋浆工序中所施加的所述金属纳米粒子浆的厚度等于或大于所述压缩变形极限厚度加上所述间隔的最大值与最小值之差的厚度。
3.根据权利要求1所述的电子元件装置的制造方法，其特征在于在所述第一电极的周围形成用来防止所述金属纳米粒子浆扩散的围堰。
4.根据权利要求1所述的电子元件装置的制造方法，其特征在于在所述第二电极的周围形成用来防止所述金属纳米粒子浆扩散的围堰。
5.根据权利要求1至4任一项所述的电子元件装置的制造方法，其特征在于还具备如下工序：准备底部填充密封用的未硬化状态的树脂；在使所述第一电极和所述第二电极相互接合的工序后，把所述未硬化状态的树脂施加到所述第一电子元件和所述第二电子元件中面积较小的一方的至少周围；使所述未硬化状态的树脂硬化。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1692552A (zh) * 2002-10-04 2005-11-02 东洋通信机株式会社 表面安装声表面波器件制造方法
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
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JP3827569B2 (ja) * 2001-12-06 2006-09-27 旭化成エレクトロニクス株式会社 微細パターン接続用回路部品およびその形成方法
JP2004128357A (ja) * 2002-10-04 2004-04-22 Ebara Corp 電極配設基体及びその電極接合方法
JP2005116612A (ja) * 2003-10-03 2005-04-28 Murata Mfg Co Ltd フリップチップ実装方法およびこの方法を用いた電子回路装置
JP4362742B2 (ja) * 2005-09-22 2009-11-11 ニホンハンダ株式会社 ペースト状金属粒子組成物の固化方法、金属製部材の接合方法およびプリント配線板の製造方法
CN101479839A (zh) * 2006-04-24 2009-07-08 株式会社村田制作所 电子元件、使用该电子元件的电子元件装置及其制造方法
JP4361572B2 (ja) * 2007-02-28 2009-11-11 株式会社新川 ボンディング装置及び方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1692552A (zh) * 2002-10-04 2005-11-02 东洋通信机株式会社 表面安装声表面波器件制造方法
CN1819172A (zh) * 2005-01-20 2006-08-16 日产自动车株式会社 半导体装置及其制造方法

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