CN101872740B - Soi衬底的制造方法 - Google Patents

Soi衬底的制造方法 Download PDF

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Publication number
CN101872740B
CN101872740B CN201010167278.XA CN201010167278A CN101872740B CN 101872740 B CN101872740 B CN 101872740B CN 201010167278 A CN201010167278 A CN 201010167278A CN 101872740 B CN101872740 B CN 101872740B
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China
Prior art keywords
substrate
heat treatment
bonded substrate
bonded
manufacturing
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Expired - Fee Related
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CN201010167278.XA
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English (en)
Chinese (zh)
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CN101872740A (zh
Inventor
花冈一哉
津屋英树
永井雅晴
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H10P90/1916—Preparing SOI wafers using bonding with separation or delamination along an ion implanted layer, e.g. Smart-cut
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3238—Materials thereof being insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Recrystallisation Techniques (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
CN201010167278.XA 2009-04-22 2010-04-20 Soi衬底的制造方法 Expired - Fee Related CN101872740B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2009104203 2009-04-22
JP2009-104203 2009-04-22

Publications (2)

Publication Number Publication Date
CN101872740A CN101872740A (zh) 2010-10-27
CN101872740B true CN101872740B (zh) 2014-05-07

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CN201010167278.XA Expired - Fee Related CN101872740B (zh) 2009-04-22 2010-04-20 Soi衬底的制造方法

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US (2) US8168481B2 (https=)
JP (1) JP5721962B2 (https=)
KR (1) KR101752350B1 (https=)
CN (1) CN101872740B (https=)
SG (2) SG183670A1 (https=)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
SG178179A1 (en) * 2009-10-09 2012-03-29 Semiconductor Energy Lab Reprocessing method of semiconductor substrate, manufacturing method of reprocessed semiconductor substrate, and manufacturing method of soi substrate
JP5752264B2 (ja) * 2010-12-27 2015-07-22 シャンハイ シングイ テクノロジー カンパニー リミテッドＳｈａｎｇｈａｉ Ｓｉｍｇｕｉ Ｔｅｃｈｎｏｌｏｇｙ Ｃｏ．， Ｌｔｄ 不純物のゲッタリングプロセスで絶縁層付きの半導体基板を製造する方法
US8735263B2 (en) 2011-01-21 2014-05-27 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
JP2013093434A (ja) * 2011-10-26 2013-05-16 Semiconductor Energy Lab Co Ltd 半導体基板の解析方法
JPWO2013105634A1 (ja) 2012-01-12 2015-05-11 信越化学工業株式会社 熱酸化異種複合基板及びその製造方法
US8879275B2 (en) * 2012-02-21 2014-11-04 International Business Machines Corporation Anti-corrosion conformal coating comprising modified porous silica fillers for metal conductors electrically connecting an electronic component
EP2879177B1 (en) * 2012-07-25 2020-08-19 Shin-Etsu Chemical Co., Ltd. Method for producing sos substrates, and sos substrate
US9196503B2 (en) * 2012-08-23 2015-11-24 Michael Xiaoxuan Yang Methods for fabricating devices on semiconductor substrates
AU2014228794B2 (en) 2013-03-15 2019-04-18 The Regents Of The University Of California Multi-site transcutaneous electrical stimulation of the spinal cord for facilitation of locomotion
US10190235B2 (en) * 2013-05-24 2019-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer supporting structure and method for forming the same
US10137299B2 (en) 2013-09-27 2018-11-27 The Regents Of The University Of California Engaging the cervical spinal cord circuitry to re-enable volitional control of hand function in tetraplegic subjects
KR102306979B1 (ko) * 2014-04-01 2021-09-30 에베 그룹 에. 탈너 게엠베하 기질의 표면 처리를 위한 방법 및 장치
US9425063B2 (en) * 2014-06-19 2016-08-23 Infineon Technologies Ag Method of reducing an impurity concentration in a semiconductor body, method of manufacturing a semiconductor device and semiconductor device
US11097122B2 (en) 2015-11-04 2021-08-24 The Regents Of The University Of California Magnetic stimulation of the spinal cord to restore control of bladder and/or bowel
US11235154B2 (en) 2017-02-17 2022-02-01 The University Of British Columbia Apparatus and methods for maintaining physiological functions
WO2018217791A1 (en) 2017-05-23 2018-11-29 The Regents Of The University Of California Accessing spinal networks to address sexual dysfunction
DE20168827T1 (de) 2017-06-30 2021-01-21 Gtx Medical B.V. System zur neuromodulierung
US12357828B2 (en) 2017-12-05 2025-07-15 Ecole Polytechnique Federale De Lausanne (Epfl) System for planning and/or providing neuromodulation
ES3058711T3 (en) 2017-12-05 2026-03-12 Ecole Polytechnique Fed Lausanne Epfl A system for planning and/or providing neuromodulation
JP2021534877A (ja) 2018-08-23 2021-12-16 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニアThe Regents Of The University Of California 神経根麻痺、馬尾症候群、及び上肢機能の回復のための非侵襲性脊髄刺激
DE18205817T1 (de) 2018-11-13 2020-12-24 Gtx Medical B.V. Sensor in bekleidung von gliedmassen oder schuhwerk
ES2911465T3 (es) 2018-11-13 2022-05-19 Onward Medical N V Sistema de control para la reconstrucción y/o restauración del movimiento de un paciente
EP3695878B1 (en) 2019-02-12 2023-04-19 ONWARD Medical N.V. A system for neuromodulation
DE19211698T1 (de) 2019-11-27 2021-09-02 Onward Medical B.V. Neuromodulation system
EP3827875B1 (en) 2019-11-27 2023-07-05 ONWARD Medical N.V. Neuromodulation system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308782A (zh) * 2007-05-18 2008-11-19 株式会社半导体能源研究所 Soi衬底的制造方法、以及半导体装置的制造方法

Family Cites Families (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2550371A1 (de) * 1975-11-10 1977-05-12 Ibm Deutschland Verfahren zum thermischen oxydieren von silicium
FR2681472B1 (fr) * 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2715501B1 (fr) * 1994-01-26 1996-04-05 Commissariat Energie Atomique Procédé de dépôt de lames semiconductrices sur un support.
JP4103968B2 (ja) * 1996-09-18 2008-06-18 株式会社半導体エネルギー研究所 絶縁ゲイト型半導体装置
US6534380B1 (en) * 1997-07-18 2003-03-18 Denso Corporation Semiconductor substrate and method of manufacturing the same
US6388652B1 (en) * 1997-08-20 2002-05-14 Semiconductor Energy Laboratory Co., Ltd. Electrooptical device
US6686623B2 (en) * 1997-11-18 2004-02-03 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile memory and electronic apparatus
TW508378B (en) * 1998-03-09 2002-11-01 Shinetsu Handotai Kk A method for producing a silicon single crystal wafer and a silicon single crystal wafer
JPH11307747A (ja) * 1998-04-17 1999-11-05 Nec Corp Ｓｏｉ基板およびその製造方法
JP3500063B2 (ja) * 1998-04-23 2004-02-23 信越半導体株式会社 剥離ウエーハを再利用する方法および再利用に供されるシリコンウエーハ
US6162708A (en) * 1998-05-22 2000-12-19 Shin-Etsu Handotai Co., Ltd. Method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer
JP2000012864A (ja) * 1998-06-22 2000-01-14 Semiconductor Energy Lab Co Ltd 半導体装置の作製方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
JP4476390B2 (ja) * 1998-09-04 2010-06-09 株式会社半導体エネルギー研究所 半導体装置の作製方法
JP2000349264A (ja) * 1998-12-04 2000-12-15 Canon Inc 半導体ウエハの製造方法、使用方法および利用方法
JP2000349266A (ja) 1999-03-26 2000-12-15 Canon Inc 半導体部材の製造方法、半導体基体の利用方法、半導体部材の製造システム、半導体部材の生産管理方法及び堆積膜形成装置の利用方法
JP4379943B2 (ja) 1999-04-07 2009-12-09 株式会社デンソー 半導体基板の製造方法および半導体基板製造装置
JP2001144275A (ja) * 1999-08-27 2001-05-25 Shin Etsu Handotai Co Ltd 貼り合わせｓｏｉウエーハの製造方法および貼り合わせｓｏｉウエーハ
KR100682190B1 (ko) * 1999-09-07 2007-02-12 동경 엘렉트론 주식회사 실리콘 산질화물을 포함하는 절연막의 형성 방법 및 장치
KR100730806B1 (ko) * 1999-10-14 2007-06-20 신에쯔 한도타이 가부시키가이샤 Ｓｏｉ웨이퍼의 제조방법 및 ｓｏｉ 웨이퍼
JP3943782B2 (ja) * 1999-11-29 2007-07-11 信越半導体株式会社 剥離ウエーハの再生処理方法及び再生処理された剥離ウエーハ
JP2002110949A (ja) * 2000-09-28 2002-04-12 Canon Inc Ｓｏｉの熱処理方法及び製造方法
US7119365B2 (en) * 2002-03-26 2006-10-10 Sharp Kabushiki Kaisha Semiconductor device and manufacturing method thereof, SOI substrate and display device using the same, and manufacturing method of the SOI substrate
JP4772258B2 (ja) 2002-08-23 2011-09-14 シャープ株式会社 Ｓｏｉ基板の製造方法
JP2004134675A (ja) 2002-10-11 2004-04-30 Sharp Corp Ｓｏｉ基板、表示装置およびｓｏｉ基板の製造方法
US7508034B2 (en) * 2002-09-25 2009-03-24 Sharp Kabushiki Kaisha Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device
JP4699675B2 (ja) * 2002-10-08 2011-06-15 信越半導体株式会社 アニールウェーハの製造方法
JP2004193515A (ja) * 2002-12-13 2004-07-08 Shin Etsu Handotai Co Ltd Ｓｏｉウエーハの製造方法
US6809370B1 (en) * 2003-07-31 2004-10-26 Texas Instruments Incorporated High-k gate dielectric with uniform nitrogen profile and methods for making the same
US7052978B2 (en) * 2003-08-28 2006-05-30 Intel Corporation Arrangements incorporating laser-induced cleaving
JP5110772B2 (ja) 2004-02-03 2012-12-26 株式会社半導体エネルギー研究所 半導体薄膜層を有する基板の製造方法
JP2006294737A (ja) * 2005-04-07 2006-10-26 Sumco Corp Ｓｏｉ基板の製造方法及びその製造における剥離ウェーハの再生処理方法。
JP4715470B2 (ja) 2005-11-28 2011-07-06 株式会社Sumco 剥離ウェーハの再生加工方法及びこの方法により再生加工された剥離ウェーハ
EP1835533B1 (en) * 2006-03-14 2020-06-03 Soitec Method for manufacturing compound material wafers and method for recycling a used donor substrate
FR2899380B1 (fr) 2006-03-31 2008-08-29 Soitec Sa Procede de revelation de defauts cristallins dans un substrat massif.
JP5314838B2 (ja) * 2006-07-14 2013-10-16 信越半導体株式会社 剥離ウェーハを再利用する方法
EP1978554A3 (en) * 2007-04-06 2011-10-12 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate comprising implantation and separation steps
JP5289805B2 (ja) * 2007-05-10 2013-09-11 株式会社半導体エネルギー研究所 半導体装置製造用基板の作製方法
US20090004764A1 (en) * 2007-06-29 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing SOI substrate and method for manufacturing semiconductor device
KR101499175B1 (ko) * 2007-10-04 2015-03-05 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 제조방법
JP2009272471A (ja) * 2008-05-08 2009-11-19 Sumco Corp 貼り合わせウェーハの製造方法
US20100022070A1 (en) * 2008-07-22 2010-01-28 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101308782A (zh) * 2007-05-18 2008-11-19 株式会社半导体能源研究所 Soi衬底的制造方法、以及半导体装置的制造方法

Also Published As

Publication number Publication date
US8168481B2 (en) 2012-05-01
JP5721962B2 (ja) 2015-05-20
US20100273310A1 (en) 2010-10-28
SG166060A1 (en) 2010-11-29
CN101872740A (zh) 2010-10-27
US8486772B2 (en) 2013-07-16
JP2010272851A (ja) 2010-12-02
SG183670A1 (en) 2012-09-27
US20120208348A1 (en) 2012-08-16
KR101752350B1 (ko) 2017-06-29
KR20100116536A (ko) 2010-11-01

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